#Note: For normal mode, the clock is referred to input pfl_clk clock(clk_50m_max5) of PFL II IP.
#If burst mode is used, the clock is referred to flash clock of PFL II IP.
set_output_delay -add_delay -max -clock [get_clocks {clk_50m_max5}] \
$flash_out_max_dly [get_ports {flash_nce[0] flash_nce[1] flash_noe flash_nwe flash_addr[*] flash_data[*]}]
set_output_delay -add_delay -min -clock [get_clocks {clk_50m_max5}] \
$flash_out_min_dly [get_ports { flash_nce[0] flash_nce[1] flash_noe flash_nwe flash_addr[*] flash_data[*]}]
#Only need to constraint flash_advn pin when using burst mode.
set_output_delay -add_delay -max -clock [get_clocks { FLASH_CLK }] $flash_out_max_dly [get_ports {flash_nadv}]
set_output_delay -add_delay -min -clock [get_clocks { FLASH_CLK }] $flash_out_min_dly [get_ports {flash_nadv}]
Example 9. Set input delay for input pins
Example below sets the input delay for CFI flash data.
# For Normal Mode
set flash_noe_tracemax 0.250
set flash_noe_tracemin 0.000
set flash_tco_max 7.000
set flash_tco_min 0.000
set normal_in_max_dly [expr $flash_data_tr $flash_t $ flash_noe_tracemax]
set normal_in_min_dly [expr $flash_data_tr $flash_t $ flash_noe_tracemin]
set_input_delay -clock { clk_50m_max5 } -max $normal_in_max_dly [get_ports {flash_data[*]}]
set_input_delay -clock { clk_50m_max5 } -min $normal_in_min_dly [get_ports {flash_data[*]}]
# For Burst mode
set flash_tco_max 5.500
set flash_tco_min 2.000
set burst_in_max_dly [expr $flash_data_tr $flash_t $flash_clk_tracemax]
set burst_in_min_dly [expr $flash_data_tr $flash_t $flash_clk_tracemin]
set_input_delay -clock { FLASH_CLK } -max $burst_in_max_dly [get_ports {flash_data[*]}]
set_input_delay -clock { FLASH_CLK } -min $burst_in_min_dly [get_ports {flash_data[*]}]
3.1.7.4.4. PFL II IP Recommended Constraints for Other Input Pins
Example 10. Set a false path for PFL II IP input pins
You can set the
pfl_nreset
input reset pin to a false path since this pin is asynchronous.
set_false_path -from [get_ports {pfl_nreset}] -to *
3. Intel Agilex Configuration Schemes
683673 | 2021.10.29
Intel
®
Agilex
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Configuration User Guide
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