Note: For Avalon-ST x16 and x32 configuration schemes the host must drive
nCONFIG
low until it samples
nSTATUS
low.
If the host fails to drive
nCONFIG
low until it samples
nSTATUS
low there is a chance that configuration may fail.
3. When the external host drives
nCONFIG
signal high, the SDM initiates configuration. The SDM drives the
nSTATUS
signal
high, signaling the beginning of FPGA configuration. The SDM receives the configuration bitstream on the interface that
the
MSEL
bus specified in Step 1. Throughout the configuration, it is possible for
AVST_READY
to deassert which would
require
AVST_VALID
to deassert within six cycles.
4. The SDM drives the
CONF_DONE
signal high, indicating the SDM received the bitstream successfully.
5. When the Intel Agilex device asserts
INIT_DONE
to indicate the FPGA has entered user mode. GPIO pins exit the high
impedance state. The time between the assertion of
CONF_DONE
and
INIT_DONE
is variable. For FPGA First configuration,
INIT_DONE
asserts after initialization of the FPGA fabric, including registers and state machines. For HPS first
configuration, the HPS application controls the time between
CONF_DONE
and
INIT_DONE
.
INIT_DONE
does not assert
until after the software running on the HPS such as U-Boot or the operating system (OS) initiates the configuration, the
FPGA configures and enters user mode.
The entire device does not enter user mode simultaneously. Intel requires you to include reset release as described in the
Including the Reset Release Intel FPGA IP in Your Design
on page 134. Use the
nINIT_DONE
output of the Reset Release
Intel FPGA IP to hold your application logic in the reset state until the entire FPGA fabric is in user mode. Failure to include
this IP in your design may result in intermittent application logic failures.
Reconfiguration Timing
The second event in the timing diagram illustrates the Intel Agilex device reconfiguration. If you change the
MSEL
setting
after power-on, you must power-cycle the Intel Agilex. Power cycling forces the SDM to sample the
MSEL
pins before
reconfiguring the device.
The numbers in the Reconfiguration part of the timing diagram mark the following events:
1. The external host drives
nCONFIG
signal low.
nCONFIG
signal must be held low until the device drives the
nSTATUS
signal low.
2. The SDM initiates device cleaning.
3. The SDM drives the
nSTATUS
signal low when device cleaning is complete.
4. The external host drives the
nCONFIG
signal high to initiate reconfiguration.
5. The SDM drives the
nSTATUS
signal high signaling the device is ready for reconfiguration and starts to reconfigure.
Note: If you do not monitor the
nSTATUS
signal, pulse the
nCONFIG
signal low for at least 1000 ms to initiate a
reconfiguration request.
2. Intel Agilex Configuration Details
683673 | 2021.10.29
Intel
®
Agilex
™
Configuration User Guide
20
