2. Intel Agilex Configuration Details
2.1. Intel Agilex Configuration Timing Diagram
Figure 4.
Power-On, Configuration, and Reconfiguration Timing Diagram
nCONFIG
nSTATUS
CONF_DONE
INIT_DONE
nINIT_DONE
MSEL[2:0]
Data[
<n>
-1:0](Generic)
AVST_READY (Avalon ST only)
AVST_VALID (Avalon ST only)
AS_CS0 (AS only)
Configuration_State
Power_Supply_Status[7:0]
GPIO Status
Power-On Reset
User Mode
Reconfiguration Triggered
Reconfiguration
Idle
Configuration
Initialization
User Mode
Idle
Configuration
Sample
Power On SDM Start
Device Clean
Group 1
Supply Up
Group 2
Supply Up
Group 3
Supply Up
Tri-Stated with Weak Pull-Up
User Defined
1
2
3
4
5
1
3
5
4
2
(weak int/ext pullup)
(internal signal)
Tri-Stated with Weak Pull-Up
Initialization
User Mode
User Defined
...
...
...
...
...
...
...
...
Note:
(1) All I/O pins in SDM and HPS bank except the VSIGP_0, VSIGN_0, VSIGP_1, VSIGN_1, and RREF_SDM pins are in undetermined state during device power up and power down.
Input signals of an I/O pin at any point during the power up and power down should not exceed the I/O buffer power supply rail of the bank. When using pin in the GPIO bank with 1.5V VCCIO_PIO, the pin voltage must
not exceed the VCCIO_PIO rail or 1.2V, whichever is lower.
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
683673 | 2021.10.29
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