3.1.7.4.5. PFL II IP Recommended Constraints for Other Output Pins
Example 15. Set output delay to PFL II IP output pins
Example below sets the output delay for the
pfl_flash_access_request
output pin.
•
You don't have to constraint the path when this signal feeds arbiter logic or device tristate logic,
•
You don't have to constraint the path when this signal feeds the
pfl_flash_access_granted
input pin while not using
the device arbiter logic or the external processor.
•
You can constraint the path when this signal feeds the processor or an external device controls.
set_output_delay -add_delay -clock [get_clocks { clk_50m_sysmax }] \
-max $flash_access_request_tracemax [get_ports {pfl_flash_access_request}]
set_output_delay -add_delay -clock [get_clocks { clk_50m_sysmax }] \
-min $flash_access_request_tracemin [get_ports {pfl_flash_access_request}]
Example 16. Set output delay to
flash_nreset
output pin
The
flash_nreset
output pin is available in Burst mode only.
set_output_delay -add_delay -max -clock [get_clocks { FLASH_CLK }] $flash_out_max_dly [get_ports {flash_nreset}]
set_output_delay -add_delay -min -clock [get_clocks { FLASH_CLK }] $flash_out_min_dly [get_ports {flash_nreset}]
Example 17. Set a false path for
fpga_nconfig
output pin
You can set the
fpga_nconfig
output pin to a false path since the
nCONFIG
is an asynchronous input pin..
set_false_path -from [get_ports {fpga_nconfig}] -to *
Example 18. Set output delay to
pfl_watchdog_error
output pin
•
You don't have to constraint the path when the signal feeds the internal logic.
•
You can constraint the path when signal feeds an external host.
set_output_delay -add_delay -clock [get_clocks { clk_50m_sysmax }] \
-max $pfl_watchdog_error_tracemax [get_ports {pfl_watchdog_error}]
set_output_delay -add_delay -clock [get_clocks { clk_50m_sysmax }] \
-min $pfl_watchdog_error_tracemin [get_ports {pfl_watchdog_error}]
3. Intel Agilex Configuration Schemes
683673 | 2021.10.29
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Configuration User Guide
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