3.2.11. Debugging Guidelines for the AS Configuration Scheme
The AS configuration scheme operation is like earlier device families. However, there is one significant difference. Intel Agilex
devices using AS mode, try to load a firmware section from addresses 0, 512k, 1024k and 1536k in the serial flash device
connected to the CS0 pin.
If the configuration bitstream does not include a valid image, the SDM asserts an error by driving
nSTATUS
low. You can
recover from the error by reconfiguring the FPGA over JTAG, or by driving
nCONFIG
low.
SDM tristates AS pins,
AS_CLK
,
AS_nRST
,
AS_DATA0
-
AS_DATA3
, and
AS_nCSO0
-
AS_nCSO3
, only when the device powers on
if you set
MSEL
to JTAG. If
MSEL
is either AS fast or normal, the SDM drives the AS pins until you power cycle the Intel Agilex
device. Unlike earlier device families, the AS pins are not tristated when the device enters user mode.
The AS configuration scheme has power-on requirements. If you use AS Fast mode, you must ramp all power supplies to the
recommended operating condition within 10 ms. This ramp-up requirement ensures that the AS x4 device is within its
operating voltage range when the Intel Agilex device begins accessing the AS x4 device.
When using AS fast mode, all power supplies to the Intel Agilex device must be fully ramped-up to the recommended
operating conditions before the SDM releases from reset. To meet the PCIe 100 ms power-up-to-active time requirement for
CvP, all the power supplies to the Intel Agilex device must be at the recommended operating range within 10 ms.
Debugging Suggestions
Here are some debugging tips for the AS configuration scheme:
•
Ensure that the design meets the power-supply ramp requirements for fast AS mode. If using fast mode, all power
supplies must ramp to the recommended operating condition within 10 ms.
•
Ensure that the flash is powered up and ready to be accessed when the Intel Agilex device exits power-on reset.
•
If you are using an external clock source for configuration, ensure the
OSC_CLK_1
pin is fed correctly, and the frequency
matches the frequency you set for the
OSC_CLK_1
in your Intel Quartus Prime Pro Edition project.
•
Ensure the
MSEL
pins reflect the correct AS configuration scheme.
3. Intel Agilex Configuration Schemes
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Configuration User Guide
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