Figure 56.
Using nINIT_DONE to Gate the PLL_Reset Signal
nCONFIG
nSTATUS
INIT_DONE
nINIT_DONE
PLL_Reset
Clock
PLL_Lock
Another alternative if you are using
PLL_Lock
in your reset sequence is to gate the
PLL_Lock
output with the
nINIT_DONE
signal,
(PLL_Lock && !nINIT_DONE)
.
4.4. Guidance When Using Partial Reconfiguration (PR)
The PR Region Controller IP provides reset logic that ensures that the static region of the device and the PR personas do not
interact during PR.
The Reset Release IP is only necessary to manage reset for full FPGA core configuration and subsequent full FPGA core
reconfigurations. The Reset Release IP is not necessary to prevent interaction between the static and PR personas during the
PR process. For more information about PR refer to the Intel Quartus Prime Pro Edition User Guide: Partial Reconfiguration.
Related Information
Creating a Partial Reconfiguration Design
4.5. Detailed Description of Device Configuration
Each Local Sector Manager (LSM) configures its own sector. A sector comprises multiple logic array block (LAB) rows. A logical
function can span multiple rows and multiple sectors.
4. Including the Reset Release Intel FPGA IP in Your Design
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