Power-On
•
The Intel Agilex power supplies follow the guidelines in the Power-Up Sequence Requirements for Intel Agilex Devices
section of the Intel Agilex Power Management User Guide.
•
A device-wide power-on reset (POR) asserts after the power supplies reach the correct operating voltages. The external
power supply ramp must not be slower than the minimum ramping rate until the supplies reach the operating voltage.
•
During power-on stage, internal circuitry pulls the
SDM_IO0
,
SDM_IO8
, and
SDM_IO16
low internally. Internal circuitry
pulls the remaining
SDM_IO
pins to a weak high.
•
After POR, internal circuitry also pulls all GPIO pins to a weak high until the device enters user mode.
•
All I/O pins in SDM and HPS bank except the
VSIGP_0
,
VSIGN_0
,
VSIGP_1
,
VSIGN_1
, and
RREF_SDM
pins are in
undetermined state during device power up and power down.
•
Input signals of an I/O pin at any point during the power up and power down should not exceed the I/O buffer power
supply rail of the bank. When using pin in the GPIO bank with 1.5V
VCCIO_PIO
, the pin voltage must not exceed the
VCCIO_PIO
rail or 1.2V, whichever is lower.
SDM Startup
•
The SDM samples the
MSEL
pins during power-on.
•
If
MSEL
is set to JTAG, the SDM remains in the Startup state.
•
The SDM runs firmware stored in the on-chip boot ROM and enters the Idle state until the host drives
nCONFIG
high. The
host should not drive
nCONFIG
high before all clocks are stable.
Idle
•
The SDM remains in IDLE state until the external host initiates configuration by driving the
nCONFIG
pin from low to high.
Alternatively, the SDM enters the idle state after it exits the error state.
FPGA Configuration
•
After the SDM receives a configuration initiation request (
nCONFIG = HIGH
), the SDM signals the beginning of
configuration by driving the
nSTATUS
pin high.
•
Upon receiving configuration data, the SDM performs authentication, decryption and decompression.
•
The
nCONFIG
pin remains high during configuration and in user mode. The host monitors the
nSTATUS
pin continuously
for configuration errors.
2. Intel Agilex Configuration Details
683673 | 2021.10.29
Intel
®
Agilex
™
Configuration User Guide
24
