Table 1.
Intel Agilex Configuration Scheme, Data Width, and MSEL
Configuration Scheme
Data Width (bits)
MSEL[2:0]
Passive
Avalon-ST
32
000
16
101
8
110
JTAG
1
111
Configuration via Protocol (CvP)
x8, x16 lanes
(1)
001
(2)
Active
AS - fast mode
4
001
AS - normal mode
4
011
Avalon-ST
The Avalon-ST configuration scheme is a passive configuration scheme. Avalon-ST is the fastest configuration scheme for Intel
Agilex devices. Avalon-ST configuration supports x8, x16, and x32 modes. The x16 and x32 bit modes use general-purpose
I/Os (GPIOs) for configuration. The x8 bit mode uses dedicated SDM I/O pins.
Note:
The
AVST_data[15:0]
,
AVST_data[31:0]
,
AVST_clk
, and
AVST_valid
use dual-purpose GPIOs which operate at 1.2 V.
You can use these pins as regular I/Os after the device enters user mode.
Avalon-ST supports backpressure using the
AVST_READY
and
AVST_VALID
pins. Because the time to decompress the
incoming bitstream varies, backpressure support is necessary to transfer data to the Intel Agilex device. For more information
about the Avalon-ST refer to the Avalon Interface Specifications.
JTAG
You can configure the Intel Agilex device using the dedicated JTAG pins. The JTAG port provides seamless access to many
useful tools and functions. In addition to configuring the Intel Agilex, you use the JTAG port for debugging with Signal Tap or
the System Console tools.
(1)
For more information, refer to the Intel FPGA P-Tile Avalon Streaming (Avalon -ST) IP for PCI Express* User Guide and the Intel
Agilex Configuration via Protocol (CvP) Implementation User Guide.
(2)
Before you can use CvP you must configure either the periphery image or full image configuration via the AS scheme. Then you can
configure the core image using CvP.
1. Intel
®
Agilex
™
Configuration User Guide
683673 | 2021.10.29
Intel
®
Agilex
™
Configuration User Guide
7
