4.5.1. Device Initialization
The following steps summarize device initialization:
1. An external host drives a configuration request to the Secure Device Manager (SDM) by driving
nCONFIG
high. The SDM
exits the IDLE state and signals the beginning of configuration by driving
nSTATUS
high and driving configuration data.
2. The SDM asserts
CONF_DONE
indicating that the Intel FPGA has successfully received all the configuration data.
3. The SDM uses the configuration logic to start non-gated clocks in the fabric. Intel Hyperflex
™
registers begin shifting data.
Consequently, the initial conditions of Intel Hyperflex registers can be random. Use the Disable Register Power-up
Initialization setting in the Intel Quartus Prime Configuration dialog box to disable Intel Hyperflex register initialization
during power-on as explained below.
4. The SDM uses the configuration logic to enable and initialize user registers in the LABs, DSP, and embedded memory
blocks.
5. The SDM drives
INIT_DONE
to indicate that the device has fully entered user mode. The Reset Release IP asserts
nINIT_DONE
. Intel recommends that you use
nINIT_DONE
to gate your reset logic.
6. The FPGA is now in user mode and ready for operation.
4.5.2. Preventing Register Initialization During Power-On
If not held in reset, both ALM and Intel Hyperflex registers may lose their initial state if they initialize before their respective
source.
You can prevent registers from initializing during power-on by enabling an option in the Intel Quartus Prime software.
Complete the following steps to turn on this option:
1. On the Assignments menu select Device
➤
Device and Pin Options
➤
Configuration.
2. In the Configuration dialog box, turn on Disable Register Power-up Initialization.
4. Including the Reset Release Intel FPGA IP in Your Design
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