Document Version
Intel Quartus
Prime Version
Changes
• Removed
CONF_DONE
configuration function from the Required Configuration Signals for the AS Configuration Scheme
table.
• Added
.rpd
programming file in the Output File Types table in the AS Configuration Scheme Hardware Components and
File Types.
• Revised JTAG Configuration
• Removed QSF Assignment for AS topic.
• Added video describing reset importance in the Including the Reset Release Intel FPGA IP in Your Design.
• Revised attention note in Understanding the Reset Release IP Requirement.
• Added important note about the RSU SDM Command Use Case in Operation Commands.
• Revised Command List and Description table. Updated description for:
—
CONFIG_STATUS
—
RSU_STATUS
• Added new topic: Generating the Initial RSU Image Using
.rbf
Files
• Corrected minor errors and spelling mistakes.
2021.06.21
21.2
Made the following changes:
• Added a CvP-related note in the Intel Agilex Configuration Overview.
• Revised block diagram descriptions in the Intel Agilex Configuration Architecture.
• Revised Intel Agilex Configuration Timing Diagram.
— Added a note in the Reconfiguration Timing section.
— Re-ordered sections for clarity.
• Revised Intel Agilex Configuration Flow Diagram section.
— Renamed Power Up section to Power-On to align the description with figure.
— Merged Configuration Start and Configuration Pass sections into the FPGA Configuration section.
— Renamed Configuration Error section to Failed FPGA Configuration.
— Minor re-ordered sections for clarity.
— Removed JTAG Configuration section. Reposition the existing JTAG configuration note.
— Moved device response content to a new section: Device Response to Configuration and Reset Events.
• Removed
DATA UNLOCK
signal from the Available SDM I/O Pin Assignments for Configuration Signals that Do Not Use
Dedicated SDM I/O Pins.
DATA UNLOCK
is not available for Intel Agilex devices.
• Revised text and figure in SDM I/O Pins for Power Management and SmartVID
• Revised
OSC_CLK_1
requirements in OSC_CLK_1 Clock Input
• Added new topic: Intel Agilex Configuration Time Estimation
• Added new PFL II IP-related topics:
— PFL II IP Recommended Constraints for Other Input Pins
— PFL II IP Recommended Constraints for Other Output Pins
continued...
9. Document Revision History for the Intel Agilex Configuration User Guide
683673 | 2021.10.29
Intel
®
Agilex
™
Configuration User Guide
219
