Intel 8XC251SA, User Manual

Page: 397 / 458

B-5
SIGNAL DESCRIPTIONS
RST I Reset. Reset input to the chip. Holding this pin high for 64 oscillator
periods while the oscillator is running resets the device. The port
pins are driven to their reset conditions when a voltage greater than
V
IH1
is applied, whether or not the oscillator is running. This signal
has a Schmitt trigger input. Connecting the RST pin to V
CC
through
a capacitor provides power-on reset.
Asserting RST when the chip is in idle mode or powerdown mode
returns the chip to normal operation.
—
RXD I/O Receive Serial Data. RXD sends and receives data in serial I/O
mode 0 and receives data in serial I/O modes 1, 2, and 3. P3.0
T1:0 I Timer 1:0 External Clock Inputs. When timer 1:0 operates as a
counter, a falling edge on the T1:0 pin increments the count. P3.5:4
T2 I/O Timer 2 Clock Input/Output. For the timer 2 capture mode, this
signal is the external clock input. For the clock-out mode, it is the
timer 2 clock output. P1.0
T2EX I Timer 2 External Input. In timer 2 capture mode, a falling edge
initiates a capture of the timer 2 registers. In auto-reload mode, a
falling edge causes the timer 2 registers to be reloaded. In the up-
down counter mode, this signal determines the count direction: 1 =
up, 0 = down. P1.1
TXD O Transmit Serial Data. TXD outputs the shift clock in serial I/O
mode 0 and transmits serial data in serial I/O modes 1, 2, and 3. P3.1
V
CC
PWR Supply Voltage. Connect this pin to the +5V supply voltage. —
V
CC
2
PWR Secondary Supply Voltage 2. This supply voltage connection is
provided to reduce power supply noise. Connection of this pin to
the +5V supply voltage is recommended. However, when using the
8XC251SB as a pin-for-pin replacement for the 8XC51FX, V
SS
2
can
be unconnected without loss of compatibility. (Not available on
DIP.)
—
V
PP
I Programming Supply Voltage. The programming supply voltage
is applied to this pin for programming on-chip nonvolatile memory. EA#
V
SS
GND Circuit Ground. Connect this pin to ground. —
V
SS
1
GND Secondary Ground. This ground is provided to reduce ground
bounce and improve power supply bypassing. Connection of this
pin to ground is recommended. However, when using the
8XC251SA, SB, SP, SQ as a pin-for-pin replacement for the
8XC51BH, V
SS
1
can be unconnected without loss of compatibility.
(Not available on DIP.)
—
Table B-2. Signal Descriptions (Continued)
Signal
Name
Type Description
Alternate
Function
†
The descriptions of A15:8/P2.7:0 and AD7:0/P0.7:0 are for the nonpage mode chip configuration (com-
patible with 44-pin PLCC and 40-pin DIP MCS
®
51 microcontrollers). If the chip is configured for page
mode operation, port 0 carries the lower address bits (A7:0), and port 2 carries the upper address bits
(A15:8) and the data (D7:0).