Intel 8XC251SA, User Manual

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8XC251SA, SB, SP, SQ USER’S MANUAL
14-2
In some microcontroller applications, it is desirable that user program code be secure from unau-
thorized access. The 8XC251Sx offers two types of protection for program code stored in the on-
chip array.
•
Program code in the on-chip code memory is encrypted when read out for verification if the
encryption array is programmed.
•
A three-level lock bit system restricts external access to the on-chip code memory.
14.1.1 Programming Considerations for On-chip Code Memory
It is recommended that user program code be located starting at address FF:0100H. Since the first
instruction following device reset is fetched from FF:0000H, use a jump instruction to FF:0100H
to begin execution of the user program. For information on address spaces, see Chapter 3.
The top eight bytes of the memory address space (FF:FFF8H–FF:FFFFH) are reserved for device
configuration. Do not read or write user code at these locations. For EA# = 1, the reset routine
obtains configuration information from a configuration array located these addresses. For
EA# = 0, the reset routine obtains configuration information from a configuration array in exter-
nal memory using these internal addresses. For a detailed discussion of device configuration, see
Chapter 4.
ROM/OTPROM/EPROM devices have on-chip user code memory at FF:0000–FF:1FFFH
(8 Kbytes) or FF:0000H–FF:3FFFH (16 Kbytes). Addresses outside these ranges access external
memory. With EA# = 1 and both on-chip and external code memory, you can place code at the
highest addresses of the on-chip ROM/OTPROM/EPROM. When the highest on-chip address is
exceeded during execution, code fetches automatically rollover from on-chip memory to external
memory. See the notes on pipelining in section 3.2.2, “On-chip Code Memory (83C251SA, SB,
SP, SQ/87C251SA, SB, SP, SQ).”
With EA# = 1 and only on-chip code memory, multi-byte instructions and instructions that result
in call returns or prefetches should be located a few bytes below the maximum address to avoid
inadvertently exceeding the top address. Use an EJMP instruction, five or more addresses below
the top of memory, to continue execution in other areas of memory. See the note on pipelining in
section 3.2.2, “On-chip Code Memory (83C251SA, SB, SP, SQ/87C251SA, SB, SP, SQ).”
CAUTION
Execution of user code located in the top few bytes of the on-chip user
memory may cause prefetches from the next higher addresses, i.e. external
memory. External memory fetches make use of port 0 and port 3 and may
disrupt program execution if the program uses port 0 or port 3 for a different
purpose.