Intel 8XC251SA, User Manual

Page: 443 / 458

Glossary-5
GLOSSARY
nonpage mode Conventional method for accessing external memory
where code fetches require a two-state bus cycle. See
also page mode.
npn transistor A transistor consisting of one part p-type material and
two parts n-type material.
OTPROM One-time-programmable read-only memory, a version
of EPROM.
p-channel FET A field-effect transistor with a p-type conducting
path.
p-type material Semiconductor material with introduced impurities
(doping) causing it to have an excess of positively
charged carriers.
page mode Method for reducing the time for external code
fetches where subsequent code fetches to the same
256-byte “page” of memory require only a one-state
bus cycle.
PC Program counter.
peripheral cycle The cycle at which the 8XC251SA, SB, SP, SQ
peripherals operate. This is equal to six state times.
program memory A part of memory where instructions can be stored for
fetching and execution.
powerdown mode The power conservation mode that freezes both the
core clocks and the peripheral clocks.
PWM Pulse-width modulated (outputs).
real-time wait state A wait state whose delay time can be adjusted
dynamically by the programmer by means of
registers.
rel A signed (two's complement) 8-bit, relative
destination address. The destination is -128 to +127
bytes relative to the first byte of the next instruction.
reserved bits Register bits that are not used in this device but may
be used in future implementations. Avoid any
software dependence on these bits. In the 8XC251SB,
the value read from a reserved bit is indeterminate; do
not write a “1” to a reserved bit.
response time The amount of time between the interrupt request and
the resulting break in the current instruction stream.