Intel 8XC251SA, User Manual

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CONTENTS
xiii
TABLES
Table Page
1-1 Intel Application Support Services................................................................................1-7
2-1 8XC251SA, SB, SP, SQ Features................................................................................2-3
3-1 Address Mappings........................................................................................................3-4
3-2 Minimum Times to Fetch Two Bytes of Code...............................................................3-9
3-3 Register Bank Selection .............................................................................................3-12
3-4 Dedicated Registers in the Register File and their Corresponding SFRs...................3-15
3-5 8XC251SA, SB, SP, SQ SFR Map and Reset Values ...............................................3-17
3-6 Core SFRs..................................................................................................................3-18
3-7 I/O Port SFRs .............................................................................................................3-18
3-8 Serial I/O SFRs ..........................................................................................................3-19
3-9 Timer/Counter and Watchdog Timer SFRs ................................................................3-19
3-10 Programmable Counter Array (PCA) SFRs................................................................3-19
4-1 External Addresses for Configuration Array .................................................................4-4
4-2 Memory Signal Selections (RD1:0) ..............................................................................4-8
4-3 RD#, WR#, PSEN# External Wait States ...................................................................4-13
4-4 Examples of Opcodes in Binary and Source Modes ..................................................4-14
5-1 Data Types ...................................................................................................................5-2
5-2 Notation for Byte Registers, Word Registers, and Dword Registers ............................5-3
5-3 Addressing Modes for Data Instructions in the MCS® 51 Architecture ........................5-6
5-4 Addressing Modes for Data Instructions in the MCS® 251 Architecture ......................5-7
5-5 Bit-addressable Locations ..........................................................................................5-11
5-6 Addressing Two Sample Bits......................................................................................5-12
5-7 Addressing Modes for Bit Instructions ........................................................................5-12
5-8 Addressing Modes for Control Instructions.................................................................5-13
5-9 Compare-conditional Jump Instructions .....................................................................5-14
5-10 The Effects of Instructions on the PSW and PSW1 Flags..........................................5-17
6-1 Interrupt System Pin Signals ........................................................................................6-1
6-2 Interrupt System Special Function Registers ...............................................................6-3
6-3 Interrupt Control Matrix.................................................................................................6-4
6-4 Level of Priority.............................................................................................................6-7
6-5 Interrupt Priority Within Level .......................................................................................6-7
6-6 Interrupt Latency Variables ........................................................................................6-13
6-7 Actual vs. Predicted Latency Calculations..................................................................6-13
7-1 Input/Output Port Pin Descriptions ...............................................................................7-1
7-2 Instructions for External Data Moves............................................................................7-9
8-1 Timer/Counter and Watchdog Timer SFRs ..................................................................8-2
8-2 External Signals ...........................................................................................................8-3
8-3 Timer 2 Modes of Operation.......................................................................................8-15
9-1 PCA Special Function Registers (SFRs) ......................................................................9-4
9-2 External Signals ...........................................................................................................9-4
9-3 PCA Module Modes ...................................................................................................9-14
10-1 Serial Port Signals ......................................................................................................10-1
10-2 Serial Port Special Function Registers .......................................................................10-2
10-3 Summary of Baud Rates ..........................................................................................10-10