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Intel 8XC251SA, User Manual

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8XC251SA, SB, SP, SQ USER’S MANUAL

A-10

Table A-15.  INC/DEC

Instruction

Byte 0 

Byte 1

1

INC  Rm,#short

0

B

m

00

ss

2

INC  WRj,#short

0

B

 j/2

01

ss

3

INC  DRk,#short

0

B

k/4

11

ss

4

DEC Rm,#short

1

B

m

00

ss

5

DEC WRj,#short

1

B

j/2

01

ss

6

DEC DRk,#short

1

B

k/4

11

ss

Table A-16.  Encoding for INC/DEC

ss

#short

00

1

01

2

10

4

Table A-17.  Shifts

Instruction

Byte 0 

Byte 1

1

SRA Rm

0

E

m

0000

2

SRA WRj

0

E

j/2

0100

3

SRL Rm

1

E

m

0000

4

SRL WRj

1

E

j/2

0100

5

SLL Rm

3

E

m

0000

6

SLL WRj

3

E

j/2

0100

Summary of Contents for 8XC251SA

Page 1: ...8XC251SA 8XC251SB 8XC251SP 8XC251SQ Embedded Microcontroller User s Manual 8XC251SA 8XC251SB 8XC251SP 8XC251SQ Embedded Microcontroller User s Manual 27279502 qxd 6 18 96 9 25 AM Page 1...

Page 2: ......

Page 3: ...May 1996 8XC251SA 8XC251SB 8XC251SP 8XC251SQ Embedded Microcontroller User s Manual...

Page 4: ...ut notice Microcontroller products may have minor variations to this specification known as errata Other brands and names are the property of their respective owners Contact your local Intel sales off...

Page 5: ...chip Code Memory 2 7 2 2 5 On chip RAM 2 7 2 3 ON CHIP PERIPHERALS 2 7 2 3 1 Timer Counters and Watchdog Timer 2 7 2 3 2 Programmable Counter Array PCA 2 8 2 3 3 Serial I O Port 2 8 CHAPTER 3 ADDRESS...

Page 6: ...12 4 5 3 1 Configuration Bits WSA1 0 WSB1 4 12 4 5 3 2 Configuration Bit WSB 4 12 4 5 3 3 Configuration Bit XALE 4 13 4 6 OPCODE CONFIGURATIONS SRC 4 13 4 6 1 Selecting Binary Mode or Source Mode 4 1...

Page 7: ...INTERRUPT PRIORITIES 6 7 6 7 INTERRUPT PROCESSING 6 9 6 7 1 Minimum Fixed Interrupt Time 6 10 6 7 2 Variable Interrupt Parameters 6 10 6 7 2 1 Response Time Variables 6 10 6 7 2 2 Computation of Wors...

Page 8: ...e 8 11 8 6 2 Auto reload Mode 8 12 8 6 2 1 Up Counter Operation 8 12 8 6 2 2 Up Down Counter Operation 8 13 8 6 3 Baud Rate Generator Mode 8 14 8 6 4 Clock out Mode 8 14 8 7 WATCHDOG TIMER 8 16 8 7 1...

Page 9: ...0 6 3 1 Timer 1 Generated Baud Rates Modes 1 and 3 10 11 10 6 3 2 Selecting Timer 1 as the Baud Rate Generator 10 11 10 6 3 3 Timer 2 Generated Baud Rates Modes 1 and 3 10 12 10 6 3 4 Selecting Timer...

Page 10: ...13 5 1 Real time WAIT Enable RTWE 13 12 13 5 2 Real time WAIT CLOCK Enable RTWCE 13 12 13 5 3 Real time Wait State Bus Cycle Diagrams 13 12 13 6 CONFIGURATION BYTE BUS CYCLES 13 15 13 7 PORT 0 AND POR...

Page 11: ...NS 14 6 14 6 1 On chip Code Memory 14 7 14 6 2 Configuration Bytes 14 7 14 6 3 Lock Bit System 14 7 14 6 4 Encryption Array 14 8 14 6 5 Signature Bytes 14 8 14 7 VERIFYING THE 83C251SA SB SP SQ ROM 14...

Page 12: ...1 0 10 and 11 4 11 4 7 Binary Mode Opcode Map 4 15 4 8 Source Mode Opcode Map 4 15 5 1 Word and Double word Storage in Big Endien Form 5 3 5 2 Program Status Word Register 5 18 5 3 Program Status Word...

Page 13: ...Mode and Page Mode 13 1 13 2 External Code Fetch Nonpage Mode 13 4 13 3 External Data Read Nonpage Mode 13 4 13 4 External Data Write Nonpage Mode 13 5 13 5 External Code Fetch Page Mode 13 6 13 6 Ext...

Page 14: ...51SB in Nonpage Mode 13 27 13 26 Address Space for Examples 5 and 6 13 28 13 27 Bus Diagram for Example 6 80C251SB in Page Mode 13 29 13 28 Bus Diagram for Example 7 80C251SB in Page Mode 13 30 14 1 S...

Page 15: ...hitecture 5 6 5 4 Addressing Modes for Data Instructions in the MCS 251 Architecture 5 7 5 5 Bit addressable Locations 5 11 5 6 Addressing Two Sample Bits 5 12 5 7 Addressing Modes for Bit Instruction...

Page 16: ...re A 5 A 8 Data Instructions A 6 A 9 High Nibble Byte 0 of Data Instructions A 6 A 10 Bit Instructions A 7 A 11 Byte 1 High Nibble for Bit Instructions A 7 A 12 PUSH POP Instructions A 8 A 13 Control...

Page 17: ...CONTENTS xv TABLES Table Page C 4 Serial I O SFRs C 4 C 5 Timer Counter and Watchdog Timer SFRs C 4 C 6 Programmable Counter Array PCA SFRs C 5 C 7 Register File C 6...

Page 18: ......

Page 19: ...1 Guide to This Manual...

Page 20: ......

Page 21: ...ping of the address spaces of the MCS 51 architecture into the address spaces of the MCS 251 architecture Chapter 4 Device Configuration describes microcontroller features that are configured at devic...

Page 22: ...es on chip and external clock sources and describes de vice resets including power on reset Chapter 12 Special Operating Modes provides an overview of the idle powerdown and on circuit emulation ONCE...

Page 23: ...een the two possible meanings Variables in registers and signal names are commonly represented by x and y where x represents the first variable and y represents the second variable For example in regi...

Page 24: ...represented by the register name followed by a period and the bit number For example PCON 4 is bit 4 of the power control register In some discussions bit names are used For example the name of PCON 4...

Page 25: ...A microamps microamperes F microfarads s microseconds W microwatts 1 3 RELATED DOCUMENTS The following documents contain additional information that is useful in designing systems that incorporate the...

Page 26: ...ormance Using MCS 251 Microcontroller Order Number 272671 Programming the 8XC251SB AP 710 Migrating from the MCS 51 Microcontroller to the MCS 251 Order Number 272672 Microcontroller 8XC251SB Software...

Page 27: ...intel com design mcs96 Also visit Intel s Web site for financials history and news 1 4 2 CompuServe Forums Intel maintains several CompuServe forums that provide a means for you to gather information...

Page 28: ...r number of each document that has been added revised or deleted dur ing the past eight weeks The daily update catalogs are numbered with the subject catalog number followed by a zero For example for...

Page 29: ...1 on page 1 7 and respond to the system prompts During your first session the system asks you to register with the system oper ator by entering your name and location The system operator will set up y...

Page 30: ......

Page 31: ...2 Architectural Overview...

Page 32: ......

Page 33: ...251 microcontrollers share a set of common features 24 bit linear addressing and up to 16 Mbytes of memory a register based CPU with registers accessible as bytes words and double words a page mode fo...

Page 34: ...erial I O Peripherals Port 2 Drivers P2 7 0 Port 0 Drivers P0 7 0 Port 3 Drivers P3 7 0 Port 1 Drivers P1 7 0 Data Address 24 Data Bus 8 Memory Address 16 MCS 251 Microcontroller Core System Bus and I...

Page 35: ...lly programmed as a general I O signal or as a special function sig nal that supports the external bus or one of the on chip peripherals Ports P0 and P2 comprise a 16 line external bus which transmits...

Page 36: ...ent for MCS 251 architecture instructions and binary mode is more efficient for MCS 51 architecture instructions In binary mode object code for an MCS 51 microcontroller runs on the 8XC251Sx without r...

Page 37: ...XC251Sx register file has forty registers which can be accessed as bytes words and double words As in the MCS 51 architecture registers 0 7 consist of four banks of eight registers each where the acti...

Page 38: ...mes This periph eral cycle is particular to the 8XC251Sx and not a characteristic of the MCS 251 architecture A one clock interval in a peripheral cycle is denoted by its state and phase For example t...

Page 39: ...51SA and 8XC251SB have 1 Kbyte of on chip data RAM at locations 20H 41FH The 8XC251SP and 8XC251SQ have 512 bytes of on chip data RAM at locations 20H 21FH These RAM locations can be accessed with dir...

Page 40: ...serving as a software watchdog timer Chapter 9 Program mable Counter Array describes this peripheral in detail 2 3 3 Serial I O Port The serial I O port provides one synchronous and three asynchronou...

Page 41: ...3 Address Spaces...

Page 42: ......

Page 43: ...tecture and the MCS 51 architecture in terms of their address spaces 3 1 ADDRESS SPACES FOR MCS 251 MICROCONTROLLERS Figure 3 1 shows the memory space the SFR space and the register file for MCS 251 m...

Page 44: ...SP SQ Register File on page 3 10 for a further description of the register file The SFR space can accommodate up to 512 8 bit special function registers with addresses S 000H S 1FFH Some of these loc...

Page 45: ...ontrollers maps into region FF of the memory space for MCS 251 microcontrollers Assemblers for MCS 251 microcontrollers assemble code for MCS 51 microcontrollers into region FF and data accesses to co...

Page 46: ...H 01 FFFFH Internal Data 128 bytes 00H 7FH Direct Indirect 00 0000H 00 007FH 128 bytes 80H FFH Indirect 00 0080H 00 00FFH SFRs 128 bytes S 80H S FFH Direct S 080H S 0FFH Register File 8 bytes R0 R7 Re...

Page 47: ...on page 3 5 The 128 byte SFR space for MCS 51 microcontrollers is mapped into the 512 byte SFR space of the MCS 251 architecture starting at address S 080H as shown in Figure 3 3 This provides com ple...

Page 48: ...FFFFH FE FFFFH FF FFFFH 01 0000H FE 0000H FF 0000H Memory Address Space 16 Mbytes 00 0080H 00 0020H 00 007FH 00 0000H 00 001FH 00 FFFFH Indirect and Displacement Addressing 16 Mbytes Direct Addressing...

Page 49: ...FF 0000H External Memory External Memory Registers R0 R7 External Memory 00 0000H 00 FFFFH On chip ROM 8 or 16 Kbytes On chip RAM 512 or 1024 Bytes External Memory Eight byte configuration array FF FF...

Page 50: ...byte is provided for general data storage Figure 3 5 Instruc tions cannot execute from on chip data RAM The data is accessible by direct indirect and dis placement addressing Locations 00 0020H 00 007...

Page 51: ...to external code memory is transparent to the user 3 2 2 1 Accessing On chip Code Memory in Region 00 The 87C251SB SQ and the 83C251SB SQ can be configured so that the upper half of the 16 Kbyte on c...

Page 52: ...al Memory Interface on page 4 8 and Chapter 13 External Memory Interface 3 3 8XC251SA SB SP SQ REGISTER FILE The 8XC251Sx register file consists of 40 locations 0 31 and 56 63 as shown in Figure 3 6 T...

Page 53: ...4 Locations 32 55 are Reserved 63 62 61 60 59 58 57 56 R7 R6 R5 R4 R3 R2 R1 R0 R15 R14 R13 R12 R11 R10 R9 R8 DR20 DR16 DR28 DR24 WR6 WR4 WR2 WR0 WR14 WR12 WR10 WR8 WR22 WR20 WR18 WR16 WR30 WR28 WR26 W...

Page 54: ...locations 8 31 and 56 63 are always accessible These locations are implemented as registers in the CPU Register file locations 32 55 are reserved and cannot be accessed Figure 3 7 Register File Locat...

Page 55: ...0 001FH in the memory space 3 3 2 Dedicated Registers The register file has four dedicated registers R10 is the B register R11 is the accumulator ACC DR56 is the extended data pointer DPX DR60 is the...

Page 56: ...e Register File and their Corresponding SFRs Bits in the PSW and PSW1 registers reflect the status of the accumulator There are no equivalent status indicators for the other registers R11 Accumulator...

Page 57: ...nter SPX Figure 3 8 The byte at location 63 is the 8 bit stack pointer SP in the MCS 51 architecture The byte at location 62 is the stack pointer high SPH The two bytes allow the stack to extend to th...

Page 58: ...receded by S to differentiate them from addresses in the memory space Unoccupied lo cations in the SFR space the shaded locations in Table 3 5 are unimplemented i e no register exists If an instructio...

Page 59: ...000000 PSW1 00000000 D7 C8 T2CON 00000000 T2MOD xxxxxx00 RCAP2L 00000000 RCAP2H 00000000 TL2 00000000 TH2 00000000 CF C0 C7 B8 IPL0 x0000000 SADEN 00000000 SPH 00000000 BF B0 P3 11111111 IPH0 x0000000...

Page 60: ...rogram Status Word 1 S D1H SP Stack Pointer LSB of SPX S 81H SPH Stack Pointer High MSB of SPX S BEH DPTR Data Pointer 2 bytes DPL Low Byte of DPTR S 82H DPH High Byte of DPTR S 83H DPXL Data Pointer...

Page 61: ...nter 2 High Byte S CDH TCON Timer Counter 0 and 1 Control S 88H TMOD Timer Counter 0 and 1 Mode Control S 89H T2CON Timer Counter 2 Control S C8H T2MOD Timer Counter 2 Mode Control S C9H RCAP2L Timer...

Page 62: ...Byte S ECH CCAP3L PCA Compare Capture Module 3 Low Byte S EDH CCAP4L PCA Compare Capture Module 4 Low Byte S EEH CCAP0H PCA Compare Capture Module 0 High Byte S FAH CCAP1H PCA Compare Capture Module 1...

Page 63: ...4 Device Configuration...

Page 64: ......

Page 65: ...ps into the external memory See 4 5 Configuring the External Memory Interface Section 4 6 Opcode Configurations SRC discusses the choice of source mode or binary mode opcode arrangements 4 1 CONFIGURA...

Page 66: ...internal addresses FF FFF8H and FF FFF9H CAUTION The eight highest addresses in the memory address space FF FFF8H FF FFFFH are reserved for the configuration array Do not read or write these locations...

Page 67: ...FF9H x xFF8H UCONFIG1 UCONFIG0 Reserved This figure shows the addresses of configuration bytes UCONFIG1 and UCONFIG0 in external memory for several memory implementations For EA 0 the 8XC251Sx obtains...

Page 68: ...2 XALE Extends the ALE pulse WSA1 0 Selects 0 1 2 or 3 pre programmed wait states for all regions except 01 WSB1 0 Selects 0 3 pre programmed wait states for memory region 01 EMAP Affects the externa...

Page 69: ...from on chip nonvol atile memory at addresses FF FFF8H to FF FFFFH The configuration bytes are located at loca tions FF FFF8H and FF FFF9H If UCON is set e g UCON 1 the state of the EA pin at device r...

Page 70: ...on RD1 0 bit codes specify an 18 bit 17 bit or 16 bit external address bus and address ranges for RD WR and PSEN See Table 4 2 1 PAGE Page Mode Select Clear this bit for page mode enabled with A15 8 D...

Page 71: ...on chip code memory clear this bit to map the upper half of on chip code memory to region 00 data memory Maps FF 2000H FF 3FFFH to 00 E000H 00 FFFFH If this bit is set mapping does not occur and addre...

Page 72: ...cture is the same as for the MCS 51 architecture with data D7 0 multiplexed with A7 0 on P0 External code fetches require two state times 4TOSC Page mode PAGE 0 The bus structure differs from the bus...

Page 73: ...ry In some situations however a multiple mapping from internal memory to external memory does not preclude using more than one region For example for a device with on chip ROM OTPROM EPROM configured...

Page 74: ...and WR Sections 13 8 2 and 13 8 3 show examples of memory designs with this option Figure 4 5 Internal External Address Mapping RD1 0 00 and 01 FF 01 PSEN WR PSEN WR A4218 02 FF FE 01 00 RD1 0 00 18...

Page 75: ...2 PSEN WR PSEN WR FE FF 00 01 00 01 FE FF 64 Kbytes 128 Kbytes Notes 1 Single read signal 2 P3 7 RD A16 functions only as P3 7 Note 1 Compatible with MCS 51 microcontrollers 2 Cannot write to regions...

Page 76: ...icrocontrollers which have separate external memory spaces for code and data 4 5 3 Wait State Configuration Bits You can add wait states to external bus cycles by extending the RD WR PSEN pulse and or...

Page 77: ...hich set of opcodes is assigned to columns 6H through FH and which set is the alternative Binary mode and source mode refer to two ways of assigning opcodes to the instruction set for the MCS 251 arch...

Page 78: ...e that was written for an MCS 51 microcontroller and you want to run it unmod ified on an MCS 251 microcontroller choose binary mode You can use the object code without reassembling the source code Yo...

Page 79: ...4 8 Source Mode Opcode Map A4131 01 I II 0H 5H FH 6H 0H FH MCS 51 Architecture MCS 51 Architecture III 6H FH 0H FH MCS 251 Architecture A5H Prefix A4130 01 I III 0H 5H FH 6H 0H FH MCS 51 Architecture...

Page 80: ...0 FFFFH EMAP 1 Mapping of on chip code memory to region 00 does not occur Addresses in the range 00 E000H 00 FFFFH access external RAM 4 8 INTERRUPT MODE INTR The INTR bit UCONFIG1 4 determines what b...

Page 81: ...5 Programming...

Page 82: ......

Page 83: ...er to the two ways of assigning opcodes to the instruction set of the MCS 251 architecture Depending on the application one mode or the other may produce more efficient code The mode is established du...

Page 84: ...ption of the register file see section 3 3 8XC251SA SB SP SQ Register File The code fragment in Figure 5 1 illustrates the storage of words and double words in big endien form 5 2 2 Register Notation...

Page 85: ...prefixes 00 01 FF and the SFR prefix S are required Also software tools for the MCS 251 architecture permit 00 to be used for memory addresses 00H FFH and permit the prefix S to be used for SFR ad dre...

Page 86: ...essing Modes for Control Instructions 5 3 DATA INSTRUCTIONS Data instructions consist of arithmetic logical and data transfer instructions for 8 bit 16 bit and 32 bit data This section describes the d...

Page 87: ...bit immediate data into a dword register DRk place the data either into the upper word while leaving the lower word unchanged or into the lower word with a sign extension or a zero extension The incr...

Page 88: ...l data RAM See the notes in section 5 3 1 Data Addressing Modes regarding the region of external data RAM that is addressed by instructions in the MCS 51 architecture Byte register Ri i 1 2 Registers...

Page 89: ...7FH On chip RAM SFRs dir8 S 080H S 1FFH 2 or SFR mnemonic SFR address Direct 16 address bits 00 0000H 00 FFFFH dir16 00 0000H 00 FFFFH Indirect 16 address bits 00 0000H 00 FFFFH WR0 WR30 Indirect 24 a...

Page 90: ...fset which is added to the base address 5 3 2 Arithmetic Instructions The set of arithmetic instructions is greatly expanded in the MCS 251 architecture The ADD and SUB instructions Table A 19 on page...

Page 91: ...tains the first operand register The quotient is stored in the lower byte and the remainder is stored in the higher byte A 16 bit divide is similar The first operand is a word register and the result...

Page 92: ...s 01H See section 3 3 2 Dedicated Registers The MOVC Move Code instruction moves a byte from code memory region FF to the accu mulator MOVS Move with Sign Extension and MOVZ Move with Zero Extension m...

Page 93: ...5 5 The bit instructions that are unique to the MCS 251 architecture can address a wider range of bits than the instructions from the MCS 51 architecture There are some differences in the way the ins...

Page 94: ...ocontrollers have a 24 bit program counter PC which allows a target instruction to be anywhere in the 16 Mbyte address space However as discussed in this section some con trol instructions restrict th...

Page 95: ...addressing There are two types of indirect addressing for control instructions For the instructions LCALL WRj and LJMP WRj the target address is in the current 64 Kbyte region The 16 bit address in W...

Page 96: ...Bit Addressing describes the bit addressing used in these instructions Compare conditional jumps test a condition resulting from a compare CMP instruction that is assumed to precede the jump instructi...

Page 97: ...ruction address onto the stack and then changes the lower 11 bits of the PC to the 11 bit address specified by the instruction The call is to an address that is in the same 2 Kbyte block of memory as...

Page 98: ...is useful for the development of emulations of an MCS 251 microcontrol ler 5 6 PROGRAM STATUS WORDS The Program Status Word PSW register and the Program Status Word 1 PSW1 register contain four types...

Page 99: ...L SRA 4 X X X Program Control CJNE X X X DJNE X X NOTES 1 X the flag can be affected by the instruction 0 the flag is cleared by the instruction 2 The AC flag is affected only by operations on 8 bit o...

Page 100: ...lag is useful for BCD arithmetic see Table 5 10 5 F0 Flag 0 This general purpose flag is available to the user 4 3 RS1 0 Register Bank Select Bits 1 and 0 These bits select the memory locations that c...

Page 101: ...Negative Flag This bit is set if the result of the last logical or arithmetic operation was negative i e bit 15 1 Otherwise it is cleared 4 3 RS1 0 Register Bank Select Bits 0 and 1 Identical to the R...

Page 102: ......

Page 103: ...6 Interrupt System...

Page 104: ......

Page 105: ...Table 6 2 Interrupt System Special Function Registers is compared to the priority of other interrupts by the interrupt handler A high priority causes the handler to set an interrupt flag This signals...

Page 106: ...1 INT1 Timer 1 0 1 0 1 ECF ECCFx IT0 IT1 5 A4149 01 IP Interrupt Enable Priority Enable EX0 ET0 EX1 ET1 EC ES ET2 TF0 CF CCFx RI TI TF2 EXF2 TF1 PCA Counter Overflow PCA Match or Capture Receive Trans...

Page 107: ...hardware vectors to service routines only if the interrupt is negative edge triggered If the interrupt is level triggered the in terrupt service routine must clear the request bit External hardware m...

Page 108: ...determine if TF2 or EXF2 generated the interrupt and then clear the bit Timer 2 interrupt is enabled by ET2 in register IE0 Table 6 3 Interrupt Control Matrix Interrupt Name Global Enable PCA Timer 2...

Page 109: ...e Figure 9 8 on page 9 14 and Figure 9 9 on page 9 15 NOTE CCFx refers to 5 separate bits one for each PCA module CCF0 CCF1 CCF2 CCF3 CCF4 CCAPMx refers to 5 separate registers one for each PCA module...

Page 110: ...rrupt Enable Setting this bit enables the PCA interrupt 5 ET2 Timer 2 Overflow Interrupt Enable Setting this bit enables the timer 2 overflow interrupt 4 ES Serial I O Port Interrupt Enable Setting th...

Page 111: ...rrupted by any other in terrupt source Higher priority interrupts are serviced before lower priority interrupts The response to simultaneous occurrence of equal priority interrupts i e sampled within...

Page 112: ...ority Bit High 2 IPH0 2 External Interrupt 1 Priority Bit High 1 IPH0 1 Timer 0 Overflow Interrupt Priority Bit High 0 IPH0 0 External Interrupt 0 Priority Bit High IPL0 Address S B8H Reset State X000...

Page 113: ...with the request The subsequent minimum fixed sequence comprises the interrupt sample poll and request operations The variables consist of but are not limited to specific instructions in use at reque...

Page 114: ...ari able is the completion time of an instruction cycle coincident with the occurrence of an interrupt request Worst case predictions typically use the longest executing instruction in an architecture...

Page 115: ...o the execution unit If 9 states of a 10 state instruction have completed when the context switch is requested the total response time is 6 states with a context switch immediately after the final sta...

Page 116: ...ate with the assumption the instruction state overlaps the request state therefore 16 bit DIV is 21 state times 1 20 states for latency calculations The calculations add fixed and vari able interrupt...

Page 117: ...n the current 64 Kbyte region Finally three states are added for the current instruction to complete The actual latency is 26 states Worst case latency calculations predict 43 states for this example...

Page 118: ...hree ensures at least one more instruction executes before the system vectors to additional interrupts if the in struction in progress is a RETI or any write to IE0 IPH0 or IPL0 The complete polling c...

Page 119: ...Sx this causes a compatibility problem if INTR 1 in configuration byte CONFIG1 In this case the CPU pushes four bytes the three byte PC and PSW1 onto the stack when the routine is called and pops the...

Page 120: ......

Page 121: ...7 Input Output Ports...

Page 122: ......

Page 123: ...port 3 pins serve for both general purpose I O and alternate functions see Table 7 1 Table 7 1 Input Output Port Pin Descriptions Pin Name Type Alternate Pin Name Alternate Description Alternate Type...

Page 124: ...r for general purpose I O or for its al ternate input or output function Table 7 1 To use a pin for general purpose output set or clear the corresponding bit in the Px register x 1 3 To use a pin for...

Page 125: ...0 Structure Read Latch Read Pin Write to Latch Internal Bus Alternate Output Function D CL Q Q P3 x Latch Internal Pullup P3 x Alternate Input Function A2239 01 VCC Read Latch Read Pin Address Data C...

Page 126: ...scusses the operation of port 0 and port 2 as the external address data bus NOTE Port 0 and port 2 are precluded from use as general purpose I O ports when used as address data bus drivers Port 0 inte...

Page 127: ...DJNZ P3 LABEL MOV PX Y C move carry bit to bit Y of port X CLR PX Y clear bit Y of port X SETB PX Y set bit Y of port x It is not obvious that the last three instructions in this list are read modify...

Page 128: ...t buffers and therefore the pin state update early in the instruction after the read modify write instruction cycle Logical zero to one transitions in port 1 port 2 and port 3 utilize an additional pu...

Page 129: ...zero see VOL1 in the 8XC251Sx data sheet However the port 0 pins require external pullups to drive external gate inputs See the latest revision of the 8XC251Sx datasheet for com plete electrical desig...

Page 130: ...ress byte In page mode port 2 uses a strong internal pullup FET to output ones or a strong internal pulldown FET to output zeros for the upper address byte and data Port 2 is in a high impedance state...

Page 131: ...ata is written to port 0 just prior to the write WR pin asserting VOL Data remains valid until WR is undriven For read cycles data returned from external memory must appear at port 0 before the read R...

Page 132: ......

Page 133: ...8 Timer Counters and Watchdog Timer...

Page 134: ......

Page 135: ...d associated control and cap ture registers are implemented as addressable special function registers SFRs Table 8 1 briefly describes the SFRs referred to in this chapter Four of the SFRs provide pro...

Page 136: ...ock signal with frequency FOSC 12 timer operation or an external input event counter operation S CCH S CDH TCON Timer 0 1 Control Register Contains the run control bits overflow flags interrupt flags...

Page 137: ...r event counter in four modes of operation Figures 8 2 8 3 and 8 4 show the logical configuration of each mode Timer 0 is controlled by the four low order bits of the TMOD register Figure 8 5 and bits...

Page 138: ...es timer 0 as a 13 bit timer which is set up as an 8 bit timer TH0 register with a modulo 32 prescalar implemented with the lower five bits of the TL0 register Figure 8 2 The upper three bits of the T...

Page 139: ...0 operate as separate 8 bit timers Fig ure 8 4 This mode is provided for applications requiring an additional 8 bit timer or counter TL0 uses the timer 0 control bits C T0 and GATE0 in TMOD and TR0 an...

Page 140: ...imer 1 can serve as the baud rate generator for the serial port Mode 2 is best suited for this purpose For normal timer operation GATE1 0 setting TR1 allows timer register TL1 to be increment ed by th...

Page 141: ...1 with 5 bit prescalar TL1 0 1 Mode 1 16 bit timer counter 1 0 Mode 2 8 bit auto reload timer counter TL1 Reloaded from TH1 at overflow 1 1 Mode 3 Timer 1 halted Retains count 3 GATE0 Timer 0 Gate Whe...

Page 142: ...f 5 TF0 Timer 0 Overflow Flag Set by hardware when the timer 0 register overflows Cleared by hardware when the processor vectors to the interrupt routine 4 TR0 Timer 0 Run Control Bit Set cleared by s...

Page 143: ...ode 3 Halt Placing timer 1 in mode 3 causes it to halt and hold its count This can be used to halt timer 1 when the TR1 run control bit is not available i e when timer 0 is in mode 3 See the final par...

Page 144: ...order bits of the TMOD register Figure 8 5 to specify mode 1 for timer 0 C T0 0 to select FOSC 12 as the timer input and GATE0 1 to select INT0 as timer run control 2 Enter an initial value of all zer...

Page 145: ...ut The operating modes are described in the following paragraphs Block diagrams in Figures 8 7 through 8 10 show the timer 2 configuration for each mode 8 6 1 Capture Mode In the capture mode timer 2...

Page 146: ...register provides two options Figure 8 12 If EXEN2 0 timer 2 counts up to FFFFH and sets the TF2 overflow flag The overflow condition loads the 16 bit value in the re load capture registers RCAP2H RCA...

Page 147: ...low timer 2 counts down Timer underflow occurs when the count in the timer registers TH2 TL2 equals the value stored in RCAP2H and RCAP2L The underflow sets the TF2 bit and reloads FFFFH into the tim...

Page 148: ...clock timer 2 has a programmable frequency range of 61 Hz to 4 MHz The generated clock signal is brought out to the T2 pin Timer 2 is programmed for the clock out mode as follows 1 Set the T2OE bit i...

Page 149: ...2 Modes of Operation Mode RCLK OR TCLK in T2CON CP RL2 in T2CON T2OE in T2MOD Auto reload Mode 0 0 0 Capture Mode 0 1 0 Baud Rate Generator Mode 1 X X Programmable Clock Out X 0 1 Interrupt Request T2...

Page 150: ...ac cess to the WDT Two operations control the WDT Device reset clears and disables the WDT see section 11 4 Reset Writing a specific two byte sequence to the WDTRST register clears and enables the WD...

Page 151: ...or timer 1 overflow pulses TCLK 0 as the baud rate generator for serial port modes 1 and 3 3 EXEN2 Timer 2 External Enable Bit Setting EXEN2 causes a capture or reload to occur as a result of a negat...

Page 152: ...power reduction modes deserves special attention The WDT continues to count while the microcontroller is in idle mode This means the user must service the WDT during idle One approach is to use a peri...

Page 153: ...9 Programmable Counter Array...

Page 154: ......

Page 155: ...9 9 For a list of SFRs associated with the PCA see Table 9 1 For an address map of all SFRs see Table 3 5 on page 3 17 Port 1 provides external I O for the PCA on a shared basis with other functions...

Page 156: ...byte register When CL overflows the CH high byte register increments after two oscil lator periods when CH overflows it sets the PCA overflow flag CF in the CCON register gen erating a PCA interrupt r...

Page 157: ...er writing to them is inhibited while they are counting i e when the CR bit is set Figure 9 1 Programmable Counter Array 16 bit Bus CL 8 Bits CH 8 Bits CF Interrupt Request FOSC 12 PCA Timer Counter C...

Page 158: ...cycle of the output waveform S FBH S EBH CCAP2H CCAP2L PCA Module 2 Compare Capture Registers This register pair stores the comparison value or the captured value In the PWM mode the low byte registe...

Page 159: ...na tions of the available modes Other bit combinations are invalid and produce undefined results The compare capture modules perform their programmed functions when their common time base the PCA time...

Page 160: ...to the compare capture registers CCAPxH CCAPxL and to set the module s compare capture flag CCFx in the CCON register If the corresponding in terrupt enable bit ECCFx in the CCAPMx register is set Fig...

Page 161: ...peration 2 Select the input signal for the PCA timer counter 3 Load the comparison value into the module s compare capture register pair 4 Set the PCA timer counter run control bit 5 After a match cau...

Page 162: ...9 3 on page 9 14 lists the bit combinations for selecting module modes A match between the PCA timer counter and the compare capture registers CCAPxH CCAPxL toggles the CEXx pin and sets the module s...

Page 163: ...are used in applications that are subject to electrical noise power glitches elec trostatic discharges etc or where high reliability is required In addition to the 8XC251Sx s 14 bit hardware WDT the P...

Page 164: ...then later re enable it The first two options are more reliable because the WDT is not disabled as in the third option The second option is not recommended if other PCA modules are in use since the fi...

Page 165: ...ter CL is continuously compared with the value in the low byte of the compare capture register CCAPxL When CL CCAPxL the output waveform Figure 9 6 is low When a match occurs CL CCAPxL the output wave...

Page 166: ...The highest frequency occurs when the FOSC 4 input is selected for the PCA tim er counter For FOSC 16 MHz this is 15 6 KHz To program a compare capture module for the PWM mode set the ECOMx and PWMx...

Page 167: ...to run during idle mode 6 WDTE Watchdog Timer Enable WDTE 1 enables the watchdog timer output on PCA module 4 WDTE 0 disables the PCA watchdog timer output 5 3 Reserved The values read from these bit...

Page 168: ...s This generates a PCA interrupt request if the ECCFx interrupt enable bit in the corresponding CCAPMx register is set Must be cleared by software Table 9 3 PCA Module Modes ECOMx CAPPx CAPNx MATx TOG...

Page 169: ...apture triggered by a positive edge on pin CEXx 4 CAPNx Capture Mode Negative CAPNx 1 enables the capture function with capture triggered by a negative edge on pin CEXx 3 MATx Match Set ECOMx and MATx...

Page 170: ......

Page 171: ...10 Serial I O Port...

Page 172: ......

Page 173: ...serial port special function registers are described in Table 10 2 Figure 10 1 is a block diagram of the serial port For the three asynchronous modes the UART transmits on the TXD pin and receives on...

Page 174: ...rial port operating mode SCON enables and disables the receiver framing bit error detection multiprocessor communication automatic address recognition and the serial port interrupt bits 98H SADDR Seri...

Page 175: ...operating mode SM0 SM1 Mode Description Baud Rate 0 0 0 Shift register FOSC 12 0 1 1 8 bit UART Variable 1 0 2 9 bit UART FOSC 32 or FOSC 64 1 1 3 9 bit UART Variable Select by programming the SMOD bi...

Page 176: ...e 0 10 2 1 1 Transmission Mode 0 Follow these steps to begin a transmission 1 Write to the SCON register clearing bits SM0 SM1 and REN 2 Write the byte to be transmitted to the SBUF register This writ...

Page 177: ...ck signal pulse and the LSB D0 is sampled on the RXD pin at S5P2 The D0 bit is then shift ed into the shift register After eight shifts at S6P2 of every peripheral cycle the LSB D7 is shift ed into th...

Page 178: ...n On receive the ninth bit is read from the RB8 bit in the SCON register On transmit the ninth data bit is written to the TB8 bit in the SCON register Alternatively you can use the ninth bit as a comm...

Page 179: ...ocessor com munication feature is enabled the serial port can differentiate between data frames ninth bit clear and address frames ninth bit set This allows the microcontroller to function as a slave...

Page 180: ...recognition features cannot be enabled in mode 0 i e setting the SM2 bit in the SCON register in mode 0 has no effect To support automatic address recognition a device is identified by a given address...

Page 181: ...nd C the master must send an address with bit 0 set bit 1 clear and bit 2 clear e g 1111 0001 10 5 2 Broadcast Address A broadcast address is formed from the logical OR of the SADDR and SADEN register...

Page 182: ...nt Table 10 3 summarizes the baud rates that can be used for the four serial I O modes 10 6 1 Baud Rate for Mode 0 The baud rate for mode 0 is fixed at FOSC 12 10 6 2 Baud Rates for Mode 2 Mode 2 has...

Page 183: ...TMOD register Figure 8 5 on page 8 7 Select timer mode 0 3 by programming the M1 M0 bits in the TMOD register In most applications timer 1 is configured as a timer in auto reload mode high nibble of...

Page 184: ...r 2 into its baud rate generator mode Figure 10 5 In this mode a rollover in the TH2 register does not set the TF2 bit in the T2CON register Also a high to low transition at the T2EX pin sets the EXF2...

Page 185: ...Rate Generator s RCLCK Bit TCLCK Bit Receiver Baud Rate Generator Transmitter Baud Rate Generator 0 0 Timer 1 Timer 1 0 1 Timer 1 Timer 2 1 0 Timer 2 Timer 1 1 1 Timer 2 Timer 2 T2EX 2 T2 Timer 1 Ove...

Page 186: ...esults of a read or write may not be accurate In addition you may read but not write to the RCAP2 registers a write may overlap a reload and cause write and or reload errors Table 10 6 lists commonly...

Page 187: ...11 Minimum Hardware Setup...

Page 188: ......

Page 189: ...dware setup that employs the on chip oscillator for the system clock and provides power on reset Control signals and Ports 0 1 2 and 3 are not shown See sections 11 3 Clock Sources and 11 4 4 Power on...

Page 190: ...d VSS They are not required for proper de vice operation thus the 8XC251Sx is compatible with designs that do not provide connections to these pins 11 2 2 Unused Pins To provide stable predictable per...

Page 191: ...high quality components C1 C2 30 pF is adequate for this application Pins XTAL1 and XTAL2 are protected by on chip electrostatic discharge ESD devices D1 and D2 which are diodes parasitic to the RF FE...

Page 192: ...different capacitor values and circuit configuration Consult the manufacturer s data sheet for specific information 11 3 3 External Clock To operate the CHMOS 8XC251Sx from an external clock connect...

Page 193: ...k capacitance i e the Miller effect at power on Once the input waveform requirements are met the input capacitance remains under 20 pF Figure 11 4 External Clock Drive Waveforms 11 4 RESET A device re...

Page 194: ...hardware WDT overflow or the PCA WDT comparison match generates a reset signal WDT initiated resets have the same effect as an external reset See section 8 7 Watchdog Timer and section 9 3 5 PCA Watc...

Page 195: ...at power on connect the RST pin to the VCC pin through a 1 F capacitor as shown in Figure 11 1 When VCC is applied the RST pin rises to VCC then decays exponentially as the capacitor charg es The time...

Page 196: ...8XC251SA SB SP SQ USER S MANUAL 11 8 Figure 11 5 Reset Timing Sequence RST XTAL Internal Reset Routine ALE A4103 01 PSEN 64 TOSC 1 2 3 32 First ALE...

Page 197: ...12 Special Operating Modes...

Page 198: ......

Page 199: ...er off flag and two general purpose flags 12 2 1 Serial I O Control Bits The SMOD1 bit in the PCON register is a factor in determining the serial I O baud rate See Fig ure 12 1 and section 10 6 Baud R...

Page 200: ...a zero to this bit 4 POF Power Off Flag Set by hardware as VCC rises above 3 V to indicate that power has been off or VCC had fallen below 3 V and that on chip volatile memory is indeterminate Set or...

Page 201: ...eset Don t Care Weak High Weak High Floating Weak High Weak High Weak High Idle Internal 1 1 Data Data Data Data Idle External 1 1 Floating Data Data Data Powerdown Internal 0 0 Data Data Data Data Po...

Page 202: ...ion of the program memory Internal program memory the ALE and PSEN pins are pulled high and the ports 0 1 2 and 3 pins are reading data Table 12 1 External program memory the ALE and PSEN pins are pul...

Page 203: ...C251Sx and vectors the CPU to address FF 0000H NOTE During the time that execution resumes the internal RAM cannot be accessed however it is possible for the port pins to be accessed To avoid unexpect...

Page 204: ...t set the IE register EX0 and or EX1 bit s The external interrupt used to exit powerdown mode must be configured as level sensitive and must be assigned the highest priority In addition the duration o...

Page 205: ...ets and the reset waveforms in Figure 11 5 on page 11 8 2 While holding RST asserted apply and hold logic levels to I O pins as follows PSEN low P0 7 5 low P0 4 high P0 3 0 low i e port 0 10H 3 Deasse...

Page 206: ......

Page 207: ...13 External Memory Interface...

Page 208: ......

Page 209: ...r page mode or nonpage mode Page mode pro vides increased performance by reducing the time for external code fetches Page mode does not apply to code fetches from on chip memory The reset routine conf...

Page 210: ...0 All addresses 0 1 All addresses 1 0 All addresses 1 1 All addresses 80 0000H RD O Read or 17th Address Bit A16 Read signal output to external data memory or 17th external address bit A16 depending...

Page 211: ...es It also shows the activity on the bus for nonpage mode and page mode bus cycles with no wait states There are three types of nonpage mode bus cycles code read data read and data write There are fou...

Page 212: ...ite bus cycles Figure 13 4 execute in approximately three state times For the write cycle Figure 13 4 a third state is appended to provide recovery time for the bus Note that the write signal WR is as...

Page 213: ...ss it again requires a two state bus cy cle The following external code fetches are always page miss cycles the first external code fetch after a page rollover the first external code fetch after an e...

Page 214: ...ed on port 0 and memory places the in struction byte on port 2 Notice that a page hit reduces the available address access time by one state Therefore faster memories may be required to support page m...

Page 215: ...External Data Read Page Mode Figure 13 7 External Data Write Page Mode A17 A16 P0 P2 ALE RD PSEN State 1 State 2 XTAL State 3 A2811 04 A15 8 D7 0 A17 A16 A7 0 A17 A16 P0 P2 ALE WR State 1 State 2 XTA...

Page 216: ...SP SQ supports traditional real time wait state operations for dy namic bus control The real time wait state operations are enabled with the WCON SFR bits at address S 0A7H The device can also be conf...

Page 217: ...Mode One RD PSEN Wait State Figure 13 9 External Data Write Nonpage Mode One WR Wait State P0 A17 A16 P2 ALE RD PSEN State 1 State 2 XTAL State 3 A2812 04 A7 0 D7 0 A17 A16 A15 8 P0 A17 A16 P2 ALE WR...

Page 218: ...TH REAL TIME WAIT STATES In addition to fixed length wait states such as RD WR PSEN and ALE the 8XC251SA SB SP SQ offers a real time wait state The programmer can dynamically adjust the delay of the r...

Page 219: ...o drive address signal A17 in some memory designs The A17 address signal always takes priority over other alternate functions in this case both PCA 4 and WCLK Even if RTWCE is enabled in WCON 1 the WC...

Page 220: ...tasheet 13 5 2 Real time WAIT CLOCK Enable RTWCE The real time WAIT CLOCK output is driven at port 1 7 WCLK by writing a logical 1 to the WCON 1 RTWCE bit at S A7H When enabled the WCLK output produce...

Page 221: ...External Data Write Nonpage Mode RT Wait State A0 A7 WCLK ALE RD PSEN WAIT P0 P2 A8 A15 A5007 01 State 1 State 2 State 3 State 1 next cycle A0 A7 D0 D7 stretched A8 A15 stretched RD PSEN stretched A0...

Page 222: ...xternal Data Write Page Mode RT Wait State A8 A15 WCLK ALE RD PSEN WAIT P2 P0 A0 A7 A5008 01 State 1 State 2 State 3 State 1 next cycle A8 A15 D0 D7 stretched A0 A7 stretched RD PSEN stretched A8 A15...

Page 223: ...3 16 If the external memory is set up for page mode it places UCONFIG0 on P2 as D7 0 overwriting A15 8 FFH If external memory is set up for nonpage mode A15 8 is not overwritten The 8XC251Sx examines...

Page 224: ...hose on the 8XC51FX For an external memory instruction using a 16 bit address the port pins carry address and data bits during the bus cycle However if the instruction uses an 8 bit address e g MOVX R...

Page 225: ...the instruction uses an 8 bit address e g MOVX Ri the contents of P2 are driven onto the pins when data is not on the pins These logic levels can be used to select 256 bit pages in external memory Dur...

Page 226: ...ace on page 4 8 Figure 4 5 on page 4 10 and Figure 4 6 on page 4 11 depict the mapping of internal memory space into external memory 13 8 1 Example 1 RD1 0 00 18 bit Bus External Flash and RAM In this...

Page 227: ...ORY INTERFACE Figure 13 18 Address Space for Example 1 A4220 02 1056 Bytes On chip RAM 01 00 FE FF 128 Kbytes External Flash Address Space 256 Kbytes 0000H FFFFH 0420H FFFFH 128 Kbytes 1056 Bytes Exte...

Page 228: ...hat PSEN is asserted for all reads and RD functions as A16 RD1 0 01 Figure 13 20 shows how the external flash and RAM are addressed in the internal address space Addresses 0420H 7FFFH in external RAM...

Page 229: ...MORY INTERFACE Figure 13 20 Address Space for Example 2 A4168 03 1056 Bytes On chip RAM 01 00 FE FF 64 Kbytes External Flash Address Space 256 Kbytes 0000H FFFFH 0420H 32 Kbytes 1056 Bytes External RA...

Page 230: ...of external RAM Figure 13 21 The 87C251SB 83C251SB is configured so that RD functions as A16 and PSEN is asserted for all reads Figure 13 22 shows how the external RAM is addressed in the internal add...

Page 231: ...NTERFACE Figure 13 22 Address Space for Example 3 A4169 03 1056 Bytes On chip RAM 01 00 FE FF 16 Kbytes On chip Code Memory Address Space 256 Kbytes 0000H FFFFH 0420H FFFFH 128 Kbytes 1056 Bytes Exter...

Page 232: ...ion leaves P3 7 RD A16 available for general I O RD1 0 10 A maximum of 64 Kbytes of external memory can be used and all regions of internal memory map into the single 64 Kbyte region in external memor...

Page 233: ...INTERFACE Figure 13 24 Address Space for Example 4 A4224 02 1056 Bytes On chip RAM 01 00 FE FF 16 Kbytes On chip Code Memory Address Space 256 Kbytes FFFFH 0420H FFFFH External RAM 64 Kbytes 1056 Byte...

Page 234: ...ss the real time wait states are selected see Figure 13 11 on page 13 11 The examples that follow illustrate two possibilities for addressing the external RAM 13 8 5 1 An Application Requiring Fast Ac...

Page 235: ...INTERFACE Figure 13 25 Bus Diagram for Example 5 80C251SB in Nonpage Mode A4145 01 A7 0 Latch A15 8 A D7 0 EPROM 64 Kbytes OE CE A15 8 A7 0 D7 0 PSEN 80C251SB RD WR EA P2 P0 D7 0 A15 8 A7 0 RAM 64 Kby...

Page 236: ...ytes On chip RAM 01 00 FE FF 64 Kbytes External EPROM Address Space 256 Kbytes 0000H FFFFH 0420H FFFFH External RAM 64 Kbytes 1056 Bytes 1056 Bytes On chip RAM 01 00 FE FF 64 Kbytes External EPROM Add...

Page 237: ...for addresses 7F FFFFH and PSEN is asserted for addresses 80 0000 This system is the same as Example 5 Figure 13 25 except that it operates in page mode Ac cordingly the two systems have the same mem...

Page 238: ...e upper address bits A15 0 and the data D7 0 while port 0 carries only the lower address bits A7 0 The 80C251SB is configured for a single read signal PSEN The 128 Kbytes of external flash are accesse...

Page 239: ...14 Programming and Verifying Nonvolatile Memory...

Page 240: ......

Page 241: ...g the signature bytes 3 bytes Programming instructions apply to the 87C251Sx one time programmable ROM OTPROM and erasable programmable ROM EPROM Verify instructions apply to the 87C251Sx the 83C251Sx...

Page 242: ...ternal addresses For a detailed discussion of device configuration see Chapter 4 ROM OTPROM EPROM devices have on chip user code memory at FF 0000 FF 1FFFH 8 Kbytes or FF 0000H FF 3FFFH 16 Kbytes Addr...

Page 243: ...memory for devices without ROM OTPROM EPROM Figure 4 2 on page 4 3 14 3 GENERAL SETUP Figure 14 1 shows the general setup for programming and verifying nonvolatile memory on the 87C251Sx The figure a...

Page 244: ...gh 29H data FFF8H FFFFH 4 Program Mode Lock Bits 87C251Sx High Low 5 V 12 75 V 25 Pulses 6BH data 0001H 0003H 1 2 Verify Mode Lock bits 87C251Sx 83C251Sx High Low 5 V High 2BH data 0000H 3 Program Mod...

Page 245: ...on chip code memory and the configuration bytes and 25 times for the encryption array and the lock bits 6 Reduce the voltage on the VPP pin to 5 V 7 If the procedure is program immediate verify go to...

Page 246: ...controller for operation in the appropriate mode according to Table 14 1 2 Input the 16 bit address on ports P1 and P3 3 Wait for the data on port P2 to become valid TAVQV 48 clock cycles see the dat...

Page 247: ...8H and UCONFIG1 FF FFF9H are imple mented the remaining bytes are reserved for future use See Figure 4 1 on page 4 2 Figure 4 3 on page 4 6 and Figure 4 4 on page 4 7 To program the 87C251Sx configura...

Page 248: ...cryption array perform the procedure described in section 14 4 Programming Algorithm using the program encryption array mode Table 14 1 To preserve the secrecy of the encryption key byte sequence the...

Page 249: ...f nonvolatile memory on the 83C251Sx see 14 6 Programmable Functions for each function desired Or more directly perform the verification procedure described in 14 5 Verify Algorithm using the appropri...

Page 250: ......

Page 251: ...A Instruction Set Reference...

Page 252: ......

Page 253: ...ons Table A 19 Compare Instructions Table A 20 Increment and Decrement Instructions Table A 21 Multiply Divide and Decimal adjust Instructions Table A 22 Logical Instructions Table A 23 Move Instructi...

Page 254: ...ry location 00 0000H 00 FFFFH addressed indirectly through word register WR0 WR30 WRj Data RAM location 00 0000H 00 FFFFH addressed indirectly dis16 through a word register WR0 WR30 displacement value...

Page 255: ...MCS 251 Arch MCS 51 Arch bit y y y A directly addressed bit in memory locations 00 0020H 00 007FH or in any defined SFR A binary representation of the bit number 0 7 within a byte bit51 A directly add...

Page 256: ...Z rel AJMP addr11 XRL dir8 A XRL dir8 data XRL A data XRL A dir8 XRL A Ri XRL A Rn 7 JNZ rel ACALL addr11 ORL CY bit JMP A DPTR MOV A data MOV dir8 data MOV Ri data MOV Rn data 8 SJMP rel AJMP addr11...

Page 257: ...s ORL Rm Rm ORL WRj WRj ORL reg op2 2 5 JSGE rel MOV WRj dis WRj ANL Rm Rm ANL WRj WRj ANL reg op2 2 6 JE rel MOV WRj DRk dis XRL Rm Rm XRL WRj WRj XRL reg op2 2 7 JNE rel MOV DRk dis WRj MOV op1 reg...

Page 258: ...r Oper Rm dir16 x E m 0011 dir16 addr high dir16 addr low Oper WRj dir16 x E j 2 0111 dir16 addr high dir16 addr low Oper DRk dir16 1 x E k 4 1111 dir16 addr high dir16 addr low Oper Rm WRj x E j 2 10...

Page 259: ...nstruction as given in Table A 10 Table A 10 Bit Instructions Instruction Byte 0 x Byte 1 Byte 2 Byte 3 1 Bit Instr dir8 A 9 xxxx 0 bit dir8 addr rel addr Table A 11 Byte 1 High Nibble for Bit Instruc...

Page 260: ...4 0001 POP Rm D A m 1000 POP WRj D A j 2 1001 POP DRk D A k 4 1011 Table A 13 Control Instructions Instruction Byte 0 x Byte 1 Byte 2 Byte 3 EJMP addr24 8 A addr 23 16 addr 15 8 addr 7 0 ECALL addr24...

Page 261: ...m k 4 dis 15 8 dis 7 0 MOV DRk dis WRj 7 9 j 2 k 4 dis 15 8 dis 7 0 MOVS WRj Rm 1 A j 2 m MOVZ WRj Rm 0 A j 2 m MOV WRj WRj 0 B j 2 1000 j 2 0000 MOV WRj DRk 0 B k 4 1010 j 2 0000 MOV WRj WRj 1 B j 2...

Page 262: ...NC DRk short 0 B k 4 11 ss 4 DEC Rm short 1 B m 00 ss 5 DEC WRj short 1 B j 2 01 ss 6 DEC DRk short 1 B k 4 11 ss Table A 16 Encoding for INC DEC ss short 00 1 01 2 10 4 Table A 17 Shifts Instruction...

Page 263: ...Execution Times for Instructions that Access the Port SFRs The execution times for some instructions increase when the instruction accesses a port SFR Px x 0 3 as opposed to any other SFR Table A 18 l...

Page 264: ...dir8 data 3 3 2 4 6 8 ANL dir8 A 2 2 2 4 6 8 ANL Rm dir8 3 2 1 2 3 4 CLR bit 4 3 2 4 6 8 CLR bit51 2 2 2 4 6 8 CMP Rm dir8 3 2 1 2 3 4 CPL bit 4 3 2 4 6 8 CPL bit51 2 2 2 4 6 8 DEC dir8 2 2 2 4 6 8 I...

Page 265: ...8 SETB bit51 2 2 2 4 6 8 SUB Rm dir8 3 2 1 2 3 4 SUBB A dir8 1 1 1 2 3 4 XCH A dir8 3 3 2 4 6 8 XRL A dir8 1 1 1 2 3 4 XRL dir8 data 3 3 2 4 6 8 XRL dir8 A 2 2 2 4 6 8 XRL Rm dir8 3 2 1 2 3 4 Table A...

Page 266: ...g to from dword reg 3 5 2 4 Rm data Immediate 8 bit data to from byte reg 4 3 3 2 WRj data16 Immediate 16 bit data to from word reg 5 4 4 3 DRk 0data16 16 bit unsigned immediate data to from dword reg...

Page 267: ...3 3 2 WRj data16 Word reg with immediate 16 bit data 5 4 4 3 DRk 0data16 Dword reg with zero extended 16 bit immediate data 5 6 4 5 DRk 1data16 Dword reg with one extended 16 bit immediate data 5 6 4...

Page 268: ...cell denotes an instruction in the MCS 51 architecture 2 If this instruction addresses an I O port Px x 0 3 add 2 to the number of states Table A 22 Summary of Multiply Divide and Decimal adjust Instr...

Page 269: ...reg 3 3 2 2 Rm data 8 bit data to byte reg 4 3 3 2 WRj data16 16 bit data to word reg 5 4 4 3 Rm dir8 Dir addr to byte reg 4 3 3 3 2 3 WRj dir8 Dir addr to word reg 4 4 3 3 Rm dir16 Dir addr 64K to by...

Page 270: ...cal OR ORL dest src dest opnd dest opnd V src opnd Logical Exclusive OR XRL dest src dest opnd dest opnd src opnd Clear CLR A A 0 Complement CPL A Ai Ai Rotate RXX A 1 Shift SXX Rm or Wj 1 SWAP A A3 0...

Page 271: ...yte 3 3 3 3 dir8 Ri Indir RAM to dir byte 2 3 3 4 dir8 data Immediate data to dir byte 3 3 3 3 3 3 Ri A Acc to indir RAM 1 3 2 4 Ri dir8 Dir byte to indir RAM 2 3 3 4 Ri data Immediate data to indir R...

Page 272: ...e reg 5 6 4 5 WRj WRj dis16 Indir addr with disp 64K to word reg 5 7 4 6 Rm DRk dis24 Indir addr with disp 16M to byte reg 5 7 4 6 WRj DRk dis24 Indir addr with disp 16M to word reg 5 8 4 7 WRj dis16...

Page 273: ...t addr 4 1 5 1 5 Table A 24 Summary of Move Instructions Continued Move 2 MOV dest src destination src opnd Move with Sign Extension MOVS dest src destination src opnd with sign extend Move with Zero...

Page 274: ...XCHD A Ri Acc and low nibble in on chip RAM 8 bit addr 1 4 2 5 PUSH dir8 Push dir byte onto stack 2 2 2 2 data Push immediate data onto stack 4 4 3 3 data16 Push 16 bit immediate data onto stack 5 5...

Page 275: ...1 1 1 bit51 Complement dir bit 2 2 2 2 2 2 bit Complement dir bit 4 4 2 3 3 2 ANL CY bit51 AND dir bit to carry 2 1 3 2 1 3 CY bit AND dir bit to carry 4 3 3 3 2 3 ANL CY bit51 AND complemented dir b...

Page 276: ...mp indir relative to the DPTR 1 5 1 5 JC rel Jump if carry is set 2 1 4 2 1 4 JNC rel Jump if carry not set 2 1 4 2 1 4 JB bit51 rel Jump if dir bit is set 3 2 5 3 2 5 bit rel Jump if dir bit of 8 bit...

Page 277: ...o reg and jump if not equal 3 2 5 4 3 6 Ri data rel Compare immediate to indir and jump if not equal 3 3 6 4 4 7 DJNZ Rn rel Decrement reg and jump if not zero 2 2 5 3 3 6 dir8 rel Decrement dir byte...

Page 278: ...nating bits 15 11 of the incremented PC opcode bits 7 5 and the second byte of the instruction The subroutine called must therefore start within the same 2 Kbyte page of the program memory as the firs...

Page 279: ...t out of bit 7 or a carry out of bit 7 but not bit 6 the OV flag is set When adding signed integers the OV flag indicates a negative number produced as the sum of two positive operands or a positive s...

Page 280: ...ding Source Mode Encoding Operation ADD A A dir8 ADD A Ri Binary Mode Source Mode Bytes 1 2 States 2 3 Hex Code in Binary Mode Encoding Source Mode A5 Encoding Operation ADD A A Ri ADD A Rn Binary Mod...

Page 281: ...js ADD DRkd DRks Binary Mode Source Mode Bytes 3 2 States 5 4 Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation ADD DRkd DRkd DRks ADD Rm data Binary Mode Source Mode Bytes 4 3 States...

Page 282: ...e Mode Encoding Operation ADD DRk DRk data16 ADD Rm dir8 Binary Mode Source Mode Bytes 4 3 States 3 2 If this instruction addresses a port Px x 0 3 add 1 state Hex Code in Binary Mode A5 Encoding Sour...

Page 283: ...r16 ADD WRj dir16 Binary Mode Source Mode Bytes 5 4 States 4 3 Encoding Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation ADD WRj WRj dir16 ADD Rm WRj Binary Mode Source Mode Bytes 4...

Page 284: ...bit 7 or a carry out of bit 7 but not bit 6 the OV flag is set When adding signed integers the OV flag indicates a negative number produced as the sum of two positive operands or a positive sum from t...

Page 285: ...ncoding Source Mode Encoding Operation ADDC A A CY dir8 ADDC A Ri Binary Mode Source Mode Bytes 1 2 States 2 3 Hex Code in Binary Mode Encoding Source Mode A5 Encoding Operation ADDC A A CY Ri ADDC A...

Page 286: ...Bytes 2 2 States 3 3 Hex Code in Binary Mode Encoding Source Mode Encoding Operation AJMP PC PC 2 PC 10 0 page address ANL dest src Function Logical AND Description Performs the bitwise logical AND op...

Page 287: ...er or accumulator at run time The instruction ANL P1 01110011B clears bits 7 3 and 2 of output port 1 Variations ANL dir8 A Binary Mode Source Mode Bytes 2 2 States 2 2 If this instruction addresses a...

Page 288: ...ding Source Mode Encoding Operation ANL A A dir8 ANL A Ri Binary Mode Source Mode Bytes 1 2 States 2 3 Hex Code in Binary Mode Encoding Source Mode A5 Encoding Operation ANL A A Ri ANL A Rn Binary Mod...

Page 289: ...Rm data Binary Mode Source Mode Bytes 4 3 States 3 2 Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation ANL Rm Rm data ANL WRj data16 Binary Mode Source Mode Bytes 5 4 States 4 3 Encod...

Page 290: ...de Bytes 4 3 States 4 3 Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation ANL WRj WRj dir8 ANL Rm dir16 Binary Mode Source Mode Bytes 5 4 States 3 2 Encoding Hex Code in Binary Mode A...

Page 291: ...Operation ANL Rm Rm DRk ANL CY src bit Function Logical AND for bit variables Description If the Boolean value of the source bit is a logical 0 clear the CY flag otherwise leave the CY flag in its cur...

Page 292: ...Binary Mode Encoding Source Mode Encoding Operation ANL CY CY bit51 ANL CY bit51 Binary Mode Source Mode Bytes 2 2 States 1 1 If this instruction addresses a port Px x 0 3 add 1 state Hex Code in Bin...

Page 293: ...wo operands allow four addressing mode combinations the accumulator may be compared with any directly addressed byte or immediate data and any indirect RAM location or working register can be compared...

Page 294: ...A data THEN CY 1 ELSE CY 0 CJNE A dir8 rel Binary Mode Source Mode Not Taken Taken Not Taken Taken Bytes 3 3 3 3 States 3 6 3 6 Hex Code in Binary Mode Encoding Source Mode Encoding Operation PC PC 3...

Page 295: ...s 2 5 3 6 Hex Code in Binary Mode Encoding Source Mode A5 Encoding Operation PC PC 3 IF Rn data THEN PC PC relative offset IF Rn data THEN CY 1 ELSE CY 0 CLR A Function Clear accumulator Description C...

Page 296: ...instructions with CY as the operand Example Port 1 contains 5DH 01011101B After executing the instruction CLR P1 2 port 1 contains 59H 01011001B Variations CLR bit51 Binary Mode Source Mode Bytes 4 3...

Page 297: ...g is set otherwise it is clear When subtracting signed integers the OV flag indicates a negative result when a negative value is subtracted from a positive value or a positive result when a positive v...

Page 298: ...d WRjs CMP DRkd DRks Binary Mode Source Mode Bytes 3 2 States 5 4 Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation CMP DRkd DRks CMP Rm data Binary Mode Source Mode Bytes 4 3 States...

Page 299: ...e A5 Encoding Source Mode Encoding Operation CMP DRk 0data16 CMP DRk 1data16 Binary Mode Source Mode Bytes 5 4 States 6 5 Encoding Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation CM...

Page 300: ...Mode Source Mode Bytes 5 4 States 3 2 Encoding Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation CMP Rm dir16 CMP WRj dir16 Binary Mode Source Mode Bytes 5 4 States 4 3 Encoding Hex...

Page 301: ...g Operation CMP Rm DRk CPL A Function Complement accumulator Description Logically complements each bit of the accumulator one s complement Clear bits are set and set bits are cleared Flags Example Th...

Page 302: ...the output data latch not the input pin Flags Only for instructions with CY as the operand Example Port 1 contains 5BH 01011101B After executing the instruction sequence CPL P1 1 CPL P1 2 port 1 cont...

Page 303: ...carry out of the lowest 4 bits propagated through all higher bits but it does not clear the CY flag otherwise If the CY flag is now set or if the upper four bits now exceed nine 1010XXXX 1111XXXX the...

Page 304: ...iables can be incremented or decremented by adding 01H or 99H If the accumulator contains 30H representing the digits of 30 decimal then the instruction sequence ADD A 99H DA A leaves the CY flag set...

Page 305: ...ry Mode Source Mode Bytes 1 1 States 1 1 Hex Code in Binary Mode Encoding Source Mode Encoding Operation DEC A A 1 DEC dir8 Binary Mode Source Mode Bytes 2 2 States 2 2 If this instruction addresses a...

Page 306: ...nd by 1 2 or 4 An original value of 00H underflows to 0FFH Flags Example Register 0 contains 7FH 01111111B After executing the instruction sequence DEC R0 1 register 0 contains 7EH Variations DEC Rm s...

Page 307: ...esides the 8 bit remainder is stored in the lower byte of the word where Rmd resides For example Register 1 contains 251 0FBH or 11111011B and register 5 contains 18 12H or 00010010B After executing t...

Page 308: ...d WRjs WRjd 2 remainder WRjd WRjs if dest jd 2 6 10 30 WRjd quotient WRjd WRjs For word operands dest src WRjd WRjs the 16 bit quotient is in WR jd 2 and the 16 bit remainder is in WRjd For example fo...

Page 309: ...ding Source Mode Encoding Operation DIV A quotient A B B remainder A B DJNZ byte rel addr Function Decrement and jump if not zero Description Decrements the specified location by 1 and branches to the...

Page 310: ...to 512 machine cycles with a single instruction The instruction sequence toggles P1 7 eight times causing four output pulses to appear at bit 7 of output Port 1 Each pulse lasts three states two for D...

Page 311: ...truction Program execution continues with the instruction at this address The subroutine may therefore begin anywhere in the full 16 Mbyte memory space Flags Example The stack pointer contains 07H and...

Page 312: ...order and 16 bits of the low order words of the PC with the second third and fourth instruction bytes The destination may be therefore be anywhere in the full 16 Mbyte memory space Flags Example The...

Page 313: ...23H and 49H respectively After executing the instruction ERET the stack pointer contains 08H and program execution continues at location 012349H Binary Mode Source Mode Bytes 3 2 States 10 9 Hex Code...

Page 314: ...INC A Binary Mode Source Mode Bytes 1 1 States 1 1 Hex Code in Binary Mode Encoding Source Mode Encoding Operation INC A A 1 INC dir8 Binary Mode Source Mode Bytes 2 2 States 2 2 If this instruction a...

Page 315: ...ginal value of 0FFH overflows to 00H Flags Example Register 0 contains 7EH 011111110B After executing the instruction INC R0 1 register 0 contains 7FH Variations INC Rm short Binary Mode Source Mode B...

Page 316: ...ormed an overflow of the low byte of the data pointer DPL from 0FFH to 00H increments the high byte of the data pointer DPH by one An overflow of the high byte DPH does not increment the high word of...

Page 317: ...tains 11001010B and the accumulator contains 56 01010110B After the instruction sequence JB P1 2 LABEL1 JB ACC 2 LABEL2 program execution continues at label LABEL2 Variations JB bit51 rel Binary Mode...

Page 318: ...e first byte of the next instruction Note When this instruction is used to test an output pin the value used as the original data is read from the output data latch not the input pin Flags Example The...

Page 319: ...h the next instruction The branch destination is computed by adding the signed relative displacement in the second instruction byte to the PC after incrementing the PC twice Flags Example The CY flag...

Page 320: ...tion JE LABEL1 program execution continues at label LABEL1 Binary Mode Source Mode Not Taken Taken Not Taken Taken Bytes 3 3 2 2 States 2 5 1 4 Hex Code in Binary Mode A5 Encoding Source Mode Encoding...

Page 321: ...n If the Z flag or the CY flag is set branch to the address specified otherwise proceed with the next instruction The branch destination is computed by adding the signed relative displacement in the s...

Page 322: ...tor contains 04H at the start this sequence execution jumps to LABEL2 Remember that AJMP is a two byte instruction so the jump instructions start at every other address Binary Mode Source Mode Bytes 1...

Page 323: ...ode Not Taken Taken Not Taken Taken Bytes 3 3 3 3 States 2 5 2 5 Hex Code in Binary Mode Encoding Source Mode Encoding Operation JNB PC PC 3 IF bit51 0 THEN PC PC rel JNB bit rel Binary Mode Source Mo...

Page 324: ...nd causes program execution to continue at label LABEL2 Binary Mode Source Mode Not Taken Taken Not Taken Taken Bytes 2 2 2 2 States 1 4 1 4 Hex Code in Binary Mode Encoding Source Mode Encoding Opera...

Page 325: ...s computed by adding the signed relative displacement in the second instruction byte to the PC after incrementing the PC twice The accumulator is not modified Flags Example The accumulator contains 00...

Page 326: ...ame value Binary Mode Source Mode Not Taken Taken Not Taken Taken Bytes 3 3 2 2 States 2 5 1 4 Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation JSG PC PC 2 IF N 0 AND N OV THEN PC PC...

Page 327: ...the next instruction The branch destination is computed by adding the signed relative displacement in the second instruction byte to the PC after incrementing the PC twice Flags Example The instructio...

Page 328: ...if the Z flag is set OR if the N flag and the OV flag have different values Binary Mode Source Mode Not Taken Taken Not Taken Taken Bytes 3 3 2 2 States 2 5 1 4 Hex Code in Binary Mode A5 Encoding So...

Page 329: ...esult onto the stack low byte first The stack pointer is incremented by two The high and low bytes of the PC are then loaded respectively with the second and third bytes of the LCALL instruction Progr...

Page 330: ...tional branch to the specified address by loading the high and low bytes of the PC respectively with the second and third instruction bytes The destination may therefore be anywhere in the 64 Kbyte me...

Page 331: ...on Twenty four combinations of source and destination addressing modes are allowed Flags Example On chip RAM location 30H contains 40H on chip RAM location 40H contains 10H and input port 1 contains 1...

Page 332: ...ng Operation MOV dir8 data MOV Ri data Binary Mode Source Mode Bytes 2 3 States 3 4 Hex Code in Binary Mode Encoding Source Mode A5 Encoding Operation MOV Ri data MOV Rn data Binary Mode Source Mode B...

Page 333: ...e Source Mode Bytes 2 3 States 2 3 If this instruction addresses a port Px x 0 3 add 1 state Hex Code in Binary Mode Encoding Source Mode A5 Encoding Operation MOV dir8 Rn MOV Ri dir8 Binary Mode Sour...

Page 334: ...is instruction addresses a port Px x 0 3 add 1 state Hex Code in Binary Mode Encoding Source Mode Encoding Operation MOV A dir8 MOV A Ri Binary Mode Source Mode Bytes 1 2 States 2 3 Hex Code in Binary...

Page 335: ...Ri A Binary Mode Source Mode Bytes 1 2 States 3 4 Hex Code in Binary Mode Encoding Source Mode A5 Encoding Operation MOV Ri A MOV Rn A Binary Mode Source Mode Bytes 1 2 States 1 2 Hex Code in Binary...

Page 336: ...V DRkd DRks Binary Mode Source Mode Bytes 3 2 States 3 2 Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation MOV DRkd DRks MOV Rm data Binary Mode Source Mode Bytes 4 3 States 3 2 Hex C...

Page 337: ...de Source Mode Bytes 5 4 States 5 4 Encoding Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation MOV DRk 1data16 MOV Rm dir8 Binary Mode Source Mode Bytes 4 3 States 3 2 If this instruc...

Page 338: ...6 5 Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation MOV DRk dir8 MOV Rm dir16 Binary Mode Source Mode Bytes 5 4 States 3 2 Encoding Hex Code in Binary Mode A5 Encoding Source Mode E...

Page 339: ...inary Mode Source Mode Bytes 4 3 States 2 2 Encoding Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation MOV Rm WRj MOV Rm DRk Binary Mode Source Mode Bytes 4 3 States 4 3 Encoding Hex...

Page 340: ...nary Mode A5 Encoding Source Mode Encoding Operation MOV WRj DRk MOV dir8 Rm Binary Mode Source Mode Bytes 4 3 States 4 3 If this instruction addresses a port Px x 0 3 add 1 state Hex Code in Binary M...

Page 341: ...Mode Bytes 5 4 States 4 3 Encoding Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation MOV dir16 Rm MOV dir16 WRj Binary Mode Source Mode Bytes 5 4 States 5 4 Encoding Hex Code in Binar...

Page 342: ...Mode A5 Encoding Source Mode Encoding Operation MOV WRj Rm MOV DRk Rm Binary Mode Source Mode Bytes 4 3 States 5 4 Encoding Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation MOV DRk R...

Page 343: ...WRj MOV Rm WRj dis16 Binary Mode Source Mode Bytes 5 4 States 6 5 Encoding Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation MOV Rm WRj dis MOV WRj WRj dis16 Binary Mode Source Mode B...

Page 344: ...7 Encoding Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation MOV WRj DRk dis MOV WRj dis16 Rm Binary Mode Source Mode Bytes 5 4 States 6 5 Encoding Hex Code in Binary Mode A5 Encoding...

Page 345: ...Encoding Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation MOV DRk dis WRj MOV dest bit src bit Function Move bit data Description Copies the Boolean variable specified by the second...

Page 346: ...0 3 add 2 states Hex Code in Binary Mode Encoding Source Mode Encoding Operation MOV bit51 CY MOV CY bit51 Binary Mode Source Mode Bytes 2 2 States 1 1 If this instruction addresses a port Px x 0 3 ad...

Page 347: ...ointer DPTR with the specified 16 bit constant The high byte of the constant is loaded into the high byte of the data pointer DPH The low byte of the constant is loaded into the low byte of the data p...

Page 348: ...ween 0 and 3 The following instruction sequence translates the value in the accumulator to one of four values defined by the DB define byte directive If the subroutine is called with the accumulator e...

Page 349: ...nstruction MOVH DRk 1122H executes DRk contains 1122 7788H Variations MOVH DRk data16 Binary Mode Source Mode Bytes 5 4 States 3 2 Encoding Hex Code in Binary Mode A5 Encoding Source Mode Encoding Ope...

Page 350: ...es an 8 bit address on port 0 Eight bits are sufficient for external I O expansion decoding or for a relatively small RAM array For larger arrays any port pins can be used to output higher address bit...

Page 351: ...the instruction sequence MOVX A R1 MOVX R0 A the accumulator and external RAM location 12H contain 56H Variations MOVX A DPTR Binary Mode Source Mode Bytes 1 1 States 5 5 Hex Code in Binary Mode Enco...

Page 352: ...f the 16 bit register is filled with zeros Flags Example Eight bit register Rm contains 055H 01010101B and 16 bit register WRj contains 0FFFFH 11111111 11111111B The instruction MOVZ WRj Rm moves the...

Page 353: ...red in the following word register In this operation the OV flag is set if the product is greater than 0FFFFH otherwise it is cleared The CY flag is always cleared The N flag is set when the MSB of th...

Page 354: ...the 16 bit product is left in the accumulator and the high byte is left in register B If the product is greater than 255 0FFH the OV flag is set otherwise it is clear The CY flag is always clear Flags...

Page 355: ...dest src Function Logical OR for byte variables Description Performs the bitwise logical OR operation V between the specified variables storing the results in the destination operand The destination o...

Page 356: ...r at run time After executing the instruction ORL P1 00110010B sets bits 5 4 and 1 of output Port 1 Variations ORL dir8 A Binary Mode Source Mode Bytes 2 2 States 2 2 If this instruction addresses a p...

Page 357: ...Operation ORL A A V dir8 ORL A Ri Binary Mode Source Mode Bytes 1 2 States 2 3 Hex Code in Binary Mode Encoding Source Mode A5 Encoding Operation ORL A A V Ri ORL A Rn Binary Mode Source Mode Bytes 1...

Page 358: ...WRjd WRjd V WRjs ORL Rm data Binary Mode Source Mode Bytes 4 3 States 3 2 Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation ORL Rm Rm V data ORL WRj data16 Binary Mode Source Mode By...

Page 359: ...s 4 3 States 4 3 Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation ORL WRj WRj V dir8 ORL Rm dir16 Binary Mode Source Mode Bytes 5 4 States 3 2 Encoding Hex Code in Binary Mode A5 Enc...

Page 360: ...coding Source Mode Encoding Operation ORL Rm Rm V DRk ORL CY src bit Function Logical OR for bit variables Description Sets the CY flag if the Boolean value is a logical 1 leaves the CY flag in its cu...

Page 361: ...coding Source Mode Encoding Operation ORL CY CY V bit51 ORL CY bit51 Binary Mode Source Mode Bytes 2 2 States 1 1 If this instruction addresses a port Px x 0 3 add 1 state Hex Code in Binary Mode Enco...

Page 362: ...rred to the newly addressed location which can be 8 bit or 16 bit Flags Example The stack pointer contains 32H and on chip RAM locations 30H through 32H contain 01H 23H and 20H respectively After exec...

Page 363: ...POP Rm SP SP SP 1 POP WRj Binary Mode Source Mode Bytes 3 2 States 5 4 Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation POP SP SP 1 WRj SP SP SP 1 POP DRk Binary Mode Source Mode Byt...

Page 364: ...H After executing the instruction sequence PUSH DPL PUSH DPH the stack pointer contains 0BH and on chip RAM locations 0AH and 0BH contain 01H and 23H respectively Variations PUSH dir8 Binary Mode Sour...

Page 365: ...H Rm Binary Mode Source Mode Bytes 3 2 States 4 3 Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation PUSH SP SP 1 SP Rm PUSH WRj Binary Mode Source Mode Bytes 3 2 States 5 4 Hex Code i...

Page 366: ...nues at the resulting address which normally is the instruction immediately following ACALL or LCALL Flags Example The stack pointer contains 0BH and on chip RAM locations 0AH and 0BH contain 01H and...

Page 367: ...ected For either value of INTR hardware restores the interrupt logic to accept additional interrupts at the same priority level as the one just processed Program execution continues at the return addr...

Page 368: ...After executing the instruction RL A the accumulator contains 8BH 10001011B the CY flag is unaffected Binary Mode Source Mode Bytes 1 1 States 1 1 Hex Code in Binary Mode Encoding Source Mode Encodin...

Page 369: ...A 0 CY CY A 7 RR A Function Rotate accumulator right Description Rotates the 8 or 16 bits in the accumulator one bit to the right Bit 0 is moved into the bit 7 or 15 position Flags Example The accumul...

Page 370: ...62 01100010B and the CY flag is set Binary Mode Source Mode Bytes 1 1 States 1 1 Hex Code in Binary Mode Encoding Source Mode Encoding Operation RRC A a A a 1 A 7 CY CY A 0 SETB bit Function Set bit...

Page 371: ...his instruction addresses a port Px x 0 3 add 2 states Encoding Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation SETB bit 1 SJMP rel Function Short jump Description Program control b...

Page 372: ...would be a one instruction infinite loop Binary Mode Source Mode Bytes 2 2 States 4 4 Hex Code in Binary Mode Encoding Source Mode Encoding Operation SJMP PC PC 2 PC PC rel SLL src Function Shift log...

Page 373: ...ription Shifts the specified variable to the arithmetic right by 1 bit The MSB is unchanged The bit shifted out LSB is stored in the CY bit Flags Example Register 1 contains 0C5H 11000101B After execu...

Page 374: ...the right by 1 bit replacing the MSB with a zero The bit shifted out LSB is stored in the CY bit Flags Example Register 1 contains 0C5H 11000101B After executing the instruction SRL register 1 Regist...

Page 375: ...is subtracted from a positive value or a positive result when a positive number is subtracted from a negative number Bit 7 in this description refers to the most significant byte of the operand 8 16 o...

Page 376: ...DRkd DRks Binary Mode Source Mode Bytes 3 2 States 5 4 Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation SUB DRkd DRkd DRks SUB Rm data Binary Mode Source Mode Bytes 4 3 States 3 2 H...

Page 377: ...Mode Bytes 4 3 States 3 2 If this instruction addresses a port Px x 0 3 add 1 state Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation SUB Rm Rm dir8 SUB WRj dir8 Binary Mode Source M...

Page 378: ...ding Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation SUB WRj WRj dir16 SUB Rm WRj Binary Mode Source Mode Bytes 4 3 States 3 2 Encoding Hex Code in Binary Mode A5 Encoding Source Mo...

Page 379: ...gative number produced when a negative value is subtracted from a positive value or a positive result when a positive number is subtracted from a negative number Bit 6 and bit 7 in this description re...

Page 380: ...e Encoding Source Mode Encoding Operation SUBB A A CY dir8 SUBB A Ri Binary Mode Source Mode Bytes 1 2 States 2 3 Hex Code in Binary Mode Encoding Source Mode A5 Encoding Operation SUBB A A CY Ri SUBB...

Page 381: ...y Mode Encoding Source Mode Encoding Operation SWAP A 3 0 A 7 4 TRAP Function Causes interrupt call Description Causes an interrupt call that is vectored through location 0FF007BH The operation of thi...

Page 382: ...ariable The source destination operand can use register direct or register indirect addressing Flags Example R0 contains the address 20H the accumulator contains 3FH 00111111B and on chip RAM location...

Page 383: ...he low nibble of the accumulator bits 3 0 generally representing a hexadecimal or BCD digit with that of the on chip RAM location indirectly addressed by the specified register Does not affect the hig...

Page 384: ...or immediate data Note When this instruction is used to modify an output port the value used as the original port data is read from the output data latch not the input pins Flags Example The accumula...

Page 385: ...dir8 dir8 data XRL A data Binary Mode Source Mode Bytes 2 2 States 1 1 Hex Code in Binary Mode Encoding Source Mode Encoding Operation XRL A A data XRL A dir8 Binary Mode Source Mode Bytes 2 2 States...

Page 386: ...de Encoding Source Mode A5 Encoding Operation XRL A A Rn XRL Rmd Rms Binary Mode Source Mode Bytes 3 2 States 2 1 Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation XRL Rmd Rmd Rms XRL...

Page 387: ...Source Mode Encoding Operation XRL WRj WRj data16 XRL Rm dir8 Binary Mode Source Mode Bytes 4 3 States 3 2 If this instruction addresses a port Px x 0 3 add 1 state Hex Code in Binary Mode A5 Encoding...

Page 388: ...m dir16 XRL WRj dir16 Binary Mode Source Mode Bytes 5 4 States 4 3 Encoding Hex Code in Binary Mode A5 Encoding Source Mode Encoding Operation XRL WRj WRj dir16 XRL Rm Wrj Binary Mode Source Mode Byte...

Page 389: ...TION SET REFERENCE XRL Rm Drk Binary Mode Source Mode Bytes 4 3 States 4 3 Encoding Hex Code In Binary Mode A5 Encoding Source Mode Encoding Operation XRL Rm Rm DRk 0 1 1 0 1 1 1 0 u u u u 1 0 1 1 s s...

Page 390: ......

Page 391: ...B Signal Descriptions...

Page 392: ......

Page 393: ...RD WR and PSEN pins for exter nal memory accesses Figure B 1 8XC251SA SB SP SQ 44 pin PLCC Package AD4 P0 4 AD5 P0 5 AD6 P0 6 AD7 P0 7 EA VPP VSS2 ALE PROG PSEN A15 P2 7 A14 P2 6 A13 P2 5 P1 4 CEX1 P...

Page 394: ...WAIT 8 7 AD7 P0 7 36 32 P1 7 CEX4 A17WCLK 9 8 A8 P2 0 24 21 P3 0 RXD 11 10 A9 P2 1 25 22 P3 1 TXD 13 11 A10 P2 2 26 23 P3 4 T0 16 14 A11 P2 3 27 24 P3 5 T1 17 15 A12 P2 4 28 25 A13 P2 5 29 26 Power G...

Page 395: ...formation is available on lines A15 8 and AD7 0 An external latch can use ALE to demultiplex the address from the address data bus PROG The descriptions of A15 8 P2 7 0 and AD7 0 P0 7 0 are for the no...

Page 396: ...0 P1 0 P1 1 P1 2 P1 5 3 P1 6 P1 7 I O Port 1 This is an 8 bit bidirectional I O port with internal pullups T2 T2EX ECI CEX2 0 CEX3 WAIT CEX4 A17 WCLK P2 7 0 I O Port 2 This is an 8 bit bidirectional...

Page 397: ...smit Serial Data TXD outputs the shift clock in serial I O mode 0 and transmits serial data in serial I O modes 1 2 and 3 P3 1 VCC PWR Supply Voltage Connect this pin to the 5V supply voltage VCC2 PWR...

Page 398: ...cillator frequency P1 7 CEX4 A17 WR O Write Write signal output to external memory Asserted for the memory address range specified by configuration byte UCONFIG0 bits RD1 0 Table B 3 Also see RD P3 6...

Page 399: ...to all memory locations 128 Kbyte external memory 1 0 P1 7 CEX4 WCLK P3 7 only Asserted for all addresses Asserted for writes to all memory locations 64 Kbyte external memory One additional port pin...

Page 400: ......

Page 401: ...C Registers...

Page 402: ......

Page 403: ...Tables C 2 through C 6 list the SFRs by functional category Table C 7 lists the regis ters that make up the register file The remainder of the appendix contains descriptions of the SFRs arranged in al...

Page 404: ...00000 PSW1 00000000 D7 C8 T2CON 00000000 T2MOD xxxxxx00 RCAP2L 00000000 RCAP2H 00000000 TL2 00000000 TH2 00000000 CF C0 C7 B8 IPL0 x0000000 SADEN 00000000 SPH 00000000 BF B0 P3 11111111 IPH0 x0000000...

Page 405: ...H High Byte of DPTR S 83H DPXL Data Pointer Extended Low S 84H PCON Power Control S 87H IE0 Interrupt Enable Control 0 S A8H IPH0 Interrupt Priority Control High 0 S B7H IPL0 Interrupt Priority Contro...

Page 406: ...0 Low Byte S 8AH TH0 Timer Counter 0 High Byte S 8CH TL1 Timer Counter 1 Low Byte S 8BH TH1 Timer Counter 1 High Byte S 8DH TL2 Timer Counter 2 Low Byte S CCH TH2 Timer Counter 2 High Byte S CDH TCON...

Page 407: ...ow Byte S E9H CH PCA Timer Counter High Byte S F9H CCAP0L PCA Compare Capture Module 0 Low Byte S EAH CCAP1L PCA Compare Capture Module 1 Low Byte S EBH CCAP2L PCA Compare Capture Module 2 Low Byte S...

Page 408: ...ack pointer SPH SPL 1 3 NOTE 1 The registers in the register file are normally accessed by mnemonic Depending on its loca tion a register can be addressed as a byte word and or dword See Figure 3 7 on...

Page 409: ...ce to R11 These instructions can use byte registers Rm m 0 15 interchangeably 7 0 Accumulator Contents Bit Number Bit Mnemonic Function 7 0 ACC 7 0 Accumulator B Address F0H Reset State 0000 0000B B R...

Page 410: ...re Registers These five register pairs store the 16 bit comparison value or captured value for the corresponding compare capture modules In the PWM mode the low byte register controls the duty cycle o...

Page 411: ...high speed output pulse width modulation and watchdog timer modes 5 CAPPx Capture Mode Positive CAPPx 1 enables the capture function with capture triggered by a positive edge on pin CEXx 4 CAPNx Capt...

Page 412: ...be cleared only by software 6 CR PCA Timer Counter Run Control Bit Set and cleared by software to turn the PCA timer counter on and off 5 Reserved The value read from this bit is indeterminate Write a...

Page 413: ...L 1 disables the PCA timer counter during idle mode CIDL 0 allows the PCA timer counter to run during idle mode 6 WDTE Watchdog Timer Enable WDTE 1 enables the watchdog timer output on PCA module 4 WD...

Page 414: ...Bit Number Bit Mnemonic Function 7 0 DPH 7 0 Data Pointer High Bits 8 15 of the extended data pointer DPX DR56 DPL Address S 82H Reset State 0000 0000B Data Pointer Low DPL provides SFR access to reg...

Page 415: ...location 57 also named DPXL Location 57 is the lower byte of the upper word of the extended data pointer DPX DR56 whose lower word is the 16 bit data pointer DPTR See also DPH and DPL 7 0 DPXL Conten...

Page 416: ...0 6 Clearing this bit disables all interrupts except the TRAP interrupt which is always enabled 6 EC PCA Interrupt Enable Setting this bit enables the PCA interrupt 5 ET2 Timer 2 Overflow Interrupt E...

Page 417: ...0 4 IPH0 3 IPH0 2 IPH0 1 IPH0 0 Bit Number Bit Mnemonic Function 7 Reserved The value read from this bit is indeterminate Write a zero to this bit 6 IPH0 6 PCA Interrupt Priority Bit High 5 IPH0 5 Tim...

Page 418: ...0 6 IPL0 5 IPL0 4 IPL0 3 IPL0 2 IPL0 1 IPL0 0 Bit Number Bit Mnemonic Function 7 Reserved The value read from this bit is indeterminate Write a zero to this bit 6 IPL0 6 PCA Interrupt Priority Bit Low...

Page 419: ...e former contents of P0 are lost 7 0 P0 Contents Bit Number Bit Mnemonic Function 7 0 P0 7 0 Port 0 Register Write data to be driven onto the port 0 pins to these bits P1 Address S 90H Reset State 111...

Page 420: ...Bit Number Bit Mnemonic Function 7 0 P2 7 0 Port 2 Register Write data to be driven onto the port 2 pins to these bits P3 Address S B0H Reset State 1111 1111B Port 3 P3 is the SFR that contains data t...

Page 421: ...CON 7 are to the SM0 bit See Figure 10 2 on page 10 3 5 Reserved The value read from this bit is indeterminate Write a zero to this bit 4 POF Power Off Flag Set by hardware as VCC rises above 3 V to i...

Page 422: ...addition or a borrow into bit 3 from subtraction Otherwise it is cleared This flag is useful for BCD arithmetic see Table 5 10 on page 5 17 5 F0 Flag 0 This general purpose flag is available to the us...

Page 423: ...0 and 1 Identical to the RS1 0 bits in the PSW register 2 OV Overflow Flag Identical to the OV bit in the PSW register 1 Z Zero Flag This flag is set if the result of the last logical or arithmetic op...

Page 424: ...2 SADDR Address S A9H Reset State 0000 0000B Slave Individual Address Register SADDR contains the device s individual address for multiprocessor communication 7 0 Slave Individual Address Bit Number B...

Page 425: ...tiprocessor communication 7 0 Mask for SADDR Bit Number Bit Mnemonic Function 7 0 SADEN 7 0 SBUF Address S 99H Reset State XXXX XXXXB Serial Data Buffer Writing to SBUF loads the transmit buffer of th...

Page 426: ...ial port operating mode SM0 SM1 Mode Description Baud Rate 0 0 0 Shift register FOSC 12 0 1 1 8 bit UART Variable 1 0 2 9 bit UART FOSC 32 or FOSC 64 1 1 3 9 bit UART Variable Select by programming th...

Page 427: ...ta bit of a frame has been received Cleared by software SP Address S 81H Reset State 0000 0111B Stack Pointer SP provides SFR access to location 63 in the register file also named SP SP is the lowest...

Page 428: ...d stack pointer SPX The extended stack pointer points to the current top of stack When a byte is saved PUSHed on the stack SPX is incremented and then the byte is written to the top of stack When a by...

Page 429: ...l port modes 1 and 3 4 TCLK Transmit Clock Bit Selects timer 2 overflow pulses TCLK 1 or timer 1 overflow pulses TCLK 0 as the baud rate generator for serial port modes 1 and 3 3 EXEN2 Timer 2 Externa...

Page 430: ...k out enable bits for timer 2 7 0 T2OE DCEN Bit Number Bit Mnemonic Function 7 2 Reserved The values read from these bits are indeterminate Write zeros to these bits 1 T2OE Timer 2 Output Enable Bit I...

Page 431: ...re when the processor vectors to the interrupt routine 4 TR0 Timer 0 Run Control Bit Set cleared by software to turn timer 1 on off 3 IE1 Interrupt 1 Flag Set by hardware when an external interrupt is...

Page 432: ...ect M11 M01 0 0 Mode 0 8 bit timer counter TH1 with 5 bit prescalar TL1 0 1 Mode 1 16 bit timer counter 1 0 Mode 2 8 bit auto reload timer counter TL1 Reloaded from TH1 at overflow 1 1 Mode 3 Timer 1...

Page 433: ...Function 7 0 TH0 7 0 TL0 7 0 High byte of the timer 0 timer register Low byte of the timer 0 timer register TH1 TL1 Address TH1 S 8DH TL1 S 8BH Reset State 0000 0000B TH1 TL1 Timer Registers These reg...

Page 434: ...N Address S A7H Reset State XXXX XX00B Wait State Control Register Use this register to enable the real time wait state input signal and or the wait state output clock 7 0 RTWCE RTWE Bit Number Bit Mn...

Page 435: ...the WDTRST register clears and enables the hardware WDT The WDTRST register is a write only register Attempts to read it return FFH The WDT itself is not read or write accessible See section 8 7 Watch...

Page 436: ......

Page 437: ...Glossary...

Page 438: ......

Page 439: ...A register or storage location that forms the result of an arithmetic or logical operation addr11 An 11 bit destination address The destination can be anywhere in the same 2 Kbyte block of memory as t...

Page 440: ...51 microcontroller bit A binary digit bit operand An addressable bit in the MCS 251 architecture bit51 An addressable bit in the MCS 51 architecture byte Any 8 bit unit of data clear The term clear r...

Page 441: ...ge high to low transition a rising edge low to high transition or a rising or falling edge of an input signal as the assertion of that signal See also level triggered encryption array An array of key...

Page 442: ...es a high level logic one or a low level logic zero of an input signal as the assertion of that signal See also edge triggered LSB Least significant bit of a byte or least significant byte of a word m...

Page 443: ...8XC251SA SB SP SQ peripherals operate This is equal to six state times program memory A part of memory where instructions can be stored for fetching and execution powerdown mode The power conservation...

Page 444: ...e that is selected by a configuration bit In source mode an MCS 251 microcontroller can execute recompiled source code written for an MCS 51 microcontroller In source mode the MCS 251 microcontroller...

Page 445: ...mprises two contiguous bytes wraparound The result of interpreting an address whose hexadecimal expression uses more bits than the number of available address lines Wraparound ignores the upper addres...

Page 446: ......

Page 447: ...Index...

Page 448: ......

Page 449: ...lowing reset 11 7 idle mode 12 4 programming and verifying nonvolatile memory 14 3 ANL instruction 5 9 5 11 for bits A 23 ANL instruction 5 11 for bits A 23 Arithmetic instructions 5 8 5 9 table of A...

Page 450: ...bus cycles 13 15 programming and verifying 14 1 UCONFIG0 table 4 6 UCONFIG1 table 4 7 Control instructions 5 1 5 12 5 16 addressing modes 5 12 5 13 table of A 24 Core 2 4 SFRs 3 18 C 3 CPL instruction...

Page 451: ...13 1 External RAM example 13 26 exiting idle mode 12 5 F F0 flag 5 18 C 20 FaxBack service 1 7 1 8 Flash memory example 13 18 13 20 13 30 G Given address See Serial I O port Ground bounce 11 2 H Hard...

Page 452: ...on A 24 JMP instruction A 24 JNB instruction 5 14 A 24 JNC instruction A 24 JNE instruction A 24 JNZ instruction A 24 JSG instruction A 25 JSGE instruction A 25 JSL instruction A 24 JSLE instruction A...

Page 453: ...mode 4 15 source mode 4 15 See also Binary and source modes ORL instruction 5 9 5 11 for bits A 23 ORL instruction 5 11 for bits A 23 Oscillator 2 6 at startup 11 7 during reset 11 5 on chip 11 3 ONCE...

Page 454: ...ditional jumps 5 14 effects of instructions on flags 5 17 PSW1 A 26 Pullups 7 8 ports 1 2 3 7 6 Pulse width measurements 8 10 PUSH instruction 3 15 5 10 A 22 Q Quick pulse algorithm 14 1 R RCAP2H RCAP...

Page 455: ...0 10 baud rate generator 8 8 baud rate mode 0 10 4 10 10 baud rate modes 1 2 3 10 6 10 10 10 14 broadcast address 10 9 data frame modes 1 2 3 10 6 framing bit error detection 10 7 full duplex 10 6 giv...

Page 456: ...k out mode 8 14 interrupt 8 11 mode select 8 15 Timer counters 8 1 8 17 external input sampling 8 3 internal clock 8 3 interrupts 8 1 overview 8 1 8 3 registers 8 2 SFRs 3 19 C 4 signal descriptions 8...

Page 457: ...2 WCON 3 17 13 11 C 2 C 3 C 32 WDTRST 3 17 3 19 8 2 8 16 C 2 C 4 C 33 World Wide Web 1 7 WR 7 1 described 13 2 X XALE bit 4 13 XCH instruction 5 10 A 22 XCHD instruction 5 10 A 22 XRL instruction 5 9...

Page 458: ......

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