Intel 8XC251SA, User Manual

Page: 22 / 458

8XC251SA, SB, SP, SQ USER’S MANUAL
1-2
Chapter 7, “Input/Output Ports” — describes the four 8-bit I/O ports (ports 0–3) and discusses
their configuration for general-purpose I/O, external memory accesses (ports 0, 2), and alterna-
tive special functions.
Chapter 8, “Timer/Counters and WatchDog Timer” — describes the three on-chip tim-
er/counters and discusses their application. This chapter also provides instructions for using the
hardware watchdog timer (WDT) and describes the operation of the WDT during the idle and
powerdown modes.
Chapter 9, “Programmable Counter Array” — describes the PCA on-chip peripheral and ex-
plains how to configure it for general-purpose applications (timers and counters) and special ap-
plications (programmable WDT and pulse-width modulator).
Chapter 10, “Serial I/O Port” — describes the full-duplex serial I/O port and explains how to
program it to communicate with external peripherals. This chapter also discusses baud rate gen-
eration, framing error detection, multiprocessor communications, and automatic address recog-
nition.
Chapter 11, “Minimum Hardware Setup” — describes the basic requirements for operating
the 8XC251Sx in a system. It also discusses on-chip and external clock sources and describes de-
vice resets, including power-on reset.
Chapter 12, “Special Operating Modes” — provides an overview of the idle, powerdown, and
on-circuit emulation (ONCE) modes and describes how to enter and exit each mode. This chapter
also describes the power control (PCON) special function register and lists the status of the device
pins during the special modes and reset (Table 12-1).
Chapter 13, “External Memory Interface” —describes the external memory signals and bus
cycles and provides examples of external memory design. It provides waveform diagrams for the
bus cycles, bus cycles with wait states, and the configuration byte bus cycles. It also provides bus
cycle diagrams with AC timing symbols and definitions of the symbols.
Chapter 14, “Programming and Verifying Nonvolatile Memory” — provides instructions for
programming and verifying on-chip code memory, configuration bytes, signature bytes, lock bits
and the encryption array.
Appendix A, “Instruction Set Reference” — provides reference information for the instruction
set. It describes each instruction; defines the bits in the program status word registers (PSW,
PSW1); shows the relationships between instructions and PSW flags; and lists hexadecimal op-
codes, instruction lengths, and execution times. Chapter 5, “Programming,” includes a general
discussion of the instruction set.