Intel 8XC251SA, User Manual

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2-1
CHAPTER 2
ARCHITECTURAL OVERVIEW
The 8XC251Sx is the first member of the MCS
®
251 microcontroller family. This family of 8-bit
microcontrollers is a high-performance upgrade of the widely-used MCS 51
®
microcontrollers.
It extends features and performance while maintaining binary-code compatibility and pin com-
patibility with the 8XC51FX, so the impact on existing hardware and software is minimal. Typi-
cal control applications for the 8XC251Sx include copiers, scanners, CD ROMs, and tape drives.
It is also well suited for communications applications, such as phone terminals, business/feature
phones, and phone switching and transmission systems.
This manual covers all memory options of the 8XC251SA, SB, SP, SQ and these options are listed
in Table 2-1.
All MCS 251 microcontrollers share a set of common features:
•
24-bit linear addressing and up to 16 Mbytes of memory
•
a register-based CPU with registers accessible as bytes, words, and double words
•
a page mode for accelerating external instruction fetches
•
an instruction pipeline
•
an enriched instruction set, including 16-bit arithmetic and logic instructions
•
a 64-Kbyte extended stack space
•
a minimum instruction-execution time of two clocks (vs. 12 clocks for MCS 51 microcon-
trollers)
•
three types of wait state solutions: real-time, RD#/WR#/PSEN#, and ALE
•
binary-code compatibility with MCS 51 microcontrollers
Several benefits are derived from these features:
•
preservation of code written for MCS 51 microcontrollers
•
a significant increase in core execution speed in comparison with MCS 51 microcontrollers
at the same clock rate
•
support for larger programs and more data
•
increased efficiency for code written in C
•
dynamic bus control through real-time wait state operations