Intel 8XC251SA, User Manual

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4-1
CHAPTER 4
DEVICE CONFIGURATION
The 8XC251Sx provides user design flexibility by configuring certain operating features at de-
vice reset. These features fall into the following categories:
•
external memory interface (page mode, address bits, pre-programmed wait states and the
address range for RD#, WR#, and PSEN#)
•
source mode/binary mode opcodes
•
selection of bytes stored on the stack by an interrupt
•
mapping of the upper portion of on-chip code memory to region 00:
You can specify a 16-bit, 17-bit, or 18-bit external address bus (256 Kbyte external address
space). Wait state configurations provide pre-programmed 0, 1, 2, or 3 wait states.
This chapter provides a detailed discussion of 8XC251Sx device configuration. It describes the
configuration bytes and provides information to aid you in selecting a suitable configuration for
your application. It discusses the choices involved in configuring the external memory interface
and shows how the internal memory maps into the external memory. See 4.5, “Configuring the
External Memory Interface.” Section 4.6, “Opcode Configurations (SRC),” discusses the choice
of source mode or binary mode opcode arrangements.
4.1 CONFIGURATION OVERVIEW
The configuration of the MCS
®
251 microcontroller is established by the reset routine based on
information stored in configuration bytes. The 8XC251Sx microcontrollers store configuration
information in two configuration bytes located in code memory. Devices with no on-chip code
memory fetch configuration data from external memory. Factory programmed ROM devices use
customer provided configuration data supplied on floppy disc.
4.2 DEVICE CONFIGURATION
The 8XC251Sx reserves the top eight bytes of the memory address map (FF:FFF8H–FF:FFFFH)
for an eight-byte configuration array (Figure 4-1). The two lowest bytes of the configuration array
are assigned to the user configuration bytes UCONFIG0 (FF:FFF8H) and UCONFIG1
(FF:FFF9H). For ROM/OTPROM/EPROM devices, configuration information is stored in on-
chip non-volatile memory at these addresses. For devices without on-chip
ROM/OTPROM/EPROM, configuration information is accessed from external memory.