Intel 8XC251SA, User Manual

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8-9
TIMER/COUNTERS AND WATCHDOG TIMER
8.4.1 Mode 0 (13-bit Timer)
Mode 0 configures timer 0 as a 13-bit timer, which is set up as an 8-bit timer (TH1 register) with
a modulo-32 prescalar implemented with the lower 5 bits of the TL1 register (Figure 8-2). The
upper 3 bits of the TL1 register are ignored. Prescalar overflow increments the TH1 register.
8.4.2 Mode 1 (16-bit Timer)
Mode 1 configures timer 1 as a 16-bit timer with TH1 and TL1 connected in cascade (Figure 8-2).
The selected input increments TL1.
8.4.3 Mode 2 (8-bit Timer with Auto-reload)
Mode 2 configures timer 1 as an 8-bit timer (TL1 register) with automatic reload from the TH1
register on overflow (Figure 8-3). Overflow from TL1 sets overflow flag TF1 in the TCON reg-
ister and reloads TL1 with the contents of TH1, which is preset by software. The reload leaves
TH1 unchanged. See section 8.5.1, “Auto-load Setup Example.”
8.4.4 Mode 3 (Halt)
Placing timer 1 in mode 3 causes it to halt and hold its count. This can be used to halt timer 1
when the TR1 run control bit is not available, i.e., when timer 0 is in mode 3. See the final para-
graph of section 8.4, “Timer 1.”
8.5 TIMER 0/1 APPLICATIONS
Timer 0 and timer 1 are general purpose timers that can be used in a variety of ways. The timer
applications presented in this section are intended to demonstrate timer setup, and do not repre-
sent the only arrangement nor necessarily the best arrangement for a given task. These examples
employ timer 0, but timer 1 can be set up in the same manner using the appropriate registers.
8.5.1 Auto-load Setup Example
Timer 0 can be configured as an eight-bit timer (TL0) with automatic reload as follows:
1. Program the four low-order bits of the TMOD register (Figure 8-5) to specify: mode 2 for
timer 0, C/T0# = 0 to select F
OSC
/12 as the timer input, and GATE0 = 0 to select TR0 as
the timer run control.
2. Enter an eight-bit initial value (n
0
) in timer register TL0, so that the timer overflows after
the desired number of peripheral cycles.