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78

CHAPTER 3 INTERRUPTS

3.7.2

EI

2

OS Status Register (ISCS)

This eight-bit register indicates the update direction (increment/decrement), transfer
data format (byte/word), and transfer direction of the buffer address pointer and the I/O
register address pointer. This register also indicates whether the buffer address pointer
or I/O register address pointer is updated or fixed.

■

EI

2

OS Status Register (ISCS)

Figure 3.7-5 is a diagram of the ISCS configuration.
Be sure to write "0" in bit 7 to bit 5 of ISCS.

Figure 3.7-5 ISCS Configuration

Each bit is described below.

[bit 4] IF: Specify whether the I/O register address pointer is updated or fixed.

0: The I/O register address pointer is updated after data transfer.

1: The I/O register address pointer is not updated after data transfer.

Note:

Only increment is allowed.

[bit 3] BW: Specify the transfer data length.

0: Byte

1: Word

[bit 2] BF: Specify whether the buffer address pointer is updated or fixed.

0: The buffer address pointer is updated after data transfer.

1: The buffer address pointer is not updated after data transfer.

Note:

Only the low-order 16 bits of the buffer address pointer are updated. Only increment is allowed.

[bit 1] DIR: Specify the data transfer direction.

0: I/O --> Buffer

1: Buffer --> I/O

[bit 0] SE: Control the termination of the extended intelligent I/O service based on internal

resource requests.

0: The extended intelligent I/O service is not terminated by a internal resource request.

1: The extended intelligent I/O service is terminated by a internal resource request.

7

6

5

4

3

2

1

0

ISCS

(Undefined
when reset)

Reserved Reserved Reserved

IF

BW

BF

DIR

SE

«
...
92
93
94
95
96
...
»

Summary of Contents for F2MCTM-16LX

Page 1: ...FUJITSU SEMICONDUCTOR CONTROLLER MANUAL F2MCTM 16LX 16 BIT MICROCONTROLLER MB90360 Series HARDWARE MANUAL CM44 10136 1E ...

Page 2: ......

Page 3: ...FUJITSU LIMITED F2MCTM 16LX 16 BIT MICROCONTROLLER MB90360 Series HARDWARE MANUAL ...

Page 4: ......

Page 5: ... Series is a family member of the F2MC 16LX micro controllers CHAPTER 2 CPU This chapter explains the CPU CHAPTER 3 INTERRUPTS This chapter explains the interrupts and function and operation of the extended intelligent I O service in the MB90360 series CHAPTER 4 DELAYED INTERRUPT GENERATION MODULE This chapter explains the functions and operations of the delayed interrupt generation module CHAPTER...

Page 6: ...he functions and operation of 8 10 bit A D converter CHAPTER 19 LOW VOLTAGE DETECTION CPU OPERATING DETECTION RESET This chapter explains the function and operating the low voltage detection CPU operating detection reset This function can use only the product with T suffix of MB90360 series CHAPTER 20 LIN UART This chapter explains the functions and operation of LIN UART CHAPTER 21 CAN CONTROLLER ...

Page 7: ...210 AF120 AF110 Flash Micro computer Programmer by Yokogawa Digital Computer Corporation when the AF220 AF210 AF120 AF110 flash serial microcontroller programer from Yokogawa Digital Computer Corporation is used CHAPTER 26 ROM SECURITY FUNCTION This chapter explains the ROM security function APPENDIX The appendixes provide I O maps instructions and other information ...

Page 8: ...ein The products described in this document are designed developed and manufactured as contemplated for general use including without limitation ordinary industrial use general office use personal use and household use but are not designed developed and manufactured as contemplated 1 for use accompanying fatal risks or dangers that unless extremely high safety is secured could have a serious effec...

Page 9: ...rogram Counter PC 45 2 8 Register Bank 46 2 9 Prefix Codes 48 2 10 Interrupt Disable Instructions 51 2 11 Precautions for Use of DIV A Ri and DIVW A RWi Instructions 52 CHAPTER 3 INTERRUPTS 55 3 1 Outline of Interrupts 56 3 2 Interrupt Vector 59 3 3 Interrupt Control Registers ICR 61 3 4 Interrupt Flow 65 3 5 Hardware Interrupts 67 3 5 1 Hardware Interrupt Operation 68 3 5 2 Occurrence and Release...

Page 10: ... of an Oscillator or an External Clock to the Microcontroller 108 CHAPTER 6 CLOCK SUPERVISOR 109 6 1 Overview of Clock Supervisor 110 6 2 Block Diagram of Clock Supervisor 111 6 3 Clock Supervisor Control Register CSVCR 113 6 4 Operating Mode of Clock Supervisor 115 CHAPTER 7 RESETS 119 7 1 Resets 120 7 2 Reset Cause and Oscillation Stabilization Wait Times 123 7 3 External Reset Pin 125 7 4 Reset...

Page 11: ...Timer 192 11 7 Program Example of Timebase Timer 193 CHAPTER 12 WATCHDOG TIMER 195 12 1 Overview of Watchdog Timer 196 12 2 Configuration of Watchdog Timer 199 12 3 Watchdog Timer Registers 201 12 3 1 Watchdog timer control register WDTC 202 12 4 Explanation of Operations of Watchdog Timer Functions 204 12 5 Precautions when Using Watchdog Timer 207 12 6 Program Examples of Watchdog Timer 208 CHAP...

Page 12: ...TCH TIMER 267 15 1 Overview of Watch Timer 268 15 2 Block Diagram of Watch Timer 270 15 3 Configuration of Watch Timer 272 15 3 1 Watch Timer Control Register WTC 273 15 4 Watch Timer Interrupt 275 15 5 Explanation of Operation of Watch Timer 276 15 6 Program Example of Watch Timer 278 CHAPTER 16 8 16 BIT PPG TIMER 281 16 1 Overview of 8 16 bit PPG Timer 282 16 2 Block Diagram of 8 16 bit PPG Time...

Page 13: ... ADCR1 351 18 3 4 A D Setting Register ADSR0 ADSR1 352 18 3 5 Analog Input Enable Register ADER5 ADER6 356 18 4 Interrupt of 8 10 bit A D Converter 358 18 5 Explanation of Operation of 8 10 bit A D Converter 359 18 5 1 Single shot Conversion Mode 360 18 5 2 Continuous Conversion Mode 362 18 5 3 Pause conversion Mode 364 18 5 4 Conversion Using EI2OS Function 366 18 5 5 A D converted Data Protectio...

Page 14: ... UART in LIN communication Operation Mode 3 439 20 8 Notes on Using LIN UART 441 CHAPTER 21 CAN CONTROLLER 443 21 1 Features of CAN Controller 444 21 2 Block Diagram of CAN Controller 445 21 3 List of Overall Control Registers 446 21 4 Classifying CAN Controller Registers 452 21 4 1 Configuration of Control Status Register CSR 453 21 4 2 Function of Control Status Register CSR 454 21 4 3 Correspon...

Page 15: ...ddress Detection Control Register PACSR0 PACSR1 509 22 3 2 Detect Address Setting Registers PADR0 to PADR5 513 22 4 Explanation of Operation of Address Match Detection Function 516 22 4 1 Example of using Address Match Detection Function 517 22 5 Program Example of Address Match Detection Function 522 CHAPTER 23 ROM MIRRORING MODULE 525 23 1 Overview of ROM Mirroring Function Select Module 526 23 ...

Page 16: ...pply Used 561 25 5 Example of Minimum Connection to Flash Microcontroller Programmer Power Supplied from Programmer 563 CHAPTER 26 ROM SECURITY FUNCTION 565 26 1 Overview of ROM Security Function 566 APPENDIX 567 APPENDIX A I O Maps 568 APPENDIX B Instructions 576 B 1 Instruction Types 577 B 2 Addressing 578 B 3 Direct Addressing 580 B 4 Indirect Addressing 586 B 5 Execution Cycle Count 593 B 6 Ef...

Page 17: ...360 Series is a family member of the F2 MC 16LX micro controllers 1 1 Overview of MB90360 1 2 Block Diagram of MB90360 series 1 3 Package Dimensions 1 4 Pin Assignment 1 5 Pin Functions 1 6 Input Output Circuits 1 7 Handling Device ...

Page 18: ...lied PLL clock Clock supervisor monitors main clock or subclock independently Subclock mode Clock source selectable from external oscillator or internal CR oscillator 16 MB CPU memory space Internal 24 bit addressing Instruction system optimized for controllers Various data types bit byte word long word 23 types of addressing modes Enhanced signed instructions of multiplication division and RETI H...

Page 19: ...ubclock pin X0A X1A Yes external oscillator used products without S suffix No subclock mode is used with internal CR oscillation product with S suffix Timers Timebase timer watch timer product without S suffix watchdog timer 1 channel 8 16 bit PPG timer 8 bits 4 channels or 16 bits 2 channels 16 bit reload timer 2 channels 16 bit I O timer 16 bit free run timer 1 channel FRT0 ICU0 1 2 3 16 bit inp...

Page 20: ... voltage CPU operation detection reset function product with T suffix Detects low voltage 4 0 V 0 3 V and reset automatically Automatic reset when program runs away and counter is not cleared within internal time approx 262 ms 4 MHz external Clock supervisor MB90x367x only Changeable port input voltage level Automotive input level CMOS Schmitt input level initial value in single chip mode is Autom...

Page 21: ...No Yes No Yes No Package LQFP 48 PGA 299 Power supply for emulator Yes Corresponding EVA product name MB90V340A 102 MB90V340A 101 It is setting of Jumper switch TOOL VCC when Emulator MB2147 01 is used Please refer to Emulator hard ware manual Features MB90F362 MB90F362T MB90F362S MB90F362TS CPU F2 MC 16LX CPU System clock pin PLL clock multiplier 1 2 3 4 6 1 2 when PLL stops Minimum instruction e...

Page 22: ...Yes No Package LQFP 48 PGA 299 Power supply for emulator Yes Corresponding EVA product name MB90V340A 104 MB90V340A 103 It is setting of Jumper switch TOOL VCC when Emulator MB2147 01 is used Please refer to Emulator hard ware manual Features MB90F367 MB90F367T MB90F367S MB90F367TS CPU F2 MC 16LX CPU System clock pin PLL clock multiplier 1 2 3 4 6 1 2 when PLL stops Minimum instruction execution t...

Page 23: ...rresponds to ICU 4 5 6 7 OCU 4 5 6 7 Signal an interrupt when overflowing Supports Timer Clear when a match with Output Compare Channel 0 4 Operation clock freq fsys 21 fsys 22 fsys 23 fsys 24 fsys 25 fsys 26 fsys 27 fsys System clock freq 16 bit input capture 4 channels 8 channels Maintains I O timer value by pin input rising edge falling edge or both edges and generates interrupt 8 16 bit PPG 2 ...

Page 24: ... general purpose I O CMOS output 34 ports product without S suffix 36 ports product with S suffix Input level setting Port2 Port4 Port6 Port8 selectable from CMOS Automotive level Supports general purpose I O CMOS output 80 ports product without S suffix 82 ports product with S suffix Input level setting Port 0 to Port 3 selectable from CMOS Automotive TTL level Port 4 to Port A selectable from CM...

Page 25: ...o TIN0 TOT3 to TOT0 AD15 to AD00 A23 to A16 ALE RD WRL WRH HRQ HAK RDY CLK X0 X1 X0A X1A RST SOT4 to SOT0 SCK4 to SCK0 SIN4 to SIN0 AN23 to AN0 AVRH AVRL ADTG Clock control Prescaler 5 channels 8 10 bit A D converter 24 channels 10 bit D A converter 2 channels 8 16 bit PPG 16 channels 16 bit I O timer 0 Input capture 8 channels Output compare 8 channels 16 bit I O timer 1 CAN controller 3 channels...

Page 26: ... AN0 AVRH AVRL ADTG AD15 to AD00 A23 to A16 ALE RD WRL WRH HRQ HAK RDY CLK Clock control Prescaler 5 channels 8 10 bit A D converter 24 channels 10 bit D A converter 2 channels 8 16 bit PPG 16 channels Internal data bus 16 bit I O timer 0 Input capture 8 channels Output compare 8 channels 16 bit I O timer 1 CAN controller 3 channels 16 bit reload timer 4 channels External bus DTP external interrup...

Page 27: ...mer 2 channels DTP external interrupt SOT0 SOT1 SCK0 SCK1 SIN0 SIN1 PPGF E PPGD C PPGC D PPGE F IN0 to IN3 FRCK0 RX1 TX1 TIN2 TIN3 TOT2 TOT3 INT8 INT9R INT10 INT11 INT12R INT13 INT14R INT15R CPU operation detection 2 Low voltage detection 2 CR oscillation circuit Internal data bus AVSS AVCC Prescaler 2 channels 8 10 bit A D converter 16 channels X0 X1 X0A X1A 1 RST AVR ADTG 1 Product without S suf...

Page 28: ... MAX Weight 0 17 g Code Reference P LFQFP48 7 7 0 50 48 pin plastic LQFP FPT 48P M26 FPT 48P M26 C 2003 FUJITSU LIMITED F48040S c 2 2 24 13 36 25 48 37 INDEX SQ 9 00 0 20 354 008 SQ 0 145 0 055 006 002 0 08 003 A 0 8 059 004 008 0 10 0 20 1 50 0 60 0 15 024 006 0 10 0 10 004 004 Stand off 0 25 010 Details of A part 1 12 0 08 003 M 008 002 0 20 0 05 0 50 020 LEAD No Mounting height 276 004 016 0 10...

Page 29: ...Vcc Vss C X0A P40 1 X1A P41 1 P82 SIN0 INT14R TIN2 P50 AN8 AVcc TOP VIEW P44 FRCK0 P80 ADTG INT12R P51 AN9 X0 X1 P67 AN7 PPGE F AVR P60 AN0 P61 AN1 P62 AN2 P63 AN3 P64 AN4 P65 AN5 P27 IN3 P26 IN2 P25 IN1 P24 IN0 P23 PPGF E P22 PPGD C P21 P20 MD2 MD1 MD0 P52 AN10 P53 AN11 TIN3 P54 AN12 TOT3 INT8 P55 AN13 INT10 P56 AN14 INT11 P57 AN15 INT13 P84 SCK0 INT15R P83 SOT0 TOT2 P42 RX1 INT9R P43 TX1 P86 SOT...

Page 30: ... External interrupt request input pin for INT12R 12 to 14 P50 to P52 H General purpose I O port I O circuit type of P50 is different from that of MB90V340A AN8 to AN10 Analog input pin for A D converter 15 P53 H General purpose I O port AN11 Analog input pin for A D converter TIN3 Event input pin for reload timer 3 16 P54 H General purpose I O port AN12 Analog input pin for A D converter TOT3 Outp...

Page 31: ...ion becomes valid at shingle chip mode High current output port 37 P85 K General purpose I O port SIN1 Serial data input pin for UART1 38 P87 F General purpose I O port SCK1 Clock I O pin for UART1 39 P86 F General purpose I O port SOT1 Serial data output pin for UART1 40 P43 F General purpose I O port TX1 TX output pin for CAN1 interface 41 P42 F General purpose I O port RX1 RX input pin for CAN1...

Page 32: ...r 0 clock pin 46 47 P40 P41 F General purpose I O port product with S suffix and MB90V340A 101 103 only X1A X0A B Oscillation input pin for subclock product without S suffix and MB90V340A 102 104 only 48 AVSS I VSS power input pin for analog circuit Table 1 5 1 Pin Description 3 3 Pin number Pin name Circuit type Functional description ...

Page 33: ...dback resistor approx 1 MΩ B Oscillation circuit Low speed oscillation feedback resistor approx 10 MΩ C Mask ROM device CMOS hysteresis input pin Flash device CMOS input D Mask ROM device CMOS hysteresis input pin Pull down resistor value approx 50 kΩ Flash device CMOS input pin No Pull down X1 X0 Xout Standby control signal X1A X0A Xout Standby control signal R Hysteresis input R Hysteresis input...

Page 34: ... output IOL 4 mA IOH 4 mA CMOS hysteresis inputs with the standby time input shutdown function Automotive input with the standby time input shutdown function Programmable pull up resistor approx 50 kΩ Table 1 6 1 I O Circuit Types 2 4 Type Circuit Remarks R Hysteresis input Pull up resistor Pout Nout R Hysteresis input Automotive input Standby control for input shutdown Pout Nout R Pull up control...

Page 35: ...0 mA IOH 14 mA CMOS hysteresis inputs with the standby time input shutdown function Automotive inputs with the standby time input shutdown function Programmable pull up resistor approx 50 kΩ Table 1 6 1 I O Circuit Types 3 4 Type Circuit Remarks Pout Nout R Hysteresis input Automotive input Standby control for input shutdown Analog input Pout Nout R Hysteresis input Automotive input High current o...

Page 36: ...ysteresis inputs with the standby time input shutdown function Automotive hysteresis inputs with the standby time input shutdown function Table 1 6 1 I O Circuit Types 4 4 Type Circuit Remarks Pout Nout R CMOS input Automotive input Standby control for input shutdown ...

Page 37: ...r supply current drastically causing thermal damage to the device When used note that maximum rated voltage is not exceeded For the same reason also be careful not to let the analog power supply voltage AVCC AVR exceed the digital power supply voltage Treatment of unused pins Leaving unused input pins open may result in misbehavior or latch up and possible permanent damage of the device Therefore ...

Page 38: ...however cannot be guaranteed Power supply pins VCC VSS If there are multiple VCC and VSS pins from the point of view of device design pins to be of the same potential are connected the inside of the device to prevent such malfunctioning as latch up To reduce unnecessary radiation prevent malfunctioning of the strobe signal due to the rise of ground level and to keep the recommended DC characterist...

Page 39: ...tion circuit not cross the lines of other circuits It is highly recommended to provide a printed circuit board art work surrounding X0 and X1 pins with a ground area for stabilizing the operation Turning on Sequence of Power Supply to A D Converter and Analog Inputs Make sure to turn on the A D converter power supply AVCC AVR and analog inputs AN0 to AN15 after turning on the digital power supply ...

Page 40: ...he transient fluctuation rate becomes 0 1 V ms or less in instantaneous fluctuation for power supply switching Note on using CAN Function The MB90360 series does not contain the clock modulation function So at using CAN the DIRECT bit of the CAN direct mode register CDMR must be set 1 See Table 1 7 1 If the DIRECT bit is not set correctly the device does not operate normally Note For details on th...

Page 41: ...Access to the registers which do not exist in the MB90360 series As for the registers and bits which exist in MB90340 series but not in the MB90360 series do not access them or ensure that the initial value is set Setting any other value than the initial value may cause an abnormal operation in emulation using MB90V340 Setting of the external interrupt factor select register EISSR The MB90360 seri...

Page 42: ...26 CHAPTER 1 OVERVIEW ...

Page 43: ...PU 2 2 Memory Space 2 3 Memory Map 2 4 Linear Addressing 2 5 Bank Addressing Types 2 6 Multi byte Data in Memory Space 2 7 Registers 2 8 Register Bank 2 9 Prefix Codes 2 10 Interrupt Disable Instructions 2 11 Precautions for Use of DIV A Ri and DIVW A RWi Instructions ...

Page 44: ...n reinforced by adding instructions compatible with high level languages expanding addressing modes reinforcing multiplication and division instructions and enhancing bit processing The features of the F2 MC 16LX CPU are explained below Minimum instruction execution time 42 ns at 4 MHz oscillation 6 times clock multiplication Maximum memory space 16M bytes accessed in linear or bank mode Instructi...

Page 45: ...0B0H 000020H 000000H 007900H FF0000H 1 001900H 2 008000H F2 MC 16LX device F2 MC 16LX CPU EI2 OS EI 2 OS descriptor area Programs Peripheral circuit Peripheral circuit Data Internal data bus Interrupt General purpose ports Vector table area Peripheral function control register area Peripheral function control register area Interrupt control register area Peripheral function control register area I...

Page 46: ... RAM area it can be used as ordinary RAM When this area is used as a general purpose register general purpose register addressing enables high speed access with short instructions Extended intelligent I O service EI2 OS descriptor area address 000100H to 00017FH This area retains the transfer modes I O addresses transfer count and buffer addresses Since this area is allocated to a part of the RAM ...

Page 47: ...lowing 2 addressing modes Linear addressing An entire 24 bit address is specified by an instruction Bank addressing The eight high order bits of an address are specified by an appropriate bank register and the remaining 16 low order bits are specified by an instruction ...

Page 48: ...e 00 bank The image between FF8000H and FFFFFFH is visible in bank 00 whereas the data between FF0000H and FF7FFFH is only visible in bank FF Figure 2 3 1 Memory Map FFFFFFH FF0000H FEFFFFH FE0000H FDFFFFH FD0000H FCFFFFH FC0000H FBFFFFH FB0000H FAFFFFH FA0000H F9FFFFH 0000EFH 000000H F90000H F8FFFFH F80000H 00FFFFH 007FFFH 007900H 0078FFH 000100H 008000H MB90V340A 101 102 103 104 FFFFFFH FF0000H ...

Page 49: ...cation Figure 2 4 1 shows an example of 24 bit operand specification Figure 2 4 2 shows an example of 32 bit register indirect specification Figure 2 4 1 Example of Linear Method 24 bit operand specification Figure 2 4 2 Example of Linear Method 32 bit register indirect specification 17 12 452D 3456 17452DH 123456H JMPP 123456H JMPP 123456H Old program counter Program bank Program bank New program...

Page 50: ... specified by the USB or SSB is called a stack SP space The SP space is accessed when a stack access occurs during a push pop instruction or interrupt register saving The S flag in the condition code register determines the stack space to be accessed Additional bank register ADB The 64K bytes bank specified by the ADB is called an additional AD space The AD space for example contains data that can...

Page 51: ...RW1 RW4 or RW5 A addr16 and dir Stack space Addressing mode using PUSHW POPW RW3 or RW7 Additional space Addressing mode using RW2 or RW6 FFH B3H 92H 68H 4BH FFFFFFH FF0000H B3FFFFH 920000H 68FFFFH 680000H 4BFFFFH 4B0000H 000000H 92FFFFH B30000H PCB Program bank register ADB Additional bank register USB User stack bank register DTB Data bank register SSB System stack bank register Program space Ad...

Page 52: ...ory The low order eight bits of a data item are stored at address n then address n 1 address n 2 address n 3 etc Figure 2 6 1 Sample Allocation of Multi byte Data in Memory Accessing Multi byte Data Fundamentally accesses are made within a bank For an instruction accessing a multi byte data item address FFFFH is followed by address 0000H of the same bank Figure 2 6 2 is an example of an instructio...

Page 53: ...g special registers Accumulator A AH AL Two 16 bit accumulators Can be used as a single 32 bit accumulator User stack pointer USP 16 bit pointer indicating the user stack area System stack pointer SSP 16 bit pointer indicating the system stack area Processor status PS 16 bit register indicating the system status Program counter PC 16 bit register holding the address of the program Program bank reg...

Page 54: ...P User stack pointer SSP System stack pointer PS Processor status PC Program counter DPR Direct page register PCB Program bank register DTB Data bank register USB User bank register SSB System stack bank register ADB Additional data bank register 8 bits 16 bits 32 bits ...

Page 55: ...R7 8 bit general purpose register RW0 to RW7 16 bit general purpose register RL0 to RL3 32 bit general purpose register Figure 2 7 2 General purpose Registers The relationship between the high order and low order bytes of a byte or word register is expressed as follows RW i 4 R i 2 1 256 R i 2 i 0 to 3 The relationship between the high order and low order bytes of RLi and RW can be expressed as fo...

Page 56: ...ation function and operation between AL and AH help improve processing efficiency When a byte or shorter data item is transferred to AL the data is sign extended or zero extended and stored as a 16 bit data item in AL The data in AL can be handled either as word or byte long When a byte processing arithmetic operation instruction is executed on AL the high order eight bits of AL before operation a...

Page 57: ...e while USP is used for stack processing outside an interrupt routine If the stack space is not divided use only the SSP During stack processing the high order eight bits of an address are indicated by SSB for SSP or USB for USP USP and SSP are not initialized by a reset Instead they hold undefined values Figure 2 7 5 Stack Manipulation Instruction and Stack Pointer Note Specify an even numbered a...

Page 58: ...uction execution or interrupt occurrences Figure 2 7 6 Processor Status PS Structure Condition Code Register CCR Figure 2 7 7 is a diagram of condition code register CCR configuration Figure 2 7 7 Condition Code Register CCR Configuration I Interrupt enable flag Interrupt requests other than software interrupts are enabled when the I flag is 1 and are masked when the I flag is 0 The I flag is clea...

Page 59: ...eration execution and is otherwise cleared Register Bank Pointer RP The RP register indicates the relationship between the general purpose registers of the F2 MC 16LX and the internal RAM addresses Specifically the RP register indicates the first memory address of the currently used register bank in the following conversion expression 00180H RP 10H see Figure 2 7 8 The RP register consists of five...

Page 60: ...set in ILM Thus an interrupt of the same or lower level cannot be accepted subsequently ILM is initialized to all zeroes by a reset An instruction may transfer an eight bit immediate value to the ILM register but only the low order three bits of that data are used Figure 2 7 9 Interrupt Level Mask Register ILM ILM2 ILM1 ILM0 ILM Initial value 0 0 0 Table 2 7 1 Levels Indicated by the Interrupt Lev...

Page 61: ...e high order eight bits of the address are indicated by the PCB The PC register is updated by a conditional branch instruction subroutine call instruction interrupt or reset The PC register can also be used as a base pointer for operand access Program Counter PC Figure 2 7 10 shows the program counter Figure 2 7 10 Program Counter PCB PC FEH ABCDH FEABCDH Next instruction to be executed ...

Page 62: ...ea the register bank values are not initialized by a reset The status before a reset is maintained When the power is turned on however the register bank will have an undefined value Direct page register DPR Initial value 01H DPR specifies addr8 to addr15 of the instruction operands in direct addressing mode as shown in Figure Table 2 8 1 Register Functions R0 to R7 Used as operands of instructions...

Page 63: ...Each bank register indicates the memory bank where the PC DT SP user SP system or AD space is allocated All bank registers are one byte long PCB is initialized to 00H by a reset Bank registers other than PCB can be read or written to PCB can be read but cannot be written to PCB is updated when the JMPP CALLP RETP RETIQ or RETF instruction branching to the entire 16M bytes space is executed or when...

Page 64: ...W SCEQ SCWEQ FILS FILSW The bank register specified by an operand is used regardless of the prefix Stack manipulation instructions PUSHW POPW SSB or USB is used according to the S flag regardless of the prefix I O access instructions MOVA io MOVio A MOVXA io MOVWA io MOVWio A MOVio imm8 MOVWio imm16 MOVBA io bp MOVBio bp A SETBio bp CLRBio bp BBCio bp rel BBSio bp rel WBTC WBTS The IO space of the...

Page 65: ...CR imm8 OR CCR imm8 POPW PS The instruction is executed normally but the prefix affects the next instruction MOV ILM imm8 The instruction is executed normally but the prefix affects the next instruction Flag Change Disable Prefix NCC To disable flag changes use the flag change disable prefix code NCC Placing NCC before an instruction that suppresses unnecessary flag change disables flag changes as...

Page 66: ...50 CHAPTER 2 CPU MOV ILM imm8 The instruction is executed normally but the prefix affects the next instruction ...

Page 67: ...e is placed before an interrupt disable instruction the prefix code affects the first instruction after the code other than the interrupt disable instruction For details see Figure 2 10 2 Figure 2 10 2 Interrupt Disable Instructions and Prefix Codes Consecutive prefix codes When competitive prefix codes are placed consecutively the latter becomes valid In the figure below competitive prefix codes ...

Page 68: ...ess that stores the remainder DIVA R0 DTB DTB Upper 8 bits 0180H RP 10H 8H Lower 16 bits DIVA R1 DTB Upper 8 bits 0180H RP 10H 9H Lower 16 bits DIVA R4 DTB Upper 8 bits 0180H RP 10H CH Lower 16 bits DIVA R5 DTB Upper 8 bits 0180H RP 10H DH Lower 16 bits DIVWA RW0 DTB Upper 8 bits 0180H RP 10H 0H Lower 16 bits DIVWA RW1 DTB Upper 8 bits 0180H RP 10H 2H Lower 16 bits DIVWA RW4 DTB Upper 8 bits 0180H...

Page 69: ... A RWi Instructions without Precautions To enable users to develop programs without having to take precautions for using the DIV A Ri and DIVW A RWi instructions special compilers and assemblers are available The special compiler does not generate the instructions in Table 2 11 1 The special assemblers have a function that replaces the instructions in Table 2 11 1 with equivalent instruction strin...

Page 70: ...54 CHAPTER 2 CPU ...

Page 71: ...vice in the MB90360 series 3 1 Outline of Interrupts 3 2 Interrupt Vector 3 3 Interrupt Control Registers ICR 3 4 Interrupt Flow 3 5 Hardware Interrupts 3 6 Software Interrupts 3 7 Extended Intelligent I O Service EI2 OS 3 8 Operation Flow of and Procedure for Using the Extended Intelligent I O Service EI2 OS 3 9 Exceptions ...

Page 72: ...herefore an internal resource must have an interrupt request flag and interrupt enable flag to issue a hardware interrupt request Specifying an interrupt level An interrupt level can be specified for the hardware interrupt To specify an interrupt level use the level setting bits IL0 IL1 and IL2 of the interrupt controller Masking a hardware interrupt request A hardware interrupt request can be mas...

Page 73: ...peration To activate the extended intelligent I O service function from an internal resource the interrupt control register ICR of the interrupt controller must have an extended intelligent I O service enable flag ISE The extended intelligent I O service is started when an interrupt request occurs with 1 specified in the ISE flag To generate a normal interrupt using a hardware interrupt request se...

Page 74: ...n an exception is detected between instructions ordinary processing is suspended and exception processing is performed In general exception processing occurs as a result of an unexpected operation Therefore use exception processing for debugging programs or for activating recovery software in an emergency ...

Page 75: ... FFFFDCH FFFFDDH FFFFDEH FFFFDFH INT 9 INT9 instruction FFFFD8H FFFFD9H FFFFDAH Unused INT 10 Exception processing FFFFD4H FFFFD5H FFFFD6H Unused INT 11 Reserved ICR00 0000B0H FFFFD0H FFFFD1H FFFFD2H Unused INT 12 Reserved FFFFCCH FFFFCDH FFFFCEH Unused INT 13 CAN1 reception ICR01 0000B1H FFFFC8H FFFFC9H FFFFCAH Unused INT 14 CAN1 transmission node status FFFFC4H FFFFC5H FFFFC6H Unused INT 15 Rese...

Page 76: ...F72H Unused INT 36 UART 0 transmission FFFF6CH FFFF6DH FFFF6EH Unused INT 37 UART 1 reception ICR13 0000BDH FFFF68H FFFF69H FFFF6AH Unused INT 38 UART 1 transmission FFFF64H FFFF65H FFFF66H Unused INT 39 Reserved ICR14 0000BEH FFFF60H FFFF61H FFFF62H Unused INT 40 Reserved FFFF5CH FFFF5DH FFFF5EH Unused INT 41 Flash memory ICR15 0000BFH FFFF58H FFFF59H FFFF5AH Unused INT 42 Delayed interrupt gener...

Page 77: ... bit configuration of an interrupt control register Figure 3 3 1 Interrupt Control Register ICR Note ICS3 to ICS0 are valid only when EI2 OS is activated Set 1 in ISE to activate EI2 OS and set 0 in ISE not to activate it When EI2 OS is not to be activated any value can be set in ICS3 to ICS0 bit 10 to bit 8 bit 2 to bit 0 IL0 IL1 and IL2 interrupt level setting bits These bits are readable and wr...

Page 78: ... activated when 0 is set in the ISE bit Upon completion of EI2 OS the ISE bit is cleared to a zero If the corresponding peripheral does not have the EI2 OS function the ISE bit must be set to 0 on the software side Upon a reset the ISE bit is initialized to 0 Table 3 3 1 Interrupt Level Setting Bits and Interrupt Levels ILM2 ILM1 ILM0 Level 0 0 0 0 strongest 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 5...

Page 79: ... initialized to 0000B by a reset Table 3 3 2 describes the correspondence between the ICS bits channel numbers and descriptor addresses Table 3 3 2 ICS Bits Channel Numbers and Descriptor Address ICS3 ICS2 ICS1 ICS0 Selected channel Descriptor address 0 0 0 0 0 000100H 0 0 0 1 1 000108H 0 0 1 0 2 000110H 0 0 1 1 3 000118H 0 1 0 0 4 000120H 0 1 0 1 5 000128H 0 1 1 0 6 000130H 0 1 1 1 7 000138H 1 0 ...

Page 80: ...e bits indicate the end condition of EI2 OS These bits are initialized to 00 upon a reset Table 3 3 3 shows the relationship between the S bits and the end conditions Table 3 3 3 S Bits and End Conditions S1 S0 End conditions 0 0 EI2 OS running or not activated 0 1 Stop status by count end 1 0 Reserved 1 1 Stop status by request from internal resource ...

Page 81: ...ion of string instruction repetition Updating PC Saving PS PC PCB DTB DPR and A into the stack of SSP and setting ILM IL Saving PS PC PCB DTB ADB DPR and A into the stack of SSP and setting I O and ILM IL S 1 Fetching the interrupt vector Executing the extended intelligent I O service I Flag in CCR ILM CPU register level IF Internal resource interrupt request IE Internal resource interrupt enable ...

Page 82: ...66 CHAPTER 3 INTERRUPTS Figure 3 4 2 Register Saving during Interrupt Processing L H MSB LSB AH PS PC AL DPR DPB ADB PCB Word 16 bits SSP SSP value before interrupt SSP SSP value after interrupt ...

Page 83: ...ranches to the processing indicated by that value Structure of Hardware Interrupt Hardware interrupts are handled by the following 3 sections Internal resources Interrupt enable and request bits Used to control interrupt requests from resources Interrupt controller ICR Assigns interrupt levels and determines the priority levels of simultaneously requested interrupts CPU I and ILM Used to compare t...

Page 84: ...ts are at the same level the interrupt controller selects the request with the lowest interrupt number The relationship between the interrupt requests and ICRs is determined by the hardware The CPU compares the received interrupt level IL and the ILM in the PS register If the interrupt level is smaller than the ILM value and the I bit of the PS register is set to 1 the CPU activates the interrupt ...

Page 85: ...res the interrupt level requested by the interrupt controller with the ILM bit of the processor status register 5 If the comparison shows that the requested level is higher than the current interrupt processing level the I flag value of the same processor status register is checked 6 If the check in step 5 shows that the I flag indicates interrupt enable status the requested level is written to th...

Page 86: ...ycle count compensation value Interrupt start 24 6 Table 3 3 2 machine cycles Interrupt return 15 6 Table 3 3 2 machine cycles RETI instruction Table 3 5 1 Compensation Values for Interrupt Processing Cycle Count Address indicated by stack pointer Cycle count compensation value Internal area even number address 0 Internal area add number address 2 ...

Page 87: ...cuting instruction is completed After processing of the high level interrupt is completed the original interrupt processing is resumed An interrupt of the same or lower level may be generated while another interrupt is being processed If this happens the new interrupt request is suspended until the current interrupt processing is completed unless the ILM value or I flag is changed by an instructio...

Page 88: ...equests Structure of Software Interrupts Software interrupts are handled within the CPU CPU Microcode Interrupt processing step List of Interrupt Vectors Table D 1 Interrupt Vectors in APPENDIX D lists the interrupt vectors of the MB90360 series Software interrupts share the same interrupt vector area with hardware interrupts For example interrupt request number INT 12 is used for external interru...

Page 89: ...nstruction vector area overlaps the table of the INT vct8 instruction When designing software ensure that the CALLV instruction does not use the same address as that of the vct8 instruction Table D 2 Interrupt Causes Interrupt Vectors and Interrupt Control Registers in APPENDIX D shows the relationship of interrupt cause interrupt vector and interrupt control register in the MB90360 series RAM IR ...

Page 90: ...he transfer speed Transfer can be terminated from I O preventing unnecessary data from being transferred The buffer address may either be incremented or left unupdated The I O register address may either be incremented or left unupdated buffer address is update At the end of EI2 OS processing automatically branches to an interrupt processing routine after the end condition is set Thus the user can...

Page 91: ...oller ICR Assigns interrupt levels determines the priority levels of simultaneously requested interrupts and selects the EI2 OS operation CPU I and ILM Used to compare the requested and current interrupt levels and to identify the interrupt enable status Microcode EI2 OS processing step RAM Descriptor Describes the EI2 OS transfer information by by BAP by IOA ISD by ICS CPU Memory space I O regist...

Page 92: ...orresponding to the number of data items transferred This counter is decremented by one before data transfer EI2 OS is terminated when this counter reaches 0 Figure 3 7 3 is a diagram of the data counter configuration Figure 3 7 3 Data Counter Configuration High order 8 bits of data counter DCTH Low order 8 bits of data counter DCTL High order 8 bits of I O address pointer IOAH Low order 8 bits of...

Page 93: ...configuration Figure 3 7 4 I O Register Address Pointer Configuration Buffer Address Pointer BAP This 24 bit register holds the address used for the next EI2 OS transfer BAP exists for each EI2 OS channel Therefore each EI2 OS channel can be used for transfer with anywhere in the 16M bytes space If the BF bit of ISCS is set to 0 update enabled only the low order 16 bits of BAP changes and BAPH doe...

Page 94: ...sfer 1 The I O register address pointer is not updated after data transfer Note Only increment is allowed bit 3 BW Specify the transfer data length 0 Byte 1 Word bit 2 BF Specify whether the buffer address pointer is updated or fixed 0 The buffer address pointer is updated after data transfer 1 The buffer address pointer is not updated after data transfer Note Only the low order 16 bits of the buf...

Page 95: ...Reading ISD ISCS Interrupt sequence End request from resource Data indicated by IOA Data transfer Memory indicated by BAP Data indicated by BAP Data transfer Memory indicated by IOA Update value depends on BW Update value depends on BW Updating IOA Updating BAP Decrementing DCT Setting S1 and S0 to 00 Clearing resource interrupt request CPU operation return Setting S1 and S0 to 01 Clearing ISE to ...

Page 96: ...ted Table 3 8 1 Table 3 8 2 21 6 Table 3 5 1 machine cycles Processing by EI2OS Processing by CPU EI2OS initialization JOB execution Interrupt request Normal termination Data transfer Setting of extended intelligent I O service Switching channels Processing data in buffer AND ISE 1 Count out or interrupt generation by end request from resource Table 3 8 1 Execution Time when the EI2 OS Continues I...

Page 97: ...er Internal access B E 0 2 O 2 4 B Byte data transfer E Even address word transfer O Odd address word transfer Table 3 8 3 Interrupt Handling Time Address pointed to by the stack pointer Compensation value cycle External 8 bits 4 External even numbered address 1 External odd numbered address 4 Internal even numbered address 0 Internal odd numbered address 2 ...

Page 98: ...ry software Exception Due to Execution of an Undefined Instruction The F2 MC 16LX handles all codes that are not defined in the instruction map as undefined instructions When an undefined instruction is executed processing equivalent to the INT 10 software interrupt instruction is performed Specifically the AL AH DPR DTB ADB PCB PC and PS values are saved into the system stack and processing branc...

Page 99: ...verview of Delayed Interrupt Generation Module 4 2 Block Diagram of Delayed Interrupt Generation Module 4 3 Configuration of Delayed Interrupt Generation Module 4 4 Explanation of Operation of Delayed Interrupt Generation Module 4 5 Precautions when Using Delayed Interrupt Generation Module 4 6 Program Example of Delayed Interrupt Generation Module ...

Page 100: ...s the overview of the delayed interrupt generation module Table 4 1 1 Overview of Delayed Interrupt Generation Module Function and control Interrupt factor An interrupt request is generated by setting the R0 bit in the delayed interrupt request generate cancel register to 1 DIRR R0 1 An interrupt request is cancelled by setting the R0 bit in the delayed interrupt request generate cancel register t...

Page 101: ...ration Module Interrupt request latch This latch keeps the settings delayed interrupt request generation or cancellation of the delayed interrupt request generate cancel register DIRR Delayed interrupt request generate cancel register DIRR This register generates or cancels a delayed interrupt request Interrupt Number The interrupt number used in the delayed interrupt generation module is as follo...

Page 102: ...ection lists registers and reset values in the delayed interrupt generation module List of Registers and Reset Values Figure 4 3 1 List of Registers and Reset Values in Delayed Interrupt Generation Module Undefined Delayed interrupt request generate cancel register DIRR Address 00009FH bit 15 14 13 12 11 10 9 8 0 ...

Page 103: ...Reset value 00009FH R0 XXXXXXX0B R W Undefined R W Read Write R W Reset value bit8 R0 Delayed interrupt request generate bit 0 Release of delay interrupt request 1 Generation of delay interrupt request Table 4 3 1 Functions of Delayed Interrupt Request Generate Cancel Register DIRR Bit name Function bit8 R0 Delayed interrupt request generate bit This bit generates or cancels a delayed interrupt re...

Page 104: ... the interrupt request latch is set to 1 and an interrupt request is generated to the interrupt controller An interrupt request is generated to the CPU when the interrupt controller prioritizes the interrupt request over other requests When the interrupt level mask bit of the condition code register CCR ILM is compared to the interrupt request level ICR IL and the interrupt request level is higher...

Page 105: ...pt generation module Precautions when Using Delayed Interrupt Generation Module The interrupt processing is restarted at return from interrupt processing without setting the R0 bit in the delayed interrupt request generate cancel register DIRR to 0 within the interrupt processing routine Unlike software interrupts interrupts in the delayed interrupt generation module are delayed ...

Page 106: ...layed interrupt factor generate cancel register DIRR_R0 EQU DIRR 0 Delay interrupt request generating bit Main program CODE CSEG START Stack pointer SP already initialized AND CCR 0BFH Interrupt disabled MOV I ICR15 00H Interrupt level 0 strong MOV ILM 07H Setting ILM in PS to level 7 OR CCR 40H Interrupt enabled SETB I DIRR_R0 Delay interrupt request generating LOOP MOV A 00H No limit loop MOV A ...

Page 107: ...ocontrollers 5 1 Clocks 5 2 Block Diagram of the Clock Generation Block 5 3 Clock Selection Register CKSCR 5 4 PLL Subclock Control Register PSCCR 5 5 Clock Mode 5 6 Oscillation Stabilization Wait Interval 5 7 Connection of an Oscillator or an External Clock to the Microcontroller ...

Page 108: ... of the oscillation clock frequency The clock generation block controls the oscillation stabilization wait interval and PLL clock multiplication as well as internal clock operation by changing the clock with a clock selector Oscillation clock HCLK The oscillation clock is generated either by connecting the oscillator to high speed oscillator pins X0 X1 or by the input of an external clock Main clo...

Page 109: ... When an external clock source is used its frequency can be between 3 MHz and 24 MHz The highest operating frequency for the CPU and peripheral resource is 24 MHz However normal operation is not guaranteed if a multiplication ratio resulting in a higher frequency than 24 MHz is specified Therefore when 24 MHz external clock is inputted 1 can be specified for the PLL clock multiplication ratio The ...

Page 110: ...mebase timer Clock selector 8 16 bit PPG timer C to F 16 bit reload timer 2 3 CAN1 Oscillation stabilization wait control Watchdog timer Clock generator Pin Pin X1 X0 X1A X0A HCLK oscillation clock SCLK sub clock Pin TIN2 TIN3 Clock control block Peripheral function HCLK Oscillation clock MCLK Main clock PCLK PLL clock SCLK Sub clock f Machine clock fc CAN0 to CAN2 clock 2 divided 4 2 divided CPU ...

Page 111: ...clock oscillation circuit Subclock oscillation circuit Subclock SCLK Clock generator Operation clock selector Machine Clock Oscillation stabilization wait time selector oscillation clock HCLK X0 2 X1 Clock selection register CKSCR Low Power consumption Mode Control Register LPMCR Time sleep stop sign Time stop sign Select the intermitted cycle Internal reset generator Terminal high impedance Contr...

Page 112: ...ock that is supplied to the CPU and peripheral function Clock selection register CKSCR The clock selection register is used to switch between the oscillation clock and PLL clock and between the main clock and sub clock also used to select an oscillation stabilization wait interval and a PLL clock multiplier PLL Subclock Control Register PSCCR The PLL subclock control register is used to select mul...

Page 113: ...explains the register of the clock generation block Clock Selection Register and List of Reset Value Figure 5 2 2 Clock Selection Register and List of Reset Value 1 0 1 1 1 1 14 13 12 11 10 9 0 1 15 8 Clock selection register CKSCR 0 0 0 0 PLL subclock control register PSCCR ...

Page 114: ...it 0 Select PLL clock 1 Select main clock bit11 SCS Sub clock select bit 0 Select sub clock 1 Select main clock bit13 bit12 WS1 WS0 Oscillation stabilization wait time select bit Parenthesized values are examples calculated at an oscillation clock HCLK frequency of 4 MHz 0 0 210 HCLK approx 256 µs 0 1 213 HCLK approx 2 05 ms 1 0 217 HCLK approx 32 77 ms 1 1 215 HCLK approx 8 19 ms other than power...

Page 115: ... during operation at an oscillation clock frequency of 4 MHz When the CPU switches from subclock mode to PLL clock mode or when it returns from PLL stop mode to PLL clock mode the oscillation stabilization wait time follows the values specified in these bits The PLL clock requires an oscillation stabilization wait time of at least 214 HCLK For switching from subclock mode to PLL clock mode and tra...

Page 116: ...he MCS bit thereby setting the subclock mode 2 When switching from the main clock to PLL clock CKSCR MCS 1 0 use the timebase timer interrupt enable bit TBTC TBIE or interrupt level mask register ILM ILM2 to 0 to disable timebase timer interrupts before writing 0 to the PLL clock select bit bit9 bit8 CS1 CS0 Multiplication rate select bits These bits select the PLL clock multiplication rate with t...

Page 117: ...on of each bit in the PLL subclock control register PSCCR Figure 5 4 1 Configuration of the PLL Subclock Control Register PSCCR Address 15 14 13 12 11 10 9 8 Reset value 0000CFH Re served SCDS Re served CS2 XXXX0000B W W W W W Write only X Undefined Unused Initial value bit8 CS2 Multiplication rate selection bit 0 See the clock selection register CKSCR 1 bit9 Reserved Reserved bit 0 Always write 0...

Page 118: ...s always 1 This bit is initialized to 0 by all reset causes bit9 Reserved bit Always write 0 to this bit Read value is always 1 bit8 CS2 Multiplication rate selection bit This bit and CS1 and CS0 bits of the clock selection register CKSCR determine the PLL multiplication rate CS2 CS1 CS0 PLL clock multiplication rate 0 0 0 1 0 0 1 2 0 1 0 3 0 1 1 4 1 1 0 6 1 1 1 Setting disabled Read value is alwa...

Page 119: ...ter CKSCR CS1 and CS0 and PLL subclock control register PSCCR CS2 Clock Mode Transition Transition among main clock mode PLL clock mode and sub clock mode is performed by writing to the MCS and SCS bits of the clock selection register CKSCR Transition from main clock mode to PLL clock mode When the MCS bit of the clock selection register CKSCR is rewritten from 1 to 0 in main clock mode switching ...

Page 120: ...ck and sub clock outputted from the PLL multiplier circuit are used as machine clock This machine clock is supplied to the CPU and peripheral functions The main clock PLL clock or sub clock can be selected by writing to the MCS or SCS bit of the clock selection register CKSCR Notes Even though the MCS and SCS bits of the clock selection register CKSCR are rewritten machine clock switching does not...

Page 121: ...0 10B CS2 0 PLL4 Main MCS 1 MCM 0 SCS 1 SCM 1 CS1 CS0 11B CS2 0 PLL1 Sub MCS 1 MCM 0 SCS 0 SCM 1 CS1 CS 00B CS2 0 PLL2 Sub MCS 1 MCM 0 SCS 0 SCM 1 CS1 CS0 01B CS2 0 PLL3 Sub MCS 1 MCM 0 SCS 0 SCM 1 CS1 CS0 10B CS2 0 PLL4 Sub MCS 1 MCM 0 SCS 0 SCM 1 CS1 CS0 11B CS2 0 10 Main Sub MCS 1 MCM 1 SCS 0 SCM 1 CS1 CS0 xxB CS2 x Sub Main MCS 1 MCM 1 SCS 1 SCM 0 CS1 CS0 xxB CS2 x Sub MCS X MCM 1 SCS 0 SCM 0 ...

Page 122: ...bit 10 Synchronous timing of main clock and sub clock 11 Write 1 to SCS bit MCS1 12 Termination of main clock oscillation stabilization wait time 13 Termination of main clock oscillation stabilization wait time CS1 CS0 00B CS2 0 14 Termination of main clock oscillation stabilization wait time CS1 CS0 01B CS2 0 15 Termination of main clock oscillation stabilization wait time CS1 CS0 10B CS2 0 16 Te...

Page 123: ...the oscillation stabilization wait interval has elapsed the machine clock is supplied to the CPU Because the oscillation stabilization wait time depends on the type of oscillator crystal ceramic etc the proper oscillation stabilization wait interval for the oscillator used must be selected An oscillation stabilization wait interval is selected by setting the clock selection register CKSCR When clo...

Page 124: ...k can be input to the microcontroller Connection of an Oscillator or an External Clock to the Microcontroller Example of connecting a crystal or ceramic oscillator to the microcontroller Figure 5 7 1 Example of Connecting a Crystal or Ceramic Oscillator to the Microcontroller Example of connecting an external clock to the microcontroller Figure 5 7 2 Example of Connecting an External Clock to the ...

Page 125: ...ation of the clock supervisor Only the product with built in clock supervisor of the MB90360 series is valid to this function 6 1 Overview of Clock Supervisor 6 2 Block Diagram of Clock Supervisor 6 3 Clock Supervisor Control Register CSVCR 6 4 Operating Mode of Clock Supervisor ...

Page 126: ...or bit of watchdog timer control register WDTC Supervising a main and a sub clock can be set to the disable watching prohibition respectively independently When a sub clock stops while the device is operating in the main clock mode internal reset is not generated at once When changing to the sub clock mode internal reset is generated It is also possible to control the internal reset generation by ...

Page 127: ...it Block Diagram of Clock Supervisor Figure 6 2 1 shows the block diagram of clock supervisor Figure 6 2 1 Block Diagram of Clock Supervisor 1 2 Internal bus Clock Supervisor control register CSVCR Control circuit Internal reset Internal main clock Internal sub clock Main clock selector Sub clock selector Sub clock supervisor Main clock supervisor CR oscillation circuit Enable Detection Enable Ena...

Page 128: ... clock of clock to be monitored are controlled by setting of clock supervisor control register CKSCR Clock supervisor control register CKSCR Disable or enable for main sub clock supervisor existence of internal reset generation when clock halt condition is detected or switching to CR oscillation clock of clock to be monitored are selected Main clock selector CR oscillation clock is outputted as ma...

Page 129: ...k supervisor enable 0 Sub clock supervisor is disabled 1 Sub clock supervisor is enabled bit3 MSVE Main clock supervisor enable 0 Main clock supervisor is disabled 1 Main clock supervisor is enabled bit4 RCE CR oscillation clock enable 0 CR oscillation clock is stopped 1 CR oscillation clock is enabled bit5 SM Sub clock missing 0 Missing sub clock has not been detected 1 Missing sub clock has been...

Page 130: ...zed to 0 by power on reset or external reset without T suffix product bit4 RCE CR oscillation clock enable This bit permits built in CR oscillation 1 Built in CR oscillation is enabled 0 Built in CR oscillation is disabled This bit is initialized to 1 by power on reset external reset or low voltage detection reset with T suffix product It is initialized to 1 by power on reset or external reset wit...

Page 131: ...s set to one and the reset is generated When the sub clock is stopped on the sub clock mode the sub clock is replaced with the CR oscillation two dividing frequency clock SM bit is set to one and the reset is generated When the sub clock is stopped on the main clock mode the sub clock is replaced with the CR oscillation two dividing frequency clock SM bit is set to one However the reset is not gen...

Page 132: ...ock mode When SRST is set to 1 the reset is generated at transition to the sub clock mode Stop Mode CR oscillation circuit the main clock and the sub clock supervisor automatically become disable at transition to the stop mode when all of these functions are enable Each enable bit of the clock supervisor control register is not changed Therefore after it is released from the stop mode each enable ...

Page 133: ...e factor is a reset from an external terminal or a reset by the clock supervisor include low voltage detection CPU operating detection reset in T suffix products If both SM and MM bits bit5 and bit6 of CSVCR are 0 the reset factor is an external reset include low voltage detection CPU operating detection reset in T suffix products If SM is 1 the reset factor is a sub clock lost If MM is 1 the rese...

Page 134: ...118 CHAPTER 6 CLOCK SUPERVISOR ...

Page 135: ... chapter describes resets for the MB90360 series microcontrollers 7 1 Resets 7 2 Reset Cause and Oscillation Stabilization Wait Times 7 3 External Reset Pin 7 4 Reset Operation 7 5 Reset Cause Bits 7 6 Status of Pins in a Reset ...

Page 136: ...d to 216 oscillation clock cycles 216 HCLK approx 16 38 ms oscillating at 4 MHz When the oscillation Table 7 1 1 Cause of a Reset Reset Cause Machine clock Watchdog timer Oscillation stabilization wait Power on At power on Main clock MCLK Stop Yes External pin L level input to RST pin Main clock MCLK Stop None Software Write 0 to internal reset signal generation bit RST of low power consumption mo...

Page 137: ...he main clock mode by the external reset pin RST pin from the stop mode sub clock mode sub sleep mode and watch mode input L level for at least oscillation time of oscillator 100 µs Oscillation time of oscillator is the time that amplitude reaches 90 It takes several to dozens of ms for crystal oscillators hundreds of µs to several ms for FAR ceramic oscillators and 0 ms for external clocks When r...

Page 138: ...the failure of the main clock subclock is detected the clock supervisor reset is generated The oscillation stabilization wait time is not required for the clock supervisor reset Definition of clocks HCLK Oscillation clock frequency MCLK Main clock frequency φ Machine clock CPU operating clock frequency 1 φ Machine cycle CPU operating clock period See 5 1 Clocks for details Note When the reset is o...

Page 139: ... Watchdog timer overflow None Note However the WS1 and WS0 bits are initialized to 11 External L input from RST pin None Note However the WS1 and WS0 bits are initialized to 11 Software Write 0 to RST bit of low power consumption mode control register LPMCR None Note However the WS1 and WS0 bits are initialized to 11 Low voltage detection 1 When low voltage is detected None Note However the WS1 an...

Page 140: ...llation Stabilization Wait Interval for details about oscillation stabilization wait times Oscillation Stabilization Wait and Reset State A reset operation in response to a power on reset and other resets during stop mode or sub clock mode is performed after the oscillation stabilization wait time has elapsed This time interval is generated by the timebase timer If the external reset has not been ...

Page 141: ...Block diagram of the external reset pin Figure 7 3 1 Block Diagram of the External Reset Pin Note Inputs to the RST pin are accepted during cycles in which memory is not affected to prevent memory from being destroyed by a reset during a write operation A clock is required to initialize the internal circuit In particular an operation with an external clock requires clock input together with reset ...

Page 142: ...w Figure 7 4 1 Reset Operation Flow Mode Pins Setting the mode pins MD0 to MD2 specifies how to fetch the reset vector and the mode data Fetching the reset vector and the mode data is performed in the reset sequence See 9 1 1 Mode Pins for details on mode pins External reset Software reset Watchdog timer reset Low voltage detection reset 1 CPU operation detection reset 1 Clock supervisor reset 2 P...

Page 143: ... 4 2 shows the transfer of the reset vector and mode data Figure 7 4 2 Transfer of Reset Vector and Mode Data Mode data address FFFFDFH Only a reset operation changes the contents of the mode register The mode register setting is valid after a reset operation See 9 1 2 Mode Data for details on mode data Reset vector address FFFFDCH to FFFFDEH The reset vector points to the start address after the ...

Page 144: ...e program Figure 7 5 1 Block Diagram of Reset Cause Bits RST L S R F F Q S R F F Q S R F F Q S R F F Q Set Flip Flop Reset Output For MB90F367 T S MB90367 T S Failure of main sub clock Clock supervisor Watchdog timer control register WDTC RST pin No periodic clear No periodic clear RST bit set Write detection circuit of LPMCR RST bits Watchdog timer reset generation detection circuit Power on Powe...

Page 145: ... only W Write only X Undefined Table 7 5 1 Correspondence between Reset Cause Bits and Reset Causes Reset cause PONR WRST ERST SRST Generation of power on reset request 1 X X X Generation of reset request due to watchdog timer overflow 1 External reset request from RST pin Low voltage detection reset product with T suffix 1 CPU operation detection reset product with T suffix 2 Clock supervisor res...

Page 146: ...Bit is cleared by reading the WDTC register and by writing 0 to LVRF 3 At low voltage detection 4 0 V 0 3 V The LVRF and ERST bits are set to 1 at low voltage detection of VCC 4 0 V 0 3 V 4 Bit clear Bit is cleared by reading the WDTC register and by writing 0 to LVRF 1 2 3 4 1 0 0 0 1 or 0 0 1 0 1 or 0 0 1 0 Vcc Vcc 4V Flag status at power on Bit clear Flag status at low voltage detection 4V Bit ...

Page 147: ...on reset For a power on reset because the PONR bit is set to 1 but all other reset cause bits are undefined the software should be programmed so that it will ignore all reset cause bits except the PONR bit if it is 1 Clearing the reset cause bits The reset cause bits are cleared only when the watchdog timer control register WDTC is read Any bit corresponding to a reset cause that has already been ...

Page 148: ...rnal vector mode has been set MD2 to MD0 011B All I O pins resource pins are high impedance and mode data is read from the internal ROM Status of Pins after Mode Data is Read The status of pins after mode data has been read depends on the mode data M1 and M0 When single chip mode has been selected M1 and M0 00B All I O pins resource pins are high impedance and mode data is read from the internal R...

Page 149: ...rview of Low Power Consumption Mode 8 2 Block Diagram of the Low Power Consumption Control Circuit 8 3 Low Power Consumption Mode Control Register LPMCR 8 4 CPU Intermittent Operation Mode 8 5 Standby Mode 8 6 Status Change Diagram 8 7 Status of Pins in Standby Mode and during Hold and Reset 8 8 Usage Notes on Low Power Consumption Mode ...

Page 150: ...ionship between the CPU operating modes and current consumption Figure 8 1 1 CPU Operating Mode and Current Consumption Several tens of 10mA Several µA Several mA Current consumption CPU operation mode PLL clock mode PLL clock intermittent opreting mode 6 multiplier clock 4 multiplier clock 3 multiplier clock 2 multiplier clock 1 multiplier clock 6 multiplier clock 4 multiplier clock 3 multiplier ...

Page 151: ...scillation stabilization wait time actual transition may be delayed Reference For the clock mode see 5 5 Clock Mode CPU Intermittent Operating Mode In this mode the CPU is operated intermittently while high speed clock pluses are supplied to peripheral functions thereby reducing power consumption In this mode intermittent clock pulses are supplied only to the CPU while it is accessing a register i...

Page 152: ... and sub clock SCLK during operation in each clock mode and all functions other than low voltage detection circuit stop Data can be retained at the lowest power consumption Note When the clock mode is switched do not switch to other clock mode and low power consumption mode before this switching is completed Confirm the completion of clock mode switching by referring to the MCM and SCM bits of the...

Page 153: ...ed CS2 SCDS MB90367 T S Watch timer Timebase timer Main clock To watchdog timer Clock supervisor Subclock oscillation circuit Internal CR oscillation clock Clock selector Clock selector 2 divided Oscillation clock HCLK Sub clock HCLK PLL subclock control register PSCCR bit10 4 divided 2 divided Oscillation clock generator Pin Pin Pin Pin Clock select register CKSCR PLL multiplier circuit Clock gen...

Page 154: ...circuit This circuit makes I O pins high impedance in the watch mode timebase timer mode and stop mode Internal reset generation circuit This circuit generates an internal reset signal Low power consumption mode control register LPMCR This register is used to switch to and release the standby mode and to set the CPU intermittent operation mode ...

Page 155: ... watch and stop mode bit5 0 1 STP bit7 bit6 SLP 0 1 R W R W R W W W R W W W bit2 bit1 CG1 CG0 0 0 1 1 0 1 0 1 STP SLP SPL RST TMD CG1 CG0 Re served Reset value Reserved bit Be sure to set this bit to 0 Re served CPU suspended cycle number select bit 0 cycle CPU clock peripheral clock 8 cycle CPU clock peripheral clock 1 approx 3 to 4 16 cycle CPU clock peripheral clock 1 approx 5 to 6 32 cycle CPU...

Page 156: ...mode or timebase timer mode When the bit is set to 0 The current level of input output pins is held When the bit is set to 1 The I O pins enter a high impedance state The bit is initialized to 0 at a reset bit4 RST Internal reset signal generation bit This bit generates software reset When the bit is set to 0 An internal reset signal for three machine cycles is generated When the bit is set to 1 N...

Page 157: ...egister LPMCR with C language refer to Notes on Accessing the Low Power Consumption Mode Control Register LPMCR to Enter the Standby Mode in 8 8 Usage Notes on Low Power Consumption Mode When word length is used for writing the low power consumption mode control register LPMCR even addresses must be used Using odd addresses to switch to a low power consumption mode may result in a malfunction To s...

Page 158: ...xecution speed of the CPU is reduced thereby enabling low power consumption processing The low power consumption mode control register LPMCR CG1 and CG0 is used to select the number of machine cycles that halts the clock supplied to the CPU Instruction execution time in the CPU intermittent operation mode can be calculated A correction value should be obtained by multiplying the execution count of...

Page 159: ...HCLK Sub clock SCLK Machine clock CPU Peripheral function Pin Release method Sleep mode Main sleep mode MCS 1 SCS 1 SLP 1 External reset or interrupt Sub sleep mode MCS X SCS 0 SLP 1 External reset or interrupt PLL sleep mode MCS 0 SCS 1 SLP 1 External reset or interrupt Timebase timer mode SPL 0 MCS X SCS 1 TMD 0 1 External reset or interrupt 4 SPL 1 MCS X SCS 1 TMD 0 1 Hi Z 3 External reset or i...

Page 160: ... SCS Subclock select bit in the clock selection register CKSCR SPL Pin state specification bit of low power consumption mode control register LPMCR SLP Sleep mode bit of low power consumption mode control register LPMCR STP Stop mode bit of low power consumption mode control register LPMCR TMD Watch mode bit of low power consumption mode control register LPMCR Note For those external pins shared b...

Page 161: ...leep mode Note When 1 is written to the SLP and STP bits of the low power consumption mode control register LPMCR at the same time the STP bit setting overrides the SLP bit setting and the mode switches to the stop mode When 1 is written to the SLP bit and 0 is written to the TMD bit at the same time the TMD bit setting overrides the SLP bit setting and the mode switches to the timebase timer mode...

Page 162: ...n RST pin input the Low level for at least oscillator s oscillation time 100 µs 16 machine cycles main clock The oscillation time for the oscillator is the period of time taken until its amplitude reaches 90 It takes several to dozens of ms for crystal oscillators hundreds of µs to several ms for FAR ceramic oscillators and 0 ms for external clocks Return by interrupt When a higher interrupt reque...

Page 163: ...ly executes the instruction that follows the instruction in which a sleep mode has been specified The CPU then proceeds to interrupt processing I 0 ILM IL NO YES YES YES NO NO Set to interupt flag of resources No cancellation of sleep No cancellation of sleep Cancellation of sleep Execute the next instruction INT generate IL 7 Execution of interrupt process ...

Page 164: ...iately branches to the interrupt processing routine Status of pins Whether the I O pins in the watch mode retain the state they had immediately before switching to the watch mode or go to the high impedance state can be controlled by the SPL bit of the low power consumption mode control register LPMCR Note To set the pin that is shared the peripheral function and port to the high impedance in the ...

Page 165: ...t is identified immediately after return from the watch mode When the CPU is not ready to accept any interrupt request the next instruction to the currently executing instruction is executed When the CPU is ready to accept any interrupt request it immediately branches to the interrupt processing routine Note When interrupt processing is executed the CPU normally executes the instruction following ...

Page 166: ... If the CPU is not ready to accept any interrupt request the instruction next to currently executing instruction is executed If the CPU is ready to accept any interrupt request an interrupt operation immediately branches to the interrupt processing routine Status of pins Whether the I O pins in the timebase timer mode retain the state they had immediately before switching to the timebase timer mod...

Page 167: ...R the interrupt level mask register ILM and the interrupt control register ICR When the CPU is not ready to accept any interrupt request the next instruction to the currently executing instruction is executed When the CPU is ready to accept any interrupt request it immediately branches to the interrupt processing routine The following two timebase timer modes are available Main clock timebase time...

Page 168: ...ntrol register LPMCR are set to 1 simultaneously the STP bit is preferred and the mode transits to the stop mode Data retention function In the stop mode the contents of the dedicated registers such as accumulators and the internal RAM are retained Operation during an interrupt request Writing 1 in the STP bit of the low power consumption mode control register LPMCR during an interrupt request doe...

Page 169: ...is cancelled after the elapse of the main clock oscillation stabilization wait time or the sub clock oscillation stabilization wait time Return by reset factor When the stop mode is cancelled by a reset factor the main clock oscillation stabilization wait time is generated After the termination of the main clock oscillation stabilization wait time the stop mode is cancelled transiting to the reset...

Page 170: ...s executed the CPU normally executes the instruction following the instruction in which the stop mode has been specified The CPU then proceeds to interrupt processing When transiting to the PLL stop mode set the oscillation stabilization wait time selection bits in the clock selection register CKSCR WS1 WS0 to 10B or 11B In PLL stop mode the main clock and PLL multiplication circuit stop During re...

Page 171: ...lock mode PLL clock mode SCS 1 MCS 0 MCS 1 SCS 0 Subclock mode Subsleep mode Watch mode Substop mode Subclock oscillation stabilization wait PLL sleep mode PLL stop mode Main clock oscillation stabilization wait Main sleep mode Main timebase timer mode PLL timebase timer mode Main stop mode Main clock oscillation stabilization wait Interrupt Interrupt SLP 1 Interrupt SLP 1 Interrupt TMD 0 Interrup...

Page 172: ...used When the pin is set as input port handle the pull up pull down or input the external signal When the pin is set as output port the pin is set to the same state as other pins 2 Indicates that either the output pins output their state as it is immediately before entering each standby mode or the input pins are input disabled Output of the output state as it is means that when the resource with ...

Page 173: ...rated from the resource and external interrupt during operation in the sleep mode watch mode timebase timer mode or stop mode the standby mode is cancelled The standby mode is cancelled by an interrupt regardless of whether the CPU accepts interrupts or not Note To prevent the CPU from causing a branch to interrupt servicing immediately after returning from standby mode take measures such as disab...

Page 174: ...ilization wait time and PLL clock oscillation stabilization wait time The oscillation stabilization wait time for the main clock and PLL clock are counted simultaneously according to the value specified in the oscillation stabilization wait time selection bits in the clock selection register CKSCR WS1 WS0 The oscillation stabilization wait time selection bits in the clock selection register CKSCR ...

Page 175: ... occur within the function optimize the function during compilation to suppress the LINK and UNLINK instructions from occurring Example Watch mode or timebase timer mode transition function 2 Define the standby mode transition instruction using __asm statements and insert two NOP and JMP instructions after that instruction Example Transition to sleep mode 3 Define the standby mode transition instr...

Page 176: ...160 CHAPTER 8 LOW POWER CONSUMPTION MODE ...

Page 177: ...161 CHAPTER 9 MEMORY ACCESS MODES This chapter explains the functions and operations of the memory access modes 9 1 Outline of Memory Access Modes ...

Page 178: ...n be performed Bus mode Bus mode means the mode for controlling the internal ROM operation and external access function The bus mode is specified by the MDx mode setting pin and the Mx bit in mode data The MDx mode setting pin specifies the bus mode for reading the reset vector and mode data and the Mx bit in mode data specifies the bus mode for normal operation Run mode Run mode means the CPU ope...

Page 179: ...D1 MD0 0 0 0 Setting disabled 0 0 1 0 1 0 0 1 1 Internal vector mode Internal Mode data Reset sequence and subsequent sequences are controlled by mode data 1 0 0 Setting disabled 1 0 1 1 1 0 Flash serial programming 1 1 1 Flash memory Mode when parallel writer is used The serial programming of the flash memory cannot be written only by setting the mode pin Other pin also need to be set See CHAPTER...

Page 180: ...fter the reset sequence Always set the reserved bits to 0 Mode Data Figure 9 1 1 Mode Data Configuration bit7 and bit6 M1 M0 bus mode setting bits The M1 and M0 bits are used to specify the operation mode after the reset sequence is completed Table 9 1 3 shows the relationship between the M1 and M0 bits and the functions 7 6 5 4 3 2 1 0 Address FFFFDFH M1 M0 Reserved Reserved Reserved Reserved Res...

Page 181: ...9 1 2 Relationship between Access Areas and Physical Addresses for Each Bus Mode FFFFFFH 010000H 007900H RAM 000100H 0000F0H 000000H I O 008000H ROM area Address 1 Address 2 ROM area Image of FF Bank Extended I O area General purpose register Internal Access disabled Single chip Product type Address 1 Address 2 MB90F362 T S MB90362 T S MB90F367 T S MB90367 T S FF0000H 000D00H MB90V340A 101 102 F80...

Page 182: ...e 9 1 4 lists an example of recommended settings for mode pins and mode data External pins have signal functions that depend on each mode Table 9 1 4 Recommended Setting Example of Mode Pin and Mode Data Setting example MD2 MD1 MD0 M1 M0 Single chip 0 1 1 0 0 ...

Page 183: ...167 CHAPTER 10 I O PORTS This chapter explains the functions and operations of the I O ports 10 1 I O Ports 10 2 I O Port Registers ...

Page 184: ...er peripheral function the logic level at the pin is read regardless of the port data register value It is generally recommended that the read modify write instructions should not be used for setting the port data register prior to setting the port as an output This is because the read modify write instruction in this case results reading the logic level at the port rather than the register value ...

Page 185: ... 1 8 0 ADE15 ADE14 ADE13 ADE12 ADE11 ADE10 ADE9 ADE8 ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0 15 7 14 6 13 5 12 4 11 3 10 2 9 1 8 0 IL6 IL5 IL4 IL2 IL8 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Address 000002H Address 000004H Address 000005H Address 000006H Address 000008H Address 000012H Address 000014H Address 000015H Address 000016H Address 000018H Address 00001AH Bit No Bit No Bit No Bit No Bit No Addres...

Page 186: ...ng pin Figure 10 2 2 shows the port data registers PDR Port Data Register PDR Figure 10 2 2 Port Data Registers PDR P27 P26 P25 P24 P23 P22 P21 P20 P44 P43 P42 P41 P40 P54 P53 P52 P51 P50 P67 P66 P65 P64 P63 P62 P61 P60 P87 P86 P85 P84 P83 P82 P80 P57 P56 P55 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Bit No Reset value Access Undefined R W Undefined R W Undefi...

Page 187: ...onnected to the pin The following shows the value obtained by each combination Value of DDR Output state of peripheral function Reading value 0 input Enabled Output value from peripheral function 1 output Enabled Output value from peripheral function 0 input Disabled Pin state 1 output Disabled Value of output latch Further when using as input by peripheral function set the DDR of the connected pi...

Page 188: ...o SIL1 correspond to SIN0 LIN UART0 to SIN1 LIN UART1 respectively When setting to 0 CMOS or Automotive is selected for the input level depending on the setting of the corresponding ILx bit and ILTx bit in the ILSR See 10 2 5 Input Level Select Register for ILSR When set to 1 CMOS is selected for the input level regardless of the setting of the corresponding ILx bit and ILTx bit in ILSR The initia...

Page 189: ...y write RMW operation such as the INC DEC instruction cannot be used at DDRA DDRA Bits 0 to 2 Bits 5 to 7 unused bits 1 is always read from these bits Writing to these bits is no effect Table 10 2 1 SIN0 SIN1 Input Level Setting DDRA ILSR SIN0 P82 SIN1 P85 input level SIL0 SIL1 bit IL8 bit 0 0 Automotive level 0 1 CMOS level 1 x CMOS level ...

Page 190: ...l up Control Register PUCR In input mode the pull up resistor is controlled 0 No pull up resistor in input mode 1 Pull up resistor in input mode Note In output mode this register has no meaning no pull up resistor The port direction register DDR determines the input output mode In stop mode SPL 1 the state with no pull up resistor is entered high impedance PU27 PU26 PU25 PU24 PU23 PU22 PU21 PU20 7...

Page 191: ...log input mode A pin set to the analog input mode is the dedicated analog input pin for the A D converter The pin cannot be used as I O pin of I O port and other peripheral function Note When the analog input enable bit ADEx is set to 1 each pin of the port 6 and port 5 is the analog input pin for the A D converter Initial value of the ADEx bit is 1 Therefore the corresponding pins cannot be used ...

Page 192: ...input level The initial value of these bits depends on the mode pin setting For the flash memory mode the initial value is 1 TTL For all other modes the initial value is 0 Automotive bit 0 bit 1 bit 3 bit 7 and bit 9 to bit 15 undefined Reading from these bits is undefined Writing to these bits is no effect Note The threshold of the corresponding input pin varies immediately after the setting of t...

Page 193: ...ing table About detail of each mode please see CHAPTER 9 MEMORY ACCESS MODES Table 10 2 2 Relationship between Mode Pin and Initial Value of Input Level Select Register ILSR MD2 MD1 MD0 Operation mode Initial value Port input level ILx Port 2 4 to 6 8 0 0 0 Reserved 0 0 1 0 1 0 0 1 1 Internal vector mode 0 Automotive 1 0 0 Reserved 1 0 1 1 1 0 Flash serial write 0 Automotive 1 1 1 Flash memory 1 T...

Page 194: ...178 CHAPTER 10 I O PORTS ...

Page 195: ...mebase timer 11 1 Overview of Timebase Timer 11 2 Block Diagram of Timebase Timer 11 3 Configuration of Timebase Timer 11 4 Interrupt of Timebase Timer 11 5 Explanation of Operations of Timebase Timer Functions 11 6 Precautions when Using Timebase Timer 11 7 Program Example of Timebase Timer ...

Page 196: ...counter reaches the interval time set by the interval time select bits TBTC TBC1 TBC0 an overflow carrying occurs TBTC TBOF 1 and an interrupt request is generated When an interrupt is enabled when an overflow occurs TBTC TBIE 1 an overflow occurs TBTC TBOF 1 and an interrupt is generated The timebase timer has four interval times that can be selected Table 11 1 1 shows the interval times of the t...

Page 197: ...e to supply clock Clock cycle Oscillation stabilization wait time 210 HCLK approx 256 µs 213 HCLK approx 2 0 ms 215 HCLK approx 8 2 ms 217 HCLK approx 32 8 ms Watchdog timer 212 HCLK approx 1 0 ms 214 HCLK approx 4 1 ms 216 HCLK approx 16 4 ms 219 HCLK approx 131 1 ms PPG timer 29 HCLK approx 128 µs HCLK Oscillation clock The parenthesized values are provided at 4 MHz oscillation clock As the osci...

Page 198: ...est number 25 19H 21 HCLK CKSCR MCS 1 0 1 CKSCR SCS 0 1 2 OF OF OF OF TBIE TBOF TBC1 TBC0 TBR 21 22 211 212 213 214 215 216 217 218 210 29 28 23 To PPG timer Timebase timer counter To watchdog timer To clock control part oscillation stabilization waiting time selector Interval timer selector Counter clear circuit Power on reset Stop mode Timebase timer control register TBTC Timebase timer interrup...

Page 199: ...e or PLL stop mode CKSCR SCS 1 LPMCR STP 1 Switching the clock mode from main clock mode to PLL clock mode from subclock mode to PLL clock mode or from subclock mode to main clock mode Interval timer selector The interval timer selector selects the output of the timebase timer counter from four types When incrementing causes the selected interval time bit to overflow carrying an interrupt request ...

Page 200: ...er Generation of Interrupt Request from Timebase Timer When the selected interval timer counter bit reaches the interval time the overflow interrupt request flag bit in the timebase timer control register TBTC TBOF is set to 1 If the overflow interrupt request flag bit is set TBTC TBOF 1 when the interrupt is enabled TBTC TBIE 1 the timebase timer generates an interrupt request 0 0 0 1 1 0 15 14 b...

Page 201: ...lation clock The parenthesized values are provided when the oscillation clock operates at 4 MHz bit9 bit8 TBC1 TBC0 Interval time select bit 0 0 212 HCLK approx 1 0 ms 0 1 214 HCLK approx 4 1 ms 1 0 216 HCLK approx 16 4 ms 1 1 219 HCLK approx 131 1 ms bit10 TBR Timebase timer counter clear bit Read Write 0 1 is always read Clear timebase timer counter Clear TBOF bit 1 No effect bit11 TBOF Overflow...

Page 202: ...state remains unchanged Read by read modify write instructions 1 is read Note 1 To clear the TBOF bit disable interrupts TBIE 0 or mask interrupts using the interrupt mask register ILM in the processor status 2 The TBOF bit is cleared at a write of 0 transition to main stop mode or to PLL stop mode transition from subclock mode to main clock mode or to PLL clock mode transition from main clock mod...

Page 203: ... is set to 1 When the overflow interrupt request flag bit in the timebase timer control register is set TBTC TBOF 1 with an interrupt enabled TBTC TBIE 1 an interrupt request is generated When the selected interval time is reached the overflow interrupt request flag bit in the timebase timer control register TBTC TBOF is set regardless of whether an interrupt is enabled or disabled TBTC TBIE To cl...

Page 204: ... active When the timebase timer counter reaches the interval time set by the interval time select bits in the timebase timer control register TBTC TBC1 TBC0 it causes an overflow carrying and the overflow interrupt request flag bit TBTC TBOF is set to 1 When the overflow interrupt request flag bit is set TBTC TBOF 1 with interrupts enabled TBTC TBIE 1 an interrupt request is generated Note The int...

Page 205: ...K 3FFFFH 00000H Oscillation stabilization waiting time Oscillation clock Cancellation of sleep at interval interrupt of timebase timer Counter value Clear by transferring to stop mode Interval cycle TBTC TBC1 TBC0 11B Start CPU operation Power on reset TBOF bit TBIE bit STP bit LPMCR register Stop Clear by interrupt process Sleep SLP bit LPMCR register Counter clear TBTC TBR 0 Oscillation stabiliz...

Page 206: ...bit TBTC TBR Reset Power on reset Transition to main clock mode after oscillation stabilization wait time of main clock completed Watchdog reset None External reset Low voltage detection reset CPU operation detection reset Clock supervisor reset None Software reset None Switching clock mode Main clock PLL clock CKSCR MCS 1 0 Transition to PLL clock mode after oscillation stabilization wait time of...

Page 207: ...clear Oscillation stabilization wait time Cancellation of stop modes Cancellation of main stop mode Transition to main clock mode after oscillation stabilization wait time of main clock completed Cancellation of PLL stop mode Transition to PLL clock mode after oscillation stabilization wait time of main clock completed Cancellation of sub stop mode Transition to sub clock mode after oscillation st...

Page 208: ...ain stop mode PLL stop mode and sub clock mode the oscillation clock stops Therefore when oscillation starts the timebase timer requires the oscillation stabilization wait time of the main clock An appropriate oscillation stabilization wait time must be selected according to the types of oscillators connected to high speed oscillation input pins Reference For details on the oscillation stabilizati...

Page 209: ... TBIE EQU TBTC 2 Interrupt enable bit Main program CODE CSEG START Stack pointer SP already initialized AND CCR 0BFH Interrupt disable MOV I ICR07 00H Interrupt level 0 highest MOV I TBTC 10000000B Upper 3 bis are fixed TBOF clear Counter clear interval time 212 HCLK selection SETB I TBIE Interrupt enable MOV ILM 07H Setting ILM in PS to level 7 OR CCR 40H Interrupt enable LOOP MOV A 00H No limit ...

Page 210: ...194 CHAPTER 11 TIMEBASE TIMER DSL WARI ORG 0FFDCH Reset vector setting DSL START DB 00H Setting to single chip mode VECT ENDS END START ...

Page 211: ...operation of the watchdog timer 12 1 Overview of Watchdog Timer 12 2 Configuration of Watchdog Timer 12 3 Watchdog Timer Registers 12 4 Explanation of Operations of Watchdog Timer Functions 12 5 Precautions when Using Watchdog Timer 12 6 Program Examples of Watchdog Timer ...

Page 212: ...t interval time If the set interval time is reached without clearing the watchdog timer counter the CPU is reset This is called watchdog timer The interval time of the watchdog timer depends on the clock cycle input as a count clock and a watchdog reset occurs between the minimum and maximum times The clock source output destination is set by the watchdog clock select bit in the watch timer contro...

Page 213: ... 1 147 s Approx 5 898 s 221 218 HCLK Approx 458 75 ms Approx 589 82 ms Approx 9 175 s Approx 47 186 s Sub Clock cycle Examples calculated External clock 32kHz 4 frequency division CR oscillation Min Max Min 200kHz Max 50kHz 212 29 SCLK Approx 0 437 s Approx 0 563 s Approx 0 018 s Approx 0 092 s 215 212 SCLK Approx 3 500 s Approx 4 500 s Approx 0 143 s Approx 0 737 s 216 213 SCLK Approx 7 000 s App...

Page 214: ...unt clock to the watchdog timer clearing the timebase timer may extend the time for a watchdog reset to occur When the subclock is used as the machine cock be sure to set the watchdog timer clock source select bit WDCS in the watch timer control register WTC to 0 to select the watch timer output ...

Page 215: ...lear control circuit Watchdog timer control register WDTC Watch timer control register WTC Watchdog reset generation circuit 2 bit counter Count clock selector Generation of reset Shift to sleep mode Timebase timer counter Watch counter HCLK Oscillation clock SCLK Sub clock SCLK is 2 division or 4 division of the clock inputted to the low speed oscillation pin X0A and X1A or internal CR oscillatio...

Page 216: ...output or watch timer output as a count clock The clock source output destination is set by the watchdog clock select bit in the watch timer control register WTC WDCS Watchdog reset generator The watchdog reset generation circuit generates a reset signal when the watchdog timer overflows carrying Counter clear circuit The counter clear circuit clears the watchdog timer counter Watchdog timer contr...

Page 217: ...ion explains the registers used for setting the watchdog timer List of Registers and Reset Values of Watchdog Timer Figure 12 3 1 List of Registers and Reset Values of Watchdog Timer 1 1 1 7 6 bit 5 4 3 2 1 0 Watchdog timer control register WDTC Undefined Address 0000A8H ...

Page 218: ...rt up the watchdog timer Twice or more programming after reset Clear the watchdog timer 1 No effect SCLK Sub clock 2 The parenthesized values are interval time when the oscillation clock bit1 bit0 WT1 WT0 Interval time select bit watch timer output select Interval time Clock cycle Min Max 0 0 approx 0 457 s approx 0 576 s 212 29 SCLK 0 1 approx 3 584 s approx 4 608 s 215 212 SCLK 1 0 approx 7 168 ...

Page 219: ...f the watch timer Data after the watchdog timer is started is valid only Write data after the watchdog timer is started is ignored These are write only bits bit2 WTE Watchdog timer control bit This bit starts or clears the watchdog timer When set to 0 first time after reset The watchdog timer is started When set to 0 second or subsequent The watchdog timer is cleared bit6 Undefined bit Read The va...

Page 220: ...ected When the bit is set to 0 the watch timer is selected After a reset the bit returns to 1 During operation in the sub clock mode set the WDCS bit to 0 to select the watch timer Setting interval time Set the interval time select bits WDTS WT1 WT0 to select the interval time for the watchdog timer Set the interval time concurrently when starting the watchdog timer Writing to the bit is ignored a...

Page 221: ...ime it overflows and the CPU is reset A reset or transitions to the standby modes sleep mode stop mode watch mode timebase timer mode clear the watchdog timer During operation in the timebase timer mode or watch mode the watchdog timer counter is cleared However the watchdog timer remains in the activation state Figure 12 4 2 shows relationship between clear timing and interval time of watchdog ti...

Page 222: ...n circuit Count enable output circuit 2 division circuit 2 bit counter WTE bit Count enable and clear Minimum interval time When clear WTE bit immediately before rising of count clock Count clock a 2 division s value b 2 division s value c Count enable Reset signal d Count start Counter clear 7 Count clock cycle 2 WTE bit clear Watchdog reset generation Maximum interval time When clear WTE bit imm...

Page 223: ...mer counter clear bit TBR in the timebase timer control register TBTC and when the clock mode changes from the main clock to PLL clock from the subclock to main clock or from the subclock to PLL clock Set the interval time concurrently when starting the watchdog timer Setting the time interval except starting the watchdog timer is ignored Precautions when creating program When clearing the watchdo...

Page 224: ... the minimum interval time of the watchdog timer Coding example WDTC EQU 0000A8H Watchdog timer control register WTE EQU WDTC 2 Watchdog control bit Main program CODE CSEG START Stack pointer SP already initialized MOV I WDTC 00000011B Start up of watchdog timer Select interval time 221 218 cycle LOOP CLRB I WTE Clear watchdog timer ÅE User processing ÅE BRA LOOP Vector setting VECT CSEG ABS 0FFH ...

Page 225: ...of 16 bit I O Timer 13 2 Block Diagram of 16 bit I O Timer 13 3 Configuration of 16 bit I O Timer 13 4 Interrupts of 16 bit I O Timer 13 5 Explanation of Operation of 16 bit Free run Timer 13 6 Explanation of Operation of Input Capture 13 7 Precautions when Using 16 bit I O Timer 13 8 Program Example of 16 bit I O Timer ...

Page 226: ...t free run timer can be use as the base time for the input capture One of eight types of the count clock cycle can be set An overflow in the counter generates an interrupt request The counter of the 16 bit free run timer is cleared to 0000H by reset or timer clear TCCSL CLR 1 Functions of input capture The input capture consists of four 16 bit capture registers and control registers corresponding ...

Page 227: ...run timer The count value of the 16 bit free run timer can be used as the base time for the input capture Input capture When the trigger edge is inputted to the external input pin or when the trigger edge for the LIN slave baud rate measurement from the LIN UART is inputted the counter value of the 16 bit free run timer is retained and the interrupt request is generated at the same time Internal d...

Page 228: ...mber Channel Special terminal Pin name Interrupt No For I2 OS Input capture ch0 using 16 bit free run timer ch0 IN0 P24 IN0 33 21H Input capture ch1 using 16 bit free run timer ch0 IN1 P25 IN1 Input capture ch2 using 16 bit free run timer ch0 IN2 P26 IN2 Input capture ch3 using 16 bit free run timer ch0 IN3 P27 IN3 16 bit free run timer ch0 overflow interrupt FRCK0 P44 FRCK0 30 1EH ...

Page 229: ...nter value of the 16 bit free run timer During stopping of the 16 bit free run timer the counter value can be set by writing the counter value to the TCDT Timer control status register TCCSH TCCSL The timer control status register upper and lower selects the count clock and the condition for clearing the counter clears the counter enables the count operation and interrupt request checks the overfl...

Page 230: ...3 ICUS0 ICUS1 IEI0 IEI1 2 2 IN1 LIN UART1 LIN UART0 IN0 IN3 IN2 Input capture data register 0 IPCP0 Pin Pin Pin Pin Input capture data register 1 IPCP1 Input capture control status register ICS01 Input capture control status register ICS23 Input capture interrupt request Internal data bus Input capture edge register ICE23 16 bit free run timer Input capture data register 3 IPCP3 Input capture data...

Page 231: ...trol status register indicated the edge polarity detected by each input capture Also it selects the input signal external pin INx LIN UART When input is set to the LIN UART the baud rate measurement at the LIN slave operation can be performed See 20 7 3 Operation with LIN Function Operation Mode 3 Input capture edge register has 2 registers and the input capture operation of the corresponding chan...

Page 232: ...ree run timer overflow Input capture interrupt If the input capture interrupt request is set to enable ICS ICE 1 if the trigger edge is detected by the input capture pin or if the trigger edge for the LIN slave baud rate measurement from the LIN UART is inputted the interrupt request is generated Table 13 3 1 Pins of 16 bit I O Timer Channel Pin Name Pin Function Setting to use the pin 16 bit free...

Page 233: ...ined Indetermination Reset value Address Reset value bit15 ECKE External clock input enable bit 0 Use the internal clock prescaler output 1 Use the external clock FRCK0 pin input Table 13 3 2 Function of Timer Control Status Register Upper TCCSH Bit name Function bit15 ECKE External clock input enable bit This bit selects the count clock of the 16 bit free run timer When set to 1 Use the clock inp...

Page 234: ...K0 R W Read Write Reset value Reset value φ Machine clock frequency bit2 bit1 bit0 CLK2 CLK1 CLK0 Count clock cycle selection bits 0 0 0 1 φ 0 0 1 2 φ 0 1 0 4 φ 0 1 1 8 φ 1 0 0 16 φ 1 0 1 32 φ 1 1 0 64 φ 1 1 1 128 φ bit3 CLR Timer clear bit 0 No effect 1 Clear counter TCDT 0000H bit4 Reserved Reserved bit 0 Be sure to set to 0 bit5 STOP Timer operation stop bit 0 Timer operating enabled 1 Timer op...

Page 235: ...rupt request is generated When set to 0 The generation of the interrupt request is disabled bit5 STOP Timer operation stop bit This bit enables or disables stops the operation of the 16 bit free run timer When set to 0 Enable the timer operation and count up with count clock set by the CLK2 to CLK0 When set to 1 Stops count operation bit4 Reserved bit Always set this bit to 0 bit3 CLR Timer clear ...

Page 236: ...ear bit of the timer control status register TCCSL CLR 1 Setting of 0000H to the timer data register during stopping of 16 bit free run timer Reset Setting of counter value Write the counter value to the timer data register TCDT and set the timer during stopping the timer operation TCCSL STOP 1 Note Always use a word instruction MOVW to read write the timer data register R W R W R W R W R W R W R ...

Page 237: ...g edge 1 1 Detect both edges bit4 ICEn Capture interrupt enable bit n 0 Input capture 0 interrupt disable 1 Input capture 0 interrupt enable bit3 bit2 EGm1 EGm0 Edge select bit m 0 0 Without edge detection operation stop state 0 1 Detect rising edge 1 0 Detect falling edge 1 1 Detect both edges bit5 ICEm Capture interrupt enable bit m 0 Input capture 1 interrupt disable 1 Input capture 1 interrupt...

Page 238: ...s or disables the interrupt request of the input capture m When set to 1 When the valid edge detection flag bit m is set to 1 ICSnm ICPm 1 the interrupt request is generated bit4 ICEn Capture interrupt enable bit n This bit enables or disables the interrupt request of the input capture n When set to 1 When the valid edge detection flag bit n is set to 1 ICSnm ICPn 1 the interrupt request is genera...

Page 239: ...the input capture register R R R R R R R R CP03 CP00 CP01 CP02 CP07 CP04 CP05 CP06 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 XXXXXXXXB R R R R R R R R CP11 CP08 CP09 CP10 CP15 CP12 CP13 CP14 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 XXXXXXXXB R R R R R R R R CP03 CP00 CP01 CP02 CP07 CP04 CP05 CP06 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 XXXXXXXXB R R R R R R R R CP11 CP08 CP09 CP10 CP15 CP12 CP1...

Page 240: ...N3 Input Capture Edge Register ICE Figure 13 3 6 Input Capture Edge Register ICE X R R W R R R W R W IEI0 IEI1 ICUS0 ICUS1 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 ICE01 000051H ICE23 000053H R R IEI2 IEI3 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 XXX0X0XXB XXXXXXXXB n 0 2 m n 1 bit10 ICUS0 Input signal selection bit 0 0 Input signal of external pin IN0 1 Signal from UART0 Reset value bit...

Page 241: ... the trigger of the input capture 0 When set to 0 Select the external pin IN0 When set to 1 Select the IN UART0 bit9 IEI1 Detection edge indication bit 1 This bit indicated the edge detected by the input capture 1 rising falling This bit is read only 0 Indicate that falling edge is detected 1 Indicate that rising edge is detected Note This bit value is disabled when the capture operation is stoppe...

Page 242: ... 23 ICE23 Bit name Function bit15 to bit10 Undefined bits Read The value is undefined Write No effect bit9 IEI3 Detection edge indication bit 3 This bit indicates the edges detected by the input capture 3 rising falling This bit is read only 0 Indicate that falling edge is detected 1 Indicate that rising edge is detected Note This bit value is disabled when the capture operation is stopped ICSnm E...

Page 243: ...FE 1 if the timer overflow generation flag is set to 1 TCCSL IVF 1 the interrupt request is generated Input capture Interrupt When the valid edge set by the input capture pin ICS EG is detected or when the trigger edge for the LIN slave baud rate measurement from the LIN UART is inputted valid edge must be set to both edges the interrupt is shown below The counter value of the detected 16 bit free...

Page 244: ...rrupt number interrupt control register and interrupt vector address see CHAPTER 3 INTERRUPTS Correspondence to EI2 OS Function The input capture corresponds to the EI2 OS function However to use the EI2 OS function it is necessary to disable other interrupt that shares the interrupt control register ICR ...

Page 245: ...imer operation TCCSL STOP 0 Generation of overflow and interrupt request When overflow FFFFH 0000H occurs in the 16 bit free run timer the timer overflow generation flag is set to 1 TCCSL IVF and starts incrementing from 0000H When the timer overflow interrupt request is enabled TCCSL IVFE 1 the interrupt request is occurred Clear factor of counter value and clear timing Table 13 5 1 shows the cle...

Page 246: ...230 CHAPTER 13 16 Bit I O TIMER Figure 13 5 2 shows counter clearing at an overflow Figure 13 5 2 Counter Clearing at an Overflow FFFFH BFFFH 7FFFH 3FFFH 0 0 0 0 H Counter value Reset Time Overflow ...

Page 247: ...falling IEI 0 The valid edge detection flag of the input capture control status register is set to 1 ICS ICP 1 When the input capture interrupt request is enabled ICS ICE 1 the interrupt request is generated To measure the baud rate at the LIN slave operation it is necessary to set the input signal to the LIN UART ICE ICUS enable the input capture interrupt request ICS ICE 1 and set the valid edge...

Page 248: ...N N 1 N 1 φ Machine clock Data fetch φ Input capture input Capture signal Capture register Counter value Valid edge FFFFH BFFFH 7 F F F H 3 F F F H 0 0 0 0 H 7FFFH 3FFFH Counter value Reset Time INn rising edge Capture n Undefined Undefined INm falling edge Capture m n 0 2 m n 1 FFFFH BFFFH 7 F F F H 3 F F F H 0 0 0 0 H BFFFH 3FFFH Counter value Reset Time INn both edge Capture example Undefined n...

Page 249: ...SL STOP 0 The counter value of the 16 bit free run timer is cleared to 0000H by reset Stop the 16 bit free run timer TCCSL STOP 1 then write the counter value to the timer data register TCDT directly Always use a word instruction to write the timer data register TCDT Operation delay by synchronization operation The input capture generates delay of operation time because it synchronizes with the op...

Page 250: ...n 1 th IPCP0 value count clock cycle overflow count 10000H nth IPCP0 value n 1 th IPCP0 value 0 17 µs Coding example ICR09 EQU 0000B9H Interrupt control register ICR11 EQU 0000BBH Interrupt control register DDR2 EQU 000012H Port 2 direction register TCCSL EQU 007942H Timer control status register TCDT EQU 007940H Timer data register ICS01 EQU 000050H Input capture control status register IPCP0 EQU...

Page 251: ...OV CNT and input capture value User processing MOV A 0 Clear overflow count counter MOV OV_CNT A for next cycle measurement RETI Recover from interrupt WARI1 CLRB I IVF0 Clear timer overflow generation flag INC OV_CNT Increment overflow counter User processing RETI Recover from interrupt CODE ENDS Vector setting VECT CSEG ABS 0FFH ORG 00FF78H Setting vector to interrupt number 33 21H Input capture...

Page 252: ...236 CHAPTER 13 16 Bit I O TIMER ...

Page 253: ...mer 14 1 Overview of the 16 bit Reload Timer 14 2 Block Diagram of 16 bit Reload Timer 14 3 Configuration of 16 bit Reload Timer 14 4 Interrupts of 16 bit Reload Timer 14 5 Explanation of Operation of 16 bit Reload Timer 14 6 Precautions when Using 16 bit Reload Timer 14 7 Sample Program of 16 bit Reload Timer ...

Page 254: ...e timer control status register TMCSR CSL1 CSL0 are set to 00B 01B or 10B the 16 bit reload timer is set in the internal clock mode In the internal clock mode the 16 bit reload timer decrements in synchronization with the internal clock The count clock select bits in the timer control status register TMCSR CSL1 CSL0 can be used to select three count clock cycles The start trigger sets the edge det...

Page 255: ...putted from the TOT pin The pin output level select bit in the timer control status register TMCSR OUTL can be set to select the level High or Low of the rectangular wave Reload mode TMCSR RELD 1 When an underflow occurs the value set in the TMRLR is reloaded to the TMR continuing the TMR count operation In the reload mode a toggle wave inverting the output level of the TOT pin is outputted each t...

Page 256: ...of 16 bit Reload Timer CSL1 CSL0 MOD2 MOD1 OUTL OUTE RELD INTE UF CNTE TRG MOD0 TMR TMRLR TOT EN TIN 2 3 3 CLK CLK Internal data bus 16 bit reload register Reload signal 16 bit timer register UF Reload control circuit Valid clock judgement circuit Prescaler Gate input Machine clock φ Wait signal Input control circuit Clock selector Pin Function selection External clock Output control circuit Outpu...

Page 257: ...er 16 bit timer register TMR The 16 bit timer register TMR is a 16 bit down counter At read the value being counted is read 16 bit reload register TMRLR The 16 bit reload register TMRLR sets the interval time of the 16 bit reload timer When the 16 bit reload timer starts operation or the 16 bit timer register TMR underflows the value set in the TMRLR is reloaded to the TMR Timer control status reg...

Page 258: ...8 D82 0 Serial control register Setting for the reception disable SCR0 RXE 0 Disable the external interrupt external interrupt enable register ENIR1 EN14 0 P83 SOT0 TOT2 General purpose I O port UART output 0 16 bit reload timer output 2 Serial control register Setting for the transmission disable SCR0 TXE 0 Timer control status register Enable the timer output TMCSR2 OUTE 1 P53 AN11 TIN3 General ...

Page 259: ... X X X X X bit 7 6 5 4 3 2 1 0 16 bit Timer Register Lower TMR2 X X X X X X X X bit 15 14 13 12 11 10 9 8 16 bit Reload Register Upper TMRLR2 X X X X X X X X bit 7 6 5 4 3 2 1 0 16 bit Reload Register Lower TMRLR2 X X X X X X X X X Undefined bit 15 14 13 12 11 10 9 8 Timer Control Status Register Upper TMCSR3 X X X X 0 0 0 0 bit 7 6 5 4 3 2 1 0 Timer Control Status Register Lower TMCSR3 0 0 0 0 0 ...

Page 260: ...t reload timer is started and the count value of the 16 bit timer register is decremented from 0000H to FFFFH an underflow occurs When an underflow occurs the UF bit in the timer control status register is set to 1 TMCSR UF If an underflow interrupt is enabled TMCSR INTE 1 an interrupt request is generated ...

Page 261: ...7 MOD2 MOD1 MOD0 Operating mode select bit internal clock mode CSL1 0 00B 01B 10B Input pin function Valid edge level 0 0 0 Trigger disable 0 0 1 Trigger input Rising edge 0 1 0 Falling edge 0 1 1 Both edges 1 X 0 Gate input L level 1 X 1 H level bit9 bit8 bit7 MOD2 MOD1 MOD0 Operating mode select bit event count mode CSL1 0 11B Input pin function Valid edge X 0 0 X 0 1 Trigger input Rising edge X...

Page 262: ...r Internal clock mode The MOD2 bit is used to select the function of the input pin When MOD2 bit set to 0 The input pin functions as a trigger input The MOD1 and MOD0 bits are used to select the edge to be detected When the edge is detected the value set in the 16 bit reload register TMRLR is reloaded in the 16 bit timer register TMR starting the count operation of the TMR When MOD2 set to 1 The i...

Page 263: ...rs High TMCSR H Reset value Address bit0 TRG Software trigger bit 0 No effect 1 After reloading starts counting bit1 CNTE Timer operation enable bit 0 Timer operation disabled 1 Timer operation enabled wait start trigger bit2 UF Underflow generating flag bit Read Write 0 No underflow Clear UF bit 1 Underflow No effect bit3 INTE Underflow interrupt enable bit 0 Underflow interrupt disable 1 Underfl...

Page 264: ...ount operation reload mode When set to 0 At underflow stops count operation one shot mode bit3 INTE Underflow interrupt enable bit This bit enables or disables an underflow interrupt When an underflow occurs TMCSR UF 1 with an underflow interrupt enabled TMCSR INTE 1 an interrupt request is generated bit2 UF Underflow generating flag bit This bit indicates that the TMR underflows When set to 0 Cle...

Page 265: ...curs Reload mode When the TMR underflows the value set in the TMRLR is reloaded to the TMR restarting the TMR count operation One shot mode When the TMR underflows the TMR count operation is stopped entering the start trigger input wait state The TMR value is retained to FFFFH Notes The TMR can be read during the TMR count operation However always use the word instruction MOVW The TMR and the TMRL...

Page 266: ...ed the value set in the TMRLR is reloaded to the TMR starting the TMR count operation Notes Perform a write to the TMRLR after disabling the operation of the 16 bit reload timer TMCSR CNTE 0 Always use the word instruction MOVW The TMRLR and the TMR are assigned to the same address At write the set value can be written to the TMRLR without affecting the TMR At read the TMR value being counted is r...

Page 267: ...reload timers 2 and 3 correspond to the EI2 OS function An underflow in the TMR starts the EI2 OS However the EI2 OS is available only when other resources sharing the interrupt control register ICR do not use interrupts The 16 bit reload timers 2 and 3 share the ICR04 When using the EI2 OS in the 16 bit reload timers 2 and 3 it is necessary to disable the interrupt of the 16 bit reload timer shar...

Page 268: ...n external event to operate the 16 bit reload timer requires the setting shown in Figure 14 5 2 Figure 14 5 2 Setting of Event Count Mode TMCSR 1 TMRLR CSL1 CSL0 MOD2 MOD1 OUTL OUTE RELD INTE UF CNTE TRG MOD0 11 10 9 8 5 6 4 3 2 1 7 14 13 12 bit0 bit15 1 Other than 11B Set the reload value to 16 bit timer register Used bit Set 1 TMCSR TMRLR CSL1 CSL0 MOD2 MOD1 OUTL OUTE RELD INTE UF CNTE TRG MOD0 ...

Page 269: ... TOUT pin General purpose I O port 16 bit timer register retain the value at stop the value immediately after resetting is undefined Reset WAIT state RUN state TIN pin only trigger input is valid 16 bit timer register retains the value at stop the value immediately after resetting is undefined TOUT pin outputs value of 16 bit reload register TIN pin function as input pin of 16 bit reload timer TOU...

Page 270: ... reload timer TMRLR is set to the internal clock mode In the internal clock mode the 16 bit timer register TMR decrements in synchronization with the internal clock In the internal clock mode three count clock cycles can be selected by setting the count clock select bits in the timer control status register TMCSR CSL1 CSL0 Setting a reload value to TMR After the 16 bit reload timer is started the ...

Page 271: ...n the 16 bit reload timer register TMRLR is reloaded to the TMR continuing the TMR count operation In the reload mode a toggle wave inverting the output level of the TOT pin is outputted each time an underflow occurs during the TMR count operation The pin output level select bit in the timer control status register TMCSR OUTL can be set to select the level High or Low of a toggle wave as the 16 bi...

Page 272: ...FH Counter clock Counter Data load signal CNTE bit TRG bit UF bit TOT pin Start trigger input wait T Machine cycle It takes 1 machine cycle time to load data of reload register from trigger input Reloaddata 0000H Reloaddata 0000H Reloaddata 0000H Reloaddata T 1 1 1 1 Count clock Counter Data load signal UF bit CNTE bit TRG bit TOT pin T Machine cycle It takes 1 T time to load data of reload regist...

Page 273: ...s Note The trigger pulse width of the edge to be inputted to the TIN pin should be 2 T T machine cycles or more Figure 14 5 6 Count Operation in External Trigger Mode One shot Mode Figure 14 5 7 Count Operation in External Trigger Mode Reload Mode Reloaddata 0000H 1 FFFFH Reloaddata 0000H 1 FFFFH 2T to 2 5T Counter clock Counter Data load signal UF bit CNTE bit TIN pin TOT pin T Machine cycle It t...

Page 274: ...e input level High or Low can be selected by setting the operating mode select bits in the timer control status register TMCSR MOD2 to MOD0 Figure 14 5 8 Count Operation in External Gate Input Mode One shot Mode Figure 14 5 9 Count Operation in External Gate Input Mode Reload Mode 0000H Reloaddata T 1 1 1 1 FFFFH T Counter clock Counter Data load signal UF bit CNTE bit TIN pin TOT pin T Machine cy...

Page 275: ...t mode by setting the count clock select bits in the timer control status register TMCSR CSL1 CSL0 to 11B In the event count mode the TMR decrements in synchronization with the edge detection of the external event clock input to the TIN pin Setting initial value of counter After the 16 bit reload timer is started the value set in the TMRLR is reloaded to the TMR 1 Disables the operation of the 16 ...

Page 276: ...nt operation is stopped entering the start trigger input wait state When the next start trigger is inputted the TMR count operation is restarted In the one shot mode a rectangular wave is outputted from the TOT pin during the TMR count operation The pin output level select bit in the timer control status register TMCSR OUTL can be set to select the level High or Low of the rectangular wave Reload ...

Page 277: ...he operating mode select bits in the timer control status register TMCSR MOD2 to MOD0 the detected edge can be selected from the rising edge falling edge and both edges Note The level width of the external event clock to be inputted to the TIN pin should be 4 T T machine cycles or more Figure 14 5 10 Count Operation in Event Count Mode One shot Mode Figure 14 5 11 Count Operation in Event Count Mo...

Page 278: ...ount operation However always use the word instruction Change the CSL1 and CSL0 bits in the TMCSR after disabling the timer operation TMCSR CNTE 0 Precautions on interrupt When the UF bit in the TMCSR is set to 1 and the underflow interrupt output is enabled TMCSR INTE 1 it is impossible to return from interrupt processing Always clear the UF bit However when the EI2 OS is used the UF bit is clear...

Page 279: ... control register for 16 bit reload timer TMCSR2 EQU 000064H Timer control status register TMR2 EQU 00794CH 16 bit timer register TMRLR2 EQU 00794CH 16 bit reload register UF2 EQU TMCSR2 2 Interrupt request flag bit CNTE2 EQU TMCSR2 1 Counter operation enable bit TRG2 EQU TMCSR2 0 Software trigger bit Main program CODE CSEG Stack pointer SP already initialized AND CCR 0BFH Interrupts disabled MOV ...

Page 280: ...al event input pin are counted 10000 times by the 16 bit reload timer 2 Operation is performed in the one shot mode The rising edge is selected for the external trigger input EI2 OS is not used Coding example ICR04 EQU 0000B4H Interrupt control register for 16 bit reload timer TMCSR2 EQU 000064H Timer control status register TMR2 EQU 00794CH 16 bit timer register TMRLR2 EQU 00794CH 16 bit reload r...

Page 281: ...d external output disabled One shot mode selected interrupt enabled Interrupt flag cleared count started MOV ILM 07H Set ILM in PS to level 7 OR CCR 40H Interrupts enabled LOOP Processing by user BRA LOOP Interrupt program WARI CLR I UF2 Interrupt request flag cleared Processing by user RETI Return from interrupt CODE ENDS Vector setting VECT CSEG ABS 0FFH ORG 00FFB0H Set vector to interrupt 19 13...

Page 282: ...266 CHAPTER 14 16 BIT RELOAD TIMER ...

Page 283: ...the functions and operations of the watch timer 15 1 Overview of Watch Timer 15 2 Block Diagram of Watch Timer 15 3 Configuration of Watch Timer 15 4 Watch Timer Interrupt 15 5 Explanation of Operation of Watch Timer 15 6 Program Example of Watch Timer ...

Page 284: ...o WTC0 the bit corresponding to the interval time of the watch timer counter overflows carries and the overflow flag bit is set WTC WTOF 1 When the overflow flag bit is set WTC WTOF 1 with interrupt enabled when an overflow occurs WTC WTIE 1 an interrupt request is generated The interval time of the watch timer can be selected from eight types shown in Table 15 1 1 Table 15 1 1 Interval Times of W...

Page 285: ...The division ratio is set by the SCDS bit of the PLL subclock control register PSCCR When using the internal CR oscillation clock see CHAPTER 6 CLOCK SUPERVISOR Please con sider the frequency difference of built in CR oscillation when you use built in CR oscillation clock as a sub clock Table 15 1 2 Cycle of Clock Supplied from Watch Timer Where to Supply Clock Clock Cycle Timer for oscillation st...

Page 286: ...tch timer counter The watch timer counter is a 15 bit up counter that uses the subclock SCLK as a count clock Counter clear circuit The counter clear circuit clears the watch timer counter WTOF WTR WTC1 WTC0 WTC2 WDCS SCE WTIE 25 24 23 21 29 210 211 212 213 214 215 28 27 26 22 SCLK OF OF OF OF OF OF OF OF To watchdog timer Watch timer counter Power on reset Transits to hardware standby Transits to...

Page 287: ... watch timer counter reaches the interval time set in the watch timer control register WTC Watch timer control register WTC The watch timer control register WTC selects the interval time clears the watch timer counter enables or disables an interrupt checks the overflow carry state and clears the overflow flag bit ...

Page 288: ...atch Timer Generation of Interrupt Request from Watch Timer When the interval time set by the interval time select bits WTC WTC2 to WTC0 is reached the overflow flag bit WTC WTOF is set to 1 When the overflow flag bit is set WTC WTOF 1 with interrupt enabled when the watch timer counter overflows carries WTC WTIE 1 an interrupt request is generated 1 0 0 0 0 6 5 4 3 2 1 0 1 7 0 bit Address 0000AAH...

Page 289: ... bit Read Write 0 Clear watch timer counter 1 1 is always read No effect Reset value R W Read Write R Read only X Undefined SCLK Subclock Reset value bit4 WTOF Overflow flag bit Read Write 0 No overflow of the bit corresponding to set interval time Clears WTOF bit 1 Overflow of the bit corresponding to set interval time No effect bit5 WTIE Overflow interrupt enable bit 0 Interrupt request disable ...

Page 290: ...IE Overflow interrupt enable bit This bit enables or disables generation of an interrupt request when the watch timer counter overflows carries When set to 0 Interrupt request not generated even at overflow WTOF 1 When set to 1 Interrupt request generated at overflow WTOF 1 bit4 WTOF Overflow flag bit This bit is set to 1 when the counter value of the watch timer reaches the value set by the inter...

Page 291: ... is set to 1 WTC WTOF 1 When the overflow flag bit is set WTC WTOF 1 with the watch timer interrupt enabled WTC WTIE 1 an interrupt request is generated At interrupt processing set the WTOF bit to 0 and cancel the interrupt request Watch Timer Interrupt and EI2 OS Transfer Function The watch timer does not correspond to the EI2 OS function For details of the interrupt number interrupt control regi...

Page 292: ...rrupt enable bit WTIE in the WTC register to 0 and set the watch timer to interrupt inhibited state Before permitting an interrupt clear the interrupt request issued by writing zero to the overflow flag bit WTOF in the WTC register Interval Timer Function The watch timer can be used as an interval timer by generating an interrupt at each interval time Settings when using watch timer as interval ti...

Page 293: ... the clock input source of the watchdog timer When using the subclock as the machine clock always set the WDCS bit to 0 and select the output of the watch timer Oscillation Stabilization Wait Time Timer of Subclock When the watch timer returns from the power on reset and the stop mode it functions as an oscillation stabilization wait time timer of subclock The subclock oscillation stabilization wa...

Page 294: ... timer control register WTOF EQU WTC 4 Overflow flag bit Main program CODE CSEG START Stack pointer SP already initialized AND CCR 0BFH Interrupt disabled MOV I ICR07 00H Interrupt level 0 highest MOV I WTC 10100101B Interrupt enabled Overflow flag cleared Watch timer counter cleared 213 SCLK approx 1 0 s MOV ILM 07H Set ILM in PS to level 7 OR CCR 40H Interrupt enabled LOOP Processing by user BRA...

Page 295: ...279 CHAPTER 15 WATCH TIMER ORG 00FFDCH Reset vector set DSL START DB 00H Set to single chip mode VECT ENDS END START ...

Page 296: ...280 CHAPTER 15 WATCH TIMER ...

Page 297: ...ons of the 8 16 bit PPG timer 16 1 Overview of 8 16 bit PPG Timer 16 2 Block Diagram of 8 16 bit PPG Timer 16 3 Configuration of 8 16 bit PPG Timer 16 4 Interrupts of 8 16 bit PPG Timer 16 5 Explanation of Operation of 8 16 bit PPG Timer 16 6 Precautions when Using 8 16 bit PPG Timer ...

Page 298: ...s This section explains the functions of PPGC D PPGE F has the same functions as PPGC D Functions of 8 16 bit PPG Timer The 8 16 bit PPG timer consists of four 8 bit reload registers PRLHC PRLLC PRLHD and PRLLD and two PPG down counters PCNTC and PCNTD Individual setting of High and Low widths in output pulse enables an output pulse of any cycle and duty ratio The count clock can be selected from ...

Page 299: ...1 7 ns 1 φ to 28 φ 2 φ to 29 φ 2 φ 83 3 ns 2 φ to 29 φ 22 φ to 210 φ 22 φ 167 ns 22 φ to 210 φ 23 φ to 211 φ 23 φ 333 ns 23 φ to 211 φ 24 φ to 212 φ 24 φ 667 ns 24 φ to 212 φ 25 φ to 213 φ 29 HCLK 128 µs 29 HCLK to 217 HCLK 210 HCLK to 218 HCLK HCLK Oscillation clock φ Machine clock The parenthesized values are provided when the oscillation clock operates at 4 MHz and the machine clock operates at...

Page 300: ...se Time Interval Time Output Pulse Time 1 φ 41 7 ns 1 φ to 28 φ 2 φ to 29 φ 1 φ to 216 φ 2 φ to 217 φ 2 φ 83 3 ns 2 φ to 29 φ 22 φ to 210 φ 2 φ to 217 φ 22 φ to 218 φ 22 φ 167 ns 22 φ to 210 φ 23 φ to 211 φ 22 φ to 218 φ 23 φ to 219 φ 23 φ 333 ns 23 φ to 211 φ 24 φ to 212 φ 23 φ to 219 φ 24 φ to 220 φ 24 φ 667 ns 24 φ to 212 φ 25 φ to 213 φ 24 φ to 220 φ 25 φ to 221 φ 29 HCLK 128µs 29 HCLK to 217 ...

Page 301: ...or the 8 16 bit PPG timer C and 8 16 bit PPG timer D The PPGE has the same function as the PPGC and PPGF has the same function as PPGD Channels and PPG Pins of PPG Timers Figure 16 2 1 shows the relationship between the channels and the PPG pins of the 8 16 bit PPG timers in the MB90360 series Figure 16 2 1 Channels and PPG Pins of PPG Timers PPGC D PPGCD REV PPGE F PPGEF REV Pin Pin Pin PPGC outp...

Page 302: ...request output Select signal Operation mode control signal Reload register L H selector Count start value Reload Clear Pulse selector Underflow PPGD underflow PPGC underflow to PPGD PPGC down counter PCNTC Invert PPGC output latch PPG output control circuit PPGD output Timebase timer output 512 HCLK Resource clock 1 φ Resource clock 2 φ Resource clock 4 φ Resource clock 8 φ Resource clock 16 φ Cou...

Page 303: ... 2 channel PPG down counters PPGC and PPGD can also be concatenated for use as a single channel 16 bit PPG down counter PPGC temporary buffer PRLBHC This buffer prevents deviation of the output pulse width caused at writing to the PPG reload registers PRLHC and PRLLC This buffer stores the PRLHC value temporarily and enables it in synchronization with the timing of writing to the PRLLC Reload regi...

Page 304: ...mporary buffer PRLBHD Interrupt request output Reload register L H selector Select signal Clear Reload Count start value Under flow PPGD down counter PCNTD PPGD underflow to PPGC Invert PPGD output latch PPG output control circuit Pin PPGC output PPGC underflow from PPGC Timebase timer output 512 HCLK Resource clock 1 φ Resource clock 2 φ Resource clock 4 φ Resource clock 8 φ Resource clock 16 φ C...

Page 305: ...inverted The 2 channel PPG down counters PPGC and PPGD can also be connected for use as a single channel 16 bit PPG down counter PPGD temporary buffer PRLBHD This buffer prevents deviation of the output pulse width caused at writing to the PPG reload registers PRLHD and PRLLD It stores the PRLHD value temporarily and enables it in synchronization with the timing of writing to the PRLLD Reload regi...

Page 306: ... PPG Timer PPGC P66 AN6 PPGC General purpose I O port A D converter analog input 6 PPG output C Analog input enable register setting to disable ADER6 ADE6 0 PPG operating mode control register pin output enable PPGCC PE0 1 PPGD P22 PPGD General purpose I O port PPG output D PPG operating mode control register pin output enable PPGCD PE1 1 PPGE P67 AN7 PPGE General purpose I O port A D converter an...

Page 307: ...ts of channels causing an underflow are enabled PPGCn PIE0 1 PPGCm PIE1 1 an underflow interrupt request is generated to the interrupt controller 15 14 bit 13 12 11 10 9 8 7 6 bit 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 15 14 bit 13 12 11 10 9 8 bit 0 1 0 0 0 0 0 15 14 bit 13 12 11 10 9 8 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 0 1 0 0 0 bit 0 PPGm operation mode control register H PPGCm PPGn operatio...

Page 308: ...ode Control Register PPGCC Figure 16 3 2 PPGC Operation Mode Control Register PPGCC 4 5 3 2 1 0 7 6 R W R W R W R W 0 X 0 0 0 X X 1B R W PEN0 PE0 PIE0 PUF0 Re served Address chC PPGCC 000048H Other channel chE PPGCE 00004CH Reset value bit 0 Re served Reserved bit 1 Always set to 1 bit 3 PUF0 Underflow generation flag bit Read Write 0 No underflow Clears PUF0 bit 1 Underflow No effect bit 4 PIE0 U...

Page 309: ...pin The pulse output is enabled bit4 PIE0 Underflow interrupt enable bit This bit enables or disables an interrupt When set to 0 No interrupt request generated even at underflow PUF0 1 When set to 1 Interrupt request generated at underflow PUF0 1 bit3 PUF0 Underflow generation flag bit 8 bit PPG output 2 channel independent operation mode 8 8 bit PPG output operation mode When the value of the PPG...

Page 310: ...5 14 R W R W R W R W R W R W 0 X 0 0 0 0 0 1B W PEN1 PE1 PIE1 Re served PUF1 MD1 MD0 Address chD PPGCD 000049H Other channel chF PPGCF 00004DH Reset value bit 8 Re served Reserved bit 1 Always set to 1 bit 10 bit 9 MD1 MD0 Operation mode select bits 0 0 8 bit PPG output 2 channels independent operation mode 0 1 8 8 bit PPG output operation mode 1 0 Setting disable 1 1 16 bit PPG output operation m...

Page 311: ...at underflow PUF1 1 When set to 1 Interrupt request is generated at underflow PUF1 1 bit11 PUF1 Underflow generation flag bit 8 bit PPG output 2 channel independent operation mode 8 8 bit PPG output operation mode When the value of the PPGD down counter is decremented from 00H to FFH an underflow occurs PUF1 1 16 bit PPG output operation mode When the values of the PPGC and PPGD down counters are ...

Page 312: ...04EH Read Write Indeterminate Undefined Reset value Oscillation clock Machine clock frequency bit 0 REV PPG output pin select bit 0 Output pulse from standard output pin 1 Switch output pin between PPGn and PPGm Reset value bit 7 bit 6 bit 5 PCS2 PCS1 PCS0 PPGD count clock select bits 0 0 0 1 φ 41 7 ns 0 0 1 2 φ 83 3 ns 0 1 0 22 φ 167 ns 0 1 1 23 φ 333 ns 1 0 0 24 φ 667 ns 1 0 1 Setting disable 1 ...

Page 313: ... the 8 bit PPG output 2 channel independent mode PPGCD MD1 MD0 00B bit4 to bit2 PCM2 to PCM0 PPGC count clock select bits These bits set the count clock of the 8 16 bit PPG timer C The count clock can be selected from five frequency divided clocks of the machine clock and the frequency divided clocks of the timebase timer bit1 Undefined bit Read The value is undefined Write No effect bit0 REV PPG ...

Page 314: ...n the 8 8 bit PPG output operation mode PPGCD MD1 MD0 01B set the same value in both the Low level and High level PPG reload registers PRLLC PRLHC of the 8 16 bit PPG timer C Setting a different value in the Low level and High level PPG reload registers may cause the 8 16 bit PPG timer D to have different PPG output waveforms at each clock cycle R W R W R W R W R W R W R W R W D11 D8 D9 D10 D15 D1...

Page 315: ...ut operation mode In the 16 bit PPG output operation mode when the values of the PPGn and PPGm down counters are decremented from 0000H to FFFFH an underflow occurs When an underflow occurs the underflow generation flag bits in the two channels are set at one time PPGCn PUF0 1 or PPGCm PUF1 1 When an underflow occurs with either of the two channel of the interrupt requests enabled PPGCn PIE1 0 PPG...

Page 316: ...the reload registers are reloaded to the PPG down counters when an underflow occurs the pin output is inverted Figure 16 5 1 shows the output waveform of the 8 16 bit PPG timer Figure 16 5 1 Output Waveform of 8 16 bit PPG Timer Operation modes of 8 16 bit PPG timer As long as the operation of the 8 16 bit PPG timer is enabled PPGCn PEN0 1 PPGCm PEN1 1 a pulse waveform is outputted continuously fr...

Page 317: ...ion mode requires the setting shown in Figure 16 5 2 Figure 16 5 2 Setting for 8 bit PPG Output 2 channel Independent Operation Mode Note Use the word instruction to set both High level and Low level PPG reload registers PRLLn PRLHn and PRLLm PRLHm at the same time PIE1 PUF1 MD0 MD1 PEN1 PE1 PPGCm PPGCn 1 0 0 1 1 1 PIE0 PUF0 PEN0 PE0 PPGnm PCM2 PCM1 REV PCM0 PCS2 PCS1 PCS0 bit15 14 13 12 11 10 9 b...

Page 318: ... to enable the operation of the PPG timer PPGCn PENC 1 PPGCm PEND 1 the PPG down counter of the enabled channel starts counting To stop the count operation of the PPG down counter disable the operation of the PPG timer of the channel to be stopped PPGCn PENC 0 PPGCm PEND 0 The count operation of the PPG down counter is stopped and the output of the PPG output pin is held at a Low level When the PP...

Page 319: ...ns for calculating the pulse width are shown below PL T L 1 PH T H 1 PL Low width of output pulse PH High width of output pulse L Values of 8 bits in PPG reload register PRLLn or PRLLm H Values of 8 bits in PPG reload register PRLHn or PRLHm T Count clock cycle Figure 16 5 3 shows the output waveform in the 8 bit PPG output 2 channel independent operation mode Figure 16 5 3 Output Waveform in 8 bi...

Page 320: ... to set the values in the PPG reload registers or a word instruction to set the PPGn and PPGm PRLLn PRLLm or PRLHn PRLHm in this order PIE1 PUF1 MD0 MD1 PEN1 PE1 PPGCm PPGCn 1 1 1 1 1 PIE0 PUF0 PEN0 PE0 PPGnm PCM2 PCM1 REV PCM0 PCS2 PCS1 PCS0 bit15 14 13 12 11 10 9 bit8 bit7 6 5 4 3 2 1 bit0 PRLHn PRLLn PRLHm PRLLm 1 Re served Reserved area Re served PPGn set high level side reload values of lower...

Page 321: ... down counter underflows the reload values set in the PPGn and PPGm reload registers PRLLn PRLHn PRLLm PRLHm are reloaded simultaneously to the PPG down counters PCNTn PCNTm When an underflow occurs the underflow generation flag bits in both channels are set simultaneously PPGCn PUFC 1 PPGCm PUFD 1 If an interrupt request is enabled at either channel PPGCn PIEC 1 PPGCm PIED 1 an interrupt request ...

Page 322: ...for calculating the pulse width are shown below PL T L 1 PH T H 1 PL Low width of output pulse PH High width of output pulse L Values of 16 bits in PPG reload register PRLLn PRLLm H Values of 16 bits in PPG reload register PRLHn PRLHm T Count clock cycle Figure 16 5 5 shows the output waveform in the 16 bit PPG output operation mode Figure 16 5 5 Output Waveform in 16 bit PPG Output Operation Mode...

Page 323: ...e 16 5 6 Figure 16 5 6 Setting for 8 8 bit PPG Output Operation Mode Note Use the word instruction to set both High level and Low level PPG reload registers PRLLn PRLHn PRLLm PRLHm at the same time PIE1 PUF1 MD0 MD1 PEN1 PE1 PPGCm PPGCn 1 0 1 1 1 1 PIE0 PUF0 PEN0 PE0 PPGnm PCM2 PCM1 REV PCM0 PCS2 PCS1 PCS0 bit15 14 13 12 11 10 9 bit8 bit7 6 5 4 3 2 1 bit0 PRLHn PRLLn PRLHm PRLLm Re served Reserved...

Page 324: ...he count operation of the PPG down counters disable the operation of the PPG timers of both channels PPGCn PEN0 0 and PPGCm PEN1 0 The count operation of the PPG down counters is stopped and the output of the PPG output pin is held at a Low level If the PPG down counter of each channel underflows the reload values set in the PPG reload registers PRLLn PRLHn PRLLm PRLHm are reloaded to the PPG down...

Page 325: ...es of 8 bits in PPG reload register PRLHn Lm Values of 8 bits in PPG reload register PRLLm Hm Values of 8 bits in PPG reload register PRLHm T Count clock cycle Figure 16 5 7 shows the output waveform in the 8 8 bit PPG output operation mode Figure 16 5 7 Output Waveform in 8 8 bit PPG Output Operation Mode T L0 1 L1 1 T H0 1 H1 1 T L0 1 T H0 1 Operation start Operation stop PPG operation enable bi...

Page 326: ...e widths are determined at the timing of reloading the values in the Low level PPG reload registers PRLLn PRLLm to the PPG down counter If the 8 bit PPG timer is used in the 8 bit PPG output 2 channel independent operation mode or the 8 8 bit PPG output operation mode use a word instruction to set both High level and Low level PPG reload registers PRLLn PRLHn PRLLm PRLHm at the same time Using a b...

Page 327: ...are written temporarily to the temporary latch written to the PPGm reload registers PRLLm PRLHm and then transferred to the PPGn reload registers PRLLn PRLHn Therefore when setting the reload value in the PPGm reload registers PRLLm PRLHm it is necessary to set the reload value in the PPGn reload registers PRLLn PRLHn simultaneously or set the reload value in the PPGn reload registers PRLLn PRLHn ...

Page 328: ...Mode Reload value of PPGm Reload value of PPGn Only 16 bit PPG output operation mode Write to PPGn except 16 bit PPG output operation mode Transfers synchronously with writing to PPGm Temporary latch Write to PPGm PPG reload register PRLLn PRLHn PPG reload register PRLLm PRLHm Note n C E m n 1 ...

Page 329: ...al interrupt 17 1 Overview of DTP External Interrupt 17 2 Block Diagram of DTP External Interrupt 17 3 Configuration of DTP External Interrupt 17 4 Explanation of Operation of DTP External Interrupt 17 5 Precautions when Using DTP External Interrupt 17 6 Program Example of DTP External Interrupt Function ...

Page 330: ...sfer for the specified number of times Table 17 1 1 shows an overview of the DTP external interrupt Table 17 1 1 Overview of DTP External Interrupt External Interrupt DTP Function Input pin 8 pins INT8 INT9R INT10 INT11 INT12R INT13 INT14R INT15R Interrupt factor The interrupt factor is set in unit of pins using the detection level setting registers ELVR1 Input of High level Low level rising edge ...

Page 331: ...10 LB10 LA11 LB11 EN8 EN9 EN10 EN11 EN12 EN13 EN14 EN15 ER8 ER9 ER10 ER11 ER12 ER13 ER14 ER15 Level edge selector INT15R INT14R INT13 INT12R INT11 INT10 INT9R INT8 Level edge selector Level edge selector Level edge selector Level edge selector Level edge selector Level edge selector Level edge selector Pin Pin Pin Pin Pin Pin Pin Pin Internal data bus DTP external interrupt input detection circuit...

Page 332: ...ster holds DTP external interrupt factors If an enable signal is inputted to the DTP external interrupt pin the corresponding DTP external interrupt request flag bit is set to 1 DTP external interrupt enable register ENIR1 This register enables or disables DTP external interrupt requests from external peripheral devices Details of Pins and Interrupt Numbers Table 17 2 1 shows the pins and interrup...

Page 333: ...xternal interrupt factor select register EISSR to 0 Set as input ports in port direction register DDR5 P55 AN13 INT10 General purpose I O ports analog input DTP external interrupt inputs P56 AN14 INT11 P57 AN15 INT13 P42 INT9R RX1 General purpose I O ports DTP external interrupt inputs CAN1 input Rx1 Set external interrupt factor select register EISSR to 1 Set as input ports in port direction regi...

Page 334: ...00000 EN11 EN10 EN9 EN8 EN12 7 6 5 4 3 2 1 0 EN13 EN15 EN14 Address 0000CA H bit ENIR1 15 14 13 12 11 10 9 8 Address 0000CB H ER11 ER10 ER9 ER8 ER12 ER13 ER15 ER14 bit EIRR1 Address 0000CD LA10 7 6 5 4 3 2 1 0 Address 0000CC H H 15 14 13 12 11 10 9 8 LB9 LA9 LB8 LA8 LB10 LB11 LA11 LA14 LB13 LA13 LB12 LA12 LB14 LB15 LA15 bit bit ELVR1 7 6 5 4 3 2 1 0 Address 0000CE H INT15R INT14R INT13R INT12R INT...

Page 335: ...1 register is corresponding to INT8 INT9R INT10 INT11 INT12R INT13 INT14R and INT15R DTP External Interrupt Factor Register EIRR1 Figure 17 3 2 DTP External Interrupt Factor Register EIRR1 R W X EIRR1 0000CBH XXXXXXXXB 12 13 11 10 9 8 14 15 R W R W R W R W R W R W R W R W bit15 to bit8 0 1 ER15 to ER8 ER15 ER14 ER13ER12 ER11ER10 ER9 ER8 DTP external interrupt request flag bit Read Write No DTP ext...

Page 336: ...t to 1 When the DTP external interrupt request enable bit ENIR1 EN is set to 1 an interrupt request is generated to the corresponding DTP external interrupt channel When set to 0 Cleared When set to 1 No effect Note Reading by read modify write type instructions always returns 1 If more than one DTP external interrupt request is enabled ENIR1 EN 1 clear only the bit in the channel that accepts an ...

Page 337: ... Write Reset value DTP external interrupt request enable bit DTP external interrupt enable DTP external interrupt disable Table 17 3 3 Functions of DTP External Interrupt Enable Register ENIR1 Bit Name Function bit0 to bit7 EN15 to EN8 ENIR1 DTP external interrupt request enable bits These bits enable or disable the DTP external interrupt request to the DTP external interrupt channel If the DTP ex...

Page 338: ...nal Interrupt Request Flag Bits and DTP External Interrupt Request Enable Bits DTP external interrupt pin DTP external interrupt request flag bit DTP external interrupt request enable bit INT8 ER8 EN8 INT9R ER9 EN9 INT10 ER10 EN10 INT11 ER11 EN11 INT12R ER12 EN12 INT13 ER13 EN13 INT14R ER14 EN14 INT15R ER15 EN15 ...

Page 339: ... LA15 LA14 LA13 LA12 LA11 LA10 LA9 LA8 LB14 LB13 LB12 LB11 LB10 LB9 LB8 Reset value Detection condition select bit Low level detection High level detection Rising edge detection Falling edge detection Address Read Write Reset value Table 17 3 5 Functions of Detection Level Setting Register ELVR1 Bit Name Function bit15 to bit0 ELVR1 LB15 LA15 to LB8 LA8 Detection condition select bits These bits s...

Page 340: ...6 Correspondence between Detection Level Setting Register and Channels DTP External Interrupt Pin Register Name Bit Name INT8 ELVR1 LB8 LA8 INT9R LB9 LA9 INT10 LB10 LA10 INT11 LB11 LA11 INT12R LB12 LA12 INT13 LB13 LA13 INT14R LB14 LA14 INT15R LB15 LA15 ...

Page 341: ...re 17 3 5 DTP external Interrupt Factor Select Register EISSR EISSR 0000CEH Address 4 5 3 2 1 0 bit7 to bit0 6 7 R W X R W R W R W R W R W R W R W R W 0 1 INT15R to INT8R 0 0 0 0 0 0 0 0 B INT15R INT14RINT13R INT12R INT11RINT10R INT9R INT8R Reset value External interrupt factor select bit Read Write Undefined Reset value Set pins INT15 to INT8 as external interrupt factor Set pins INT15R to INT8R ...

Page 342: ...ternal Interrupt Factor Select Upper 8 bit EISSR Bit 0 Initial Value 1 INT8R INT8 P54 AN12 TOT3 INT9R INT9R P42 RX1 INT10R INT10 P55 AN13 INT11R INT11 P56 AN14 INT12R INT12R P80 ADTG INT13R INT13 P57 AN15 INT14R INT14R P82 SIN0 TIN2 INT15R INT15R P84 SCK0 ...

Page 343: ...upt control register LB15 DDR port direction register bit15 14 13 12 11 10 9 bit8 bit7 6 5 4 3 2 1 bit0 Set 0 0 Set 1 1 Used bit Set the bit corresponding to used pin to 1 Set the bit corresponding to used pin to 0 Unused bit Set the bit corresponding to pin used for DTP external interrupt input to 0 0 At DTP EI2OS 1 1 LB12 LA12 LA14 LB13 LA13 LA15 LB14 ELVR1 LB8 LA8 LB9 LA9 LA10 LB11 LA11 LB10 MO...

Page 344: ... setting the registers for the DTP external interrupt the external interrupt request must be disabled in advance ENIR1 EN 0 When enabling the DTP external interrupt request ENIR1 EN 1 the corresponding DTP external interrupt request flag bit must be cleared in advance EIRR1 ER 0 These actions prevent the mistaken interrupt request from occurring when setting the register Selecting of DTP or extern...

Page 345: ... bit in the interrupt control register ICR ISE is set to 0 the interrupt processing is executed This bit is set to 1 the EI2 OS is executed Figure 17 4 2 shows the operation of the DTP external interrupt Table 17 4 1 Control Bits and Interrupt Factors for DTP External Interrupt DTP External interrupt Interrupt request flag bit EIRR1 ER15 to ER8 Interrupt request enable bit ENIR1 EN15 to EN8 Interr...

Page 346: ...op Recovery from DTP processing Memory Peripheral data transfer Renewal of descriptor Descriptor data counter Recovery from external interrupt DTP external interrupt request generating Interrupt controller reception judge CPU interrupt reception judge Interrupt processing microprogram starting External interrupt starting Processing and interrupt flag clear DTP external interrupt circuit Factor Oth...

Page 347: ...rrupt request is generated If the level of an interrupt request ICR IL is higher than that of the interrupt level mask bit in the condition code register CCR ILM and the interrupt enable bit is enabled PS CCR I 1 the CPU performs interrupt processing after completion of the current instruction execution and branches to interrupt processing At interrupt processing set the corresponding DTP external...

Page 348: ...s updated and the DTP external interrupt request flag bit is cleared to prepare for the next request from the DTP external interrupt pin When the EI2 OS completes transfer of all the data control branches to the interrupt processing Figure 17 4 3 Example of Interface with External Peripheral Device when using EI2 OS in Single chip mode CPU EI2OS DTP factor 1 INT 1 This must be cancelled within thr...

Page 349: ... inputted with level detection set in the detection level setting register factor F F in the DTP external interrupt factor register is set to 1 and the factor is held as shown in Figure 17 5 1 With the factor held in factor F F the request to the interrupt controller remains active if the interrupt request is enabled ENIR1 EN 1 even after the DTP external interrupt factor is cancelled To cancel th...

Page 350: ...l interrupt request set to enabled ENIR1 EN 1 Always set the DTP external interrupt request flag bit to 0 EIRR1 ER at interrupt processing When the level detection is set in the detection level setting register and the level that becomes the interrupt factor remains input the DTP external interrupt request flag bit is reset immediately even when cleared EIRR1 ER 0 Disable the DTP external interrup...

Page 351: ...er 1 L ELVR1H EQU 0000CDH Detection level setting register 1 H ADER5 EQU 00000BH Port5 analog input enable register ER8 EQU EIRR1 0 INT8 Interrupt request flag bit EN8 EQU ENIR1 0 INT8 Interrupt request enable bit Main program CODE CSEG START Stack pointer SP already initialized MOV I ADER5 00000000B Set analog input of Port5 to disable MOV I DDR5 00000000B Set DDR5 to input port AND CCR 0BFH Inte...

Page 352: ...n register DDR5 EQU 000015H Port 5 direction register ENIR1 EQU 0000CAH DTP external interrupt enable register 1 EIRR1 EQU 0000CBH DTP external interrupt factor register 1 ELVR1L EQU 0000CCH Detection level setting register 1 L ELVR1H EQU 0000CDH Detection level setting register 1 H ADER5 EQU 00000BH Port5 analog input enable register ADER6 EQU 00000CH Port6 analog input enable register ER1 EQU EI...

Page 353: ...H Byte transfer buffer address 1 I O address fixed transfer from memory to I O MOV IOAL 00H Set port 0 as transfer destination MOV IOAH 00H address pointer MOV DCTL 0AH Set transfer count to 10 MOV DCTH 00H CLRB I EN8 INT8 disabled using ENIR1 MOV I ELVR1L 00000001B H level detection set for INT8 CLRB I ER8 INT8 interrupt request flag cleared using EIRR1 SETB I EN8 INT8 interrupt request enabled u...

Page 354: ...338 CHAPTER 17 DTP EXTERNAL INTERRUPTS 26 1AH DSL WARI ORG 00FFDCH Reset vector set DSL START DB 00H Set to single chip mode VECT ENDS END START ...

Page 355: ... bit A D converter 18 1 Overview of 8 10 bit A D Converter 18 2 Block Diagram of 8 10 bit A D Converter 18 3 Configuration of 8 10 bit A D Converter 18 4 Interrupt of 8 10 bit A D Converter 18 5 Explanation of Operation of 8 10 bit A D Converter 18 6 Precautions when Using 8 10 bit A D Converter ...

Page 356: ...Generates interrupt request by storing A D conversion results in A D data register Starts EI2 OS if interrupt request generated Use of the EI2 OS prevents data loss even at continuous A D conversion Selects start trigger from software trigger and external trigger falling edge When the machine clock frequency operates at 24 MHz and AVCC 4 5 V Conversion Modes of 8 10 bit A D Converter There are 3 c...

Page 357: ...ANE2 ANE1 ANS3 ANE3 ANE0 AVR AVcc AVss AN0 to AN7 AN15 to AN8 ADTG D9 D8 D5 D6 D4 D3 D2 D1 D0 D7 ST0 ST1 CT1 ST2 CT2 CT0 S10 2 8 2 3 3 Undefined Reserved Always set to 0 Machine clock Re served Re served A D setting register ADSR0 ADSR1 Decoder A D data register ADCR0 ADCR1 D A converter Internal data bus Control circuit Comparator Sample hold circuit Analog channel selector Pin Starting selector ...

Page 358: ...re set Start selector This selector selects the trigger to start A D conversion An external pin input can be set as the start trigger Decoder This decoder sets the A D conversion start channel select bits and the A D conversion end channel select bits in the A D control status register ADSR0 ANS3 to ANS0 and ANE3 to ANE0 to select the analog input pin to be used for A D conversion Table 18 2 1 Pin...

Page 359: ...n of the input voltage during A D conversion D A converter This converter generates the reference voltage which is compared with the input voltage held in the sample hold circuit Comparator This comparator compares the D A converter output voltage with input voltage held in the sample hold circuit to determine the amount of voltage Controller This circuit determines the A D conversion value by rec...

Page 360: ... ports analog inputs Enable input of analog signal ADER6 set the corresponding bit of ADE7 to ADE0 to 1 Channel 1 P61 AN1 Channel 2 P62 AN2 Channel 3 P63 AN3 Channel 4 P64 AN4 Channel 5 P65 AN5 Channel 6 P66 AN6 PPGC D General purpose I O ports analog inputs PPG output Channel 7 P67 AN7 PPGE F General purpose I O ports analog inputs PPG output Channel 8 P50 AN8 General purpose I O ports analog inp...

Page 361: ... STRT ADCS1 R W R W R W R W R W R W W 7 5 4 3 2 1 0 MD1 MD0 S10 ADCS0 R W R W R W R W ANS2 ANS1 ANS0 ANE2 ANE1 ANE3 ANE0 R W R W R W R W R W R W R W R W 6 Address 000068H A D control status register Low Data register High 15 14 13 12 11 10 9 8 Address 00006BH D9 D8 ADCR1 7 6 5 4 3 2 1 0 Address 00006AH D7 D6 D5 D4 D3 D2 D1 D0 ADCR0 R R R R R R R R R R A D setting register High 15 14 13 12 11 10 9 ...

Page 362: ...ing bit bit9 Read value is always 1 Undefined bit STS1 0 0 1 1 Starting software Starting software or external trigger Starting software Starting software or external trigger A D conversion starting trigger select bit bit11 0 1 PAUS Suspended flag bit This bit is enabled only when EI2 OS is used bit12 INTE 0 1 Interrupt request disable Interrupt request enable Interrupt request enable bit bit13 W ...

Page 363: ...stop BUSY 0 and the activation of the A D converter concurrently using software STRT 1 exter nal trigger or timer bit14 INT Interrupt request flag bit This bit indicates that an interrupt request is generated When A D conversion is terminated and its results are stored in the A D data register ADCR0 1 the INT bit is set to 1 When the interrupt request flag bit is set INT 1 with an interrupt reques...

Page 364: ...art 01B External pin trigger or software start 10B Software start 11B External pin trigger or software start Note When the falling edge is detected in the ADTG pin at selected external terminal trigger 01B 11B the A D conversion is begun If two or more start triggers are set other than STS1 STS0 00B 10B the 8 10 bit A D converter is started by the first generated start trigger Start trigger settin...

Page 365: ... 7 X R W R W R W R W Reserved bit bit0 Resolution select bit bit5 MD1 0 0 1 1 A D conversion mode select bit bit7 MD0 0 1 0 1 bit6 Single shot conversion mode 1 restartable during conversion Single shot conversion mode 2 not restartable during conversion Continuous conversion mode not restartable during conversion Pause conversion mode not restartable during conversion S10 0 MD1 MD0 S10 Re served ...

Page 366: ...on mode A D conversion for the start channel ADSR0 ANS3 to ANS0 starts The A D conversion pauses at termination of A D conversion for a channel When the start trigger is inputted while A D conversion pauses A D conversion for the next channel is started The A D conversion pauses at the termination of A D conversion for the end channel When the start trigger is inputted while A D conversion pauses ...

Page 367: ... 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 D9 D8 Reset value Reset value Data register High Address Data register Low Address Read only Undefined bit Indeterminate Table 18 3 4 Functions of A D Data Register ADCR0 ADCR1 Bit Name Function bit15 to bit10 Undefined bits 1 is always read at reading bit9 to bit0 D9 to D0 A D conversion data bits These bits store the A D conversion results When resolution set in ...

Page 368: ... φ 16 MHz 8 25 µs 176 φ φ 20 MHz 8 8 µs 264 φ φ 24 MHz 11 0 µs 4 φ φ 8 MHz 0 5 µs 6 φ φ 8 MHz 0 75 µs 8 φ φ 16 MHz 0 5 µs 12 φ φ 24 MHz 0 5 µs 24 φ φ 8 MHz 3 0 µs 36 φ φ 16 MHz 2 25 µs 48 φ φ 16 MHz 3 0 µs 128 φ φ 24 MHz 5 3 µs CT0 00006CH Address Reset value 0000000000000000B 4 5 3 2 1 0 6 7 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W ANE3 to ANE0 A D conversion end channel se...

Page 369: ... before A D conversion starts the previous conversion channel will be read even if these bits have already been set to the new value These bits are initialized to 0000B at reset Start channel end channel A D conversion starts at channel set by A D conversion start channel select bits ANS3 to ANS0 and terminates channel set by A D conversion end channel select bits ANE3 to ANE0 Start channel end ch...

Page 370: ...d terminates channel set by A D conversion end channel select bits ANE3 to ANE0 Start channel end channel A D conversion is performed only for one channel set by A D converter start end channel select bits ANE3 to ANE0 ANS3 to ANS0 Start channel end channel Do not set Continuous conversion mode and pause conversion mode When A D conversion terminated at the channel set by the A D conversion end ch...

Page 371: ...ts The comparing time must be set according to the analog power supply voltage AVCC If the following condition is not met the conversion accuracy will not be guaranteed 4 5 V AVCC 5 5 V The comparing time must be set greater than 1 00 µs 4 0 V AVCC 4 5 V The comparing time must be set greater than 2 00 µs Table 18 3 7 Relation between CT2 to CT0 Bits and Comparing Time CT2 CT1 CT0 Setting of compa...

Page 372: ... AN7 to AN0 Reset value 11111111B Address ADER6 00000CH 4 5 3 2 1 0 bit7 to bit0 R W ADE0 ADE1 ADE2 ADE3 ADE4 ADE5 ADE6 ADE7 R W R W R W R W R W R W R W 6 7 12 13 11 10 9 8 14 15 Read Write Reset value Table 18 3 8 Functions of Port 5 Analog Input Enable Register ADER5 Bit Name Function bit15 to bit8 ADE15 to ADE8 Analog input enable bits 15 to 8 These bits enable or disable the analog input pin A...

Page 373: ... to be used and set to the analog input Setting the analog input pin to ADERx 0 is disabled Always set it to ADERx 1 Each analog input pin serves as the general purpose I O port and I O of peripheral function The pin set to ADERx 1 is forcibly set to the analog input pin regardless of the port direction register DDR5 DDR6 and the I O setting of each peripheral function ...

Page 374: ...the interrupt request flag bit is set ADCS INT 1 with an interrupt request output enabled ADCS INTE 1 an interrupt request is generated 8 10 bit A D Converter Interrupt and EI2 OS EI2 OS Function of 8 10 bit A D Converter In the 8 10 bit A D converter the EI2 OS function can be used to transfer the A D conversion results from the A D data register ADCR to memory If the EI2 OS function is used the ...

Page 375: ... restarted during A D conversion Continuous Conversion Mode ADCS MD1 MD0 10B When the start trigger is inputted the analog inputs from the start channel ADCS ANS3 to ANS0 to the end channel ADCS ANE3 to ANE0 are A D converted continuously When A D conversion for the end channel is terminated it is continued after returning to the analog input for the start channel To terminate A D conversion forci...

Page 376: ...ngle shot conversion mode requires the setting shown in Figure 18 5 1 Figure 18 5 1 Setting of Single shot Conversion Mode PAUS STS1 STRT Re served STS0 BUSY INT INTE ADCS 0 0 MD1 S10 MD0 D9 to D0 Converted data stored CT1 CT2 CT0 ST1 ST2 ST0 ADCR ADER5 bit15 14 13 12 11 10 9 bit8 bit7 6 5 4 3 2 1 bit0 ADSR ANS1 ANS0 ANE1 ANE0 ANE2 ANE3 ANS2 ANS3 ADER6 ADE15ADE14ADE13ADE12ADE11ADE10 ADE9 ADE8 ADE7...

Page 377: ...SY When the A D conversion mode select bits MD1 MD0 are set to 00B this mode can be restarted during A D conversion If the bits are set to 01B this mode cannot be restarted during A D conversion When start and end channels are the same If the start and end channels have the same channel number ADCS ANS3 to ANS0 ADCS ANE3 to ANE0 only one A D conversion for one channel set as the start channel end ...

Page 378: ...he continuous conversion mode requires the setting shown in Figure 18 5 2 Figure 18 5 2 Setting of Continuous Conversion Mode PAUS STS1 STRT STS0 BUSY INT INTE ADCS 1 0 0 MD1 S10 MD0 CT1 CT2 CT0 ST1 ST2 ST0 ADCR ADER5 bit15 14 13 12 11 10 9 bit8 bit7 6 5 4 3 2 1 bit0 ADSR ANS1 ANS0 ANE1 ANE0 ANE2 ANE3 ANS2 ANS3 ADER6 ADE15ADE14ADE13ADE12ADE11ADE10 ADE9 ADE8 ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0 ...

Page 379: ...erminate A D conversion forcibly write 0 to the A D conversion on flag bit in the A D control status register ADCS BUSY This mode cannot be restarted during A D conversion When start and end channels are the same If the start and end channels have the same channel number ADCS ANS3 to ANS0 ADCS ANE3 to ANE0 A D conversion for one channel set as the start channel end channel is repeated Conversion o...

Page 380: ...he 8 10 bit A D converter in the pause conversion mode requires the setting shown in Figure 18 5 3 Figure 18 5 3 Setting of Pause conversion Mode PAUS STS1 STRT STS0 BUSY INT INTE ADCS 1 1 0 MD1 S10 MD0 CT1 CT2 CT0 ST1 ST2 ST0 ADCR ADER5 bit15 14 13 12 11 10 9 bit8 bit7 6 5 4 3 2 1 bit0 ADSR ANS1 ANS0 ANE1 ANE0 ANE2 ANE3 ANS2 ANS3 ADER6 ADE15ADE14ADE13ADE12ADE11ADE10 ADE9 ADE8 ADE7 ADE6 ADE5 ADE4 ...

Page 381: ...e A D conversion pauses input the start trigger set by the A D start trigger select bits in the A D control status register ADCS STS1 STS0 To terminate A D conversion forcibly write 0 to the A D conversion on flag bit in the A D control status register ADCS BUSY This mode cannot be restarted during A D conversion When start and end channels are the same If the start and end channels have the same ...

Page 382: ...ltiple data to memory without the loss of converted data even if A D conversion is performed continuously The conversion flow when the EI2 OS is used is shown in Figure 18 5 4 Figure 18 5 4 Flow of Conversion when Using EI2 OS A D converter starts Sample hold A D conversion starts A D conversion terminates Interrupt generated EI2OS starts Converted data transferred Interrupt processing Interrupt c...

Page 383: ...mmediately before new data is overwritten to the A D data register if the interrupt request is enabled ADCS INTE 1 while the interrupt request flag bit set at termination of previous A D conversion is set at the point that next A D conversion is terminated When the INT bit is set with an interrupt request from the A D control status register enabled ADCS INTE 1 an interrupt request is generated Wh...

Page 384: ...nversion ADCS INTE 0 A D conversion may be restarted to rewrite data being transferred The EI2 OS function is used to transfer the A D conversion results to memory do not restart Restarting during a pause of A D conversion may cause loss of the A D conversion results EI2 OS set A D continuous conversion starts First conversion terminates Data in A D data register stored Second conversion terminate...

Page 385: ...igger Set the level of the external trigger to inactive H for external trigger when the A D start trigger select bits in the A D control status register ADCS STS1 and STS0 is set the same way as starting the 8 10 bit A D converter by the external trigger Holding the input value for the start trigger active may cause the 8 10 bit A D converter to start the A D start trigger select bits in the A D c...

Page 386: ...370 CHAPTER 18 8 10 BIT A D CONVERTER ...

Page 387: ...MB90360 series 19 1 Overview of Low Voltage CPU Operating Detection Reset Circuit 19 2 Configuration of Low Voltage CPU Operating Detection Reset Circuit 19 3 Low Voltage CPU Operating Detection Reset Circuit Register 19 4 Operating of Low Voltage CPU Operating Detection Reset Circuit 19 5 Notes on Using Low Voltage CPU Operating Detection Reset Circuit 19 6 Sample Program for Low Voltage CPU Oper...

Page 388: ...ime after 20 bit counter start that makes the oscillation clock a count clock CPU operating detection reset circuit generates internal reset Low Voltage Detection Reset Circuit Figure 19 1 1 Detection Voltage of Low Voltage CPU operating Detection Reset Circuit After detecting the low voltage low voltage detection flag LVRC LVRF is set to 1 and internal reset is outputted After the low voltage is ...

Page 389: ...e fixed time by an program infinite loop etc The width of internal reset generated by CPU operating detection circuit is five machine cycles Figure 19 1 2 Interval Time of CPU operating Detection Reset Circuit In the mode that CPU stops operating the circuit stops The counter condition of CPU operating detection reset circuit is indicated as follows 1 Writing 0 to CL bit of LVRC register 2 Interna...

Page 390: ...operating detection reset control register LVRC Block Diagram of Low Voltage CPU Operating Detection Reset Circuit Figure 19 2 1 Block Diagram of Low Voltage CPU operating Detection Reset Circuit VCC VSS Voltage comparison circuit Counter F F CPU operating detection circuit Oscillation clock Reserved Reserved Reserved Reserved CL LVRF Reserved CPUF Low voltage CPU operating detection reset control...

Page 391: ... after the low voltage detection After the power supply is turned on it always operates Low voltage CPU operating detection reset control register LVRC This register clears the low voltage CPU operating detection reset flag and the counter of CPU operating detection function Reset factor of low voltage CPU operating detection reset circuit After power supply voltages is fallen more than the detect...

Page 392: ...tection flag bit CPUF Read Write 0 No overflow Clear CPUF bit 1 Overflow No change No other effect Low voltage detection flag bit LVRF Read Write 0 No detect voltage falling Clear LVRF bit 1 Detect voltage falling No change No other effect CL CPU operating detection circuit clear bit 0 Counter clear 1 No change No other effect Reserved Reserved bit This bit should write 1 Reserved Reserved bit Thi...

Page 393: ...ction circuit is cleared bit2 LVRF Low voltage detection flag bit When falling of the power supply voltage is detected the LVRF bit is set to 1 This bit is cleared by 0 at write And even if 1 is written in this bit the LVRF bit is no effect This bit is not initialized in internal reset and it is initialized only by the external reset input bit1 Reserved Reserved bit Note This bit should write 0 bi...

Page 394: ...r is not guaranteed The program restarts from the address specified by the reset vector after the reset sequence is executed when the low voltage reset is canceled Operating of Low Voltage CPU Operating Detection Reset Circuit The low voltage detection reset circuit starts the detection of the low voltage without taking the operating stability wait time after reset is canceled Operating of CPU Ope...

Page 395: ...e STOP mode reset is generated and the STOP mode is canceled Notes on Using CPU Operating Detection Reset Circuit Disabled operating stop from program CPU operating detection reset circuit operates continuously after turning on the power supply Operating cannot be stopped with software Reset generation control of CPU operating detecting function CPU operating detecting function should clear the co...

Page 396: ...e program for low voltage CPU operating detection reset circuit Sample Program for Low Voltage CPU Operating Detection Reset Circuit Processing specification The counter of CPU operating detecting function is cleared Coding example LVRC EQU 006EH Address of low voltage CPU operating detection reset control register Main program CSEG CODE SEGMENT MOV LVRC 00110101B END ...

Page 397: ... the functions and operation of LIN UART 20 1 Overview of LIN UART 20 2 Configuration of LIN UART 20 3 LIN UART Pins 20 4 LIN UART Registers 20 5 LIN UART Interrupts 20 6 LIN UART Baud Rates 20 7 Operation of LIN UART 20 8 Notes on Using LIN UART ...

Page 398: ... Synchronous to clock selecting start stop synchronous or start stop bit Asynchronous start stop bits can be used Baud rate Dedicated baud rate generator The baud rate is consisted of 15 bit reload counter An external clock can be inputted and also be adjusted by reload counter Data length 7 bits other than synchronous or LIN mode 8 bits Signal type NRZ Non Return to Zero Start bit timing Synchron...

Page 399: ...ion of start stop edges in LIN Synch field connected to input capture 0 and 1 Synchronous serial clock Synchronous serial clock can be continuously outputted to SCK pin for synchronous communication with start stop bits Clock delay option Special synchronous clock mode for delaying clock useful to SPI Table 20 1 1 LIN UART Functions 2 2 Function ...

Page 400: ...s locked to 8N1 Format LSB first If the mode is changed LIN UART cuts off all possible transmission or reception and awaits then new action Table 20 1 2 Operation Mode of LIN UART Operation Mode Data Length Synchronous Asynchronous Length of Stop Bit Data Bit Format No Parity With Parity 0 Normal mode 7 or 8 bits Asynchronous 1 bit or 2 bits LSB first MSB first 1 Multiprocessor mode 7 or 8 bits 1 ...

Page 401: ...2 0000BCH FFFF6CH FFFF6DH FFFF6EH 2 LIN UART1 reception 37 25H ICR13 0000BDH FFFF68H FFFF69H FFFF6AH 1 LIN UART1 transmission 38 26H ICR13 0000BDH FFFF64H FFFF65H FFFF66H 2 1 EI2 OS service is usable if the other interrupt s which shares the ICR12 to ICRB and same interrupt vector is are not enabled Detection of receive errors is possible and stop function for EI2 OS service is supported 2 EI2 OS ...

Page 402: ...eption Data Register RDR Transmission Control Circuit Transmission Shift Register Transmission Data Register TDR Error Detection Circuit Oversampling circuit Interrupt Generation Circuit LIN Synch Break Synch Field Detection Circuit LIN Synch Break Generation Circuit Bus Idle Detection Circuit LIN UART Serial Mode Register SMR Serial Control Register SCR Serial Status Register SSR Extended Com Con...

Page 403: ...LBR LBL1 LBL0 LBL1 LBL0 Internal data bus Reload counter Restart reception reload counter Over sampling unit Pin Pin Transmission clock Reception clock Reception control circuit Start bit detection circuit Received bit counter Received parity counter Transmission start circuit Transmission bit counter Transmission parity counter Transmission control circuit Interrupt generation circuit Reception T...

Page 404: ...g the data bit by bit When reception is completed the reception shift register transfers receive data to the RDR register Reception Data Register RDR This register retains reception data Serial input data is converted and stored in this register Transmission Control Circuit The transmission control circuit consists of a transmission bit counter transmission start circuit and transmission parity co...

Page 405: ...f the LIN synchronization field is recognized by this circuit by generating an internal signal for the Input Capture Unit to measure the actual serial clock synchronization of the transmitting master node LIN Synch Break Generation Circuit The LIN break generation circuit generates a LIN synch break of a determined length Bus Idle Detection circuit The bus idle detection circuit recognizes if neit...

Page 406: ... transmit operations and errors Specifying LSB first or MSB first Receive interrupt enable disable Transmit interrupt enable disable Extended Communication Control Register ECCR This register performs the following functions Indicating bus idle detection Specifying synchronous clock Specifying LIN synch break generation Extended Status Control Register ESCR This register performs the following fun...

Page 407: ...tomotive input Provided Set as input port DDR corresponding bit 0 P83 SOT0 P86 SOT1 Port I O or serial data output Set to output enable mode SMRn SOE 1 P84 SCK0 P87 SCK1 Port I O or serial clock input output Set as an input port when a clock is inputted DDR corresponding bit 0 Set to output enable mode when a clock is outputted SMRn SCKE 1 Pch Nch Pin Port data register PDR Resource input Resource...

Page 408: ...024H ESCR0 Extended status control register ECCR0 Extended communication control register 000027H 000026H BGR01 Baud rate generator register BGR00 Baud rate generator register LIN UART1 Address bit 15 bit 8 bit 7 bit 0 000029H 000028H SCR1 serial control register SMR1 serial mode register 00002BH 00002AH SSR1 serial status register RDR1 TDR1 reception data register transmission data register 00002...

Page 409: ... R W R W R W W R W bit8 TXE Transmission operation enable bit 0 Disable transmission 1 Enable transmission bit9 RXE Reception operation enable bit 0 Disable reception 1 Enable reception bit10 CRE Clear reception error flag bit Write Read 0 No effect Read always returns 0 1 Clear all reception error flags PE FRE ORE bit11 AD Address data format select bit 0 Data frame 1 Address frame bit12 CL Data ...

Page 410: ... reading from it for slave CPU A 1 indicates an address data frame a 0 indicates a usual data frame The reading value is a value of last received data format Note Please read the hints about using this bit in 20 8 Notes on Using LIN UART bit10 CRE Clear reception error flag bit This bit clears the FRE ORE and PE flags of the Serial Status Register SSR Writing a 1 to it clears the error flag Writin...

Page 411: ...of LIN UART bit1 SCKE LIN UART serial clock output enable bit 0 General purpose I O port or LIN UART clock input pin 1 Serial clock output pin of LIN UART bit2 UPCL LIN UART programmable clear bit write read 0 Ignored always read 0 1 Reset LIN UART bit3 REST Restart dedicated Reload Counter bit write read 0 Ignored always read 0 1 Restart Counter bit4 EXT External Serial Clock Source select bit 0 ...

Page 412: ... RDRF LBD PE ORE FRE are cleared Reset the LIN UART after disabling the interrupt and transmission Also when the reception data register is cleared RDR 00H the reload counter restarts Writing 0 to this bit has no effect Reading from it always returns 0 bit1 SCKE LIN UART serial clock output enable bit This bit controls the serial clock I O ports When this bit is 0 SCKn pin operates as general purp...

Page 413: ...nables transmission interrupt bit9 RIE Reception interrupt request enable bit 0 Disables reception interrupt 1 Enables reception interrupt bit10 BDS Transfer direction selection bit 0 LSB first transfer from lowest bit 1 MSB first transfer from highest bit bit11 TDRE Transmission data empty flag bit 0 Transmission data register is full 1 Transmission data register is empty bit12 RDRF Reception dat...

Page 414: ...e RIE bit are 1 bit11 TDRE Transmission data empty flag bit This flag indicates the status of the transmission data register TDR This bit is cleared to 0 when transmission data is written to TDR and indicates that valid data exists in TDR This bit is set to 1 when data is loaded into the transmission shift register and transmission start and indicates that no valid data exists in TDR A transmissio...

Page 415: ...D7 contains 0 When the data is stored in this register and the reception data full flag bit SSR RDRF is set to 1 If a reception interrupt request is enabled SSR RIE 1 at this point a reception interrupt occurs Read RDR when the RDRF bit of the serial status register SSR is 1 The RDRF bit is cleared automatically to 0 when RDR is read Also the reception interrupt is cleared if it is enabled and no ...

Page 416: ...sion data empty flag bit SSR TDRE is cleared to 0 When transfer to the transmission shift register is completed and transmission starts the bit is set to 1 When the TDRE bit is 1 the next part of transmission data can be written If transmission interrupt requests have been enabled a transmission interrupt is generated Write the next part of transmission data when a transmission interrupt is genera...

Page 417: ...ing on falling clock edge inverted clock bit 9 CCO Continuous Clock Output Enable Bit Mode 2 0 Continuous Clock Output disabled 1 Continuous Clock Output enabled bit 10 SIOP Serial Input Output Pin Access write SOPE 1 read 0 SOTn pin is forced to 0 Reading the actual value of SINn pin 1 SOTn pin is forced to 1 bit 11 SOPE Serial Output pin direct Access Enable Bit 0 Serial Output pin direct access...

Page 418: ... to 1 enables the direct write to the SOTn pin if SOE 1 SMR bit10 SIOP Serial Input Output Pin direct access bit Normal read instructions always return the actual value of the SINn pin Writing to it sets the bit value to the SOTn pin if SOPE 1 During a Read Modify Write instruction the bit returns the SOTn value in the read cycle bit9 CCO Continuous Clock Output enable bit This bit enables a conti...

Page 419: ...it 0 TBI Transmission bus idle detection flag bit 0 Transmission is ongoing 1 No transmission activity bit1 RBI Reception bus idle detection flag bit 0 Reception is ongoing 1 No reception activity bit 2 Unused bit Reading value is undefined Always write 0 bit 3 SSM Start stop bit mode enable bit in mode 2 0 No start stop bit 1 Enable start stop bit bit 4 SCDE Serial Clock Delay enable bit in mode ...

Page 420: ...slave mode is selected the clock source must be external and enabled the external clock input SMR SCKE 0 EXT 1 OTO 1 bit4 SCDE Serial clock delay enable bit in mode 2 If this bit is set to 1 the serial output clock is delayed as shown in Figure 20 7 5 if LIN UART operates in master mode 2 This bit is enabled to SPI This bit is fixed to 0 in operation mode 0 1 and 3 bit3 SSM Start Stop bit mode ena...

Page 421: ...unter value are allowed Also byte and word access are enabled When writing the reload value to the baud rate generator register the reload counter starts counting bit15 bit14 bit13 bit12 bit11 bit10 bit9 0 0 0 0 0 0 0 0 B BGR00 000026H BGR01 000027H BGR10 00002EH BGR11 00002FH R bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0 0 0 0 0 0 0 B R W R W R WR W R W R W R W R W R W R W R W R W R W R W R ...

Page 422: ...of the LIN UART Table 20 5 1 Interrupt Control Bits and Interrupt Cause of LIN UART Reception transmission ICU Interrupt request flag bit Flag register Operation mode Interrupt cause Interrupt cause enable bit How to clear the interrupt request 0 1 2 3 Reception RDRF SSR Receive data is written to RDR SSR RIE Receive data is read ORE SSR Overrun error 1 is written to clear reception error flag bit...

Page 423: ...d from the transmission data register TDR to the transfer shift register and transfer is started the transmission data empty flag bit TDRE of the serial status register SSR is set to 1 In this case an interrupt request is generated if the transmission interrupt enable TIE bit of the SSR was set to 1 before Note The initial value of TDRE after hardware or software reset is 1 So an interrupt is gene...

Page 424: ...ception EI2 OS can be used if other interrupt is not enabled because the UART shares the interrupt control registers with transmission interrupt and other UART For Transmission LIN UART shares the interrupt control registers with the LIN UART reception interrupts and other UART Therefore EI2 OS can be started up only when no LIN UART reception interrupts are used Table 20 5 2 LIN UART Interrupts a...

Page 425: ...nabled SSR RIE 1 reception interrupt occurs Note If a reception error has occurred the Reception Data Register RDR contains invalid data in each mode Figure 20 5 1 shows the reception operation and flag set timing Figure 20 5 1 Reception Operation and Flag Set Timing Note The example in Figure 20 5 1 does not show all possible reception options for mode 0 Here it is 7p1 and 8N1 p E even or O odd R...

Page 426: ...410 CHAPTER 20 LIN UART Figure 20 5 2 ORE Flag Set Timing RDRF ORE Reception data ...

Page 427: ...an be cleared to 0 by writing data into TDR The following figure demonstrates the transmission operation and flag set timing for the four modes of LIN UART Figure 20 5 3 Transmission Operation and Flag Set Timing Note The example in Figure 20 5 3 does not show all possible transmission options for mode 0 Here it is 8p1 p E even or O odd Parity is not provided in mode 3 or 2 if SSM 0 TDRE TDRE ST D...

Page 428: ...mission interrupt is generated Note A transmission interrupt is generated immediately after the transmission interrupt is enabled SSR TIE 1 because the TDRE bit is set to 1 as its initial value TDRE is a read only bit that can be cleared only by writing new data to the transmission data register TDR Carefully specify the transmission interrupt enable timing ...

Page 429: ...onous master mode Internal clock and baud rate generator clock is selected for the setting of clock source SMR EXT 0 OTO 0 Baud rates determined using the dedicated baud rate generator reload counter with external clock An external clock source can also be connected internally to the reload counter The baud rate can be selected via the 15 bit reload value determined by the baud rate generator regi...

Page 430: ...14 D8 D13 D12 D11 D10 D9 D6 D7 D4 D5 D2 D3 D0 D1 Reload Value v Reception 15 bit Reload Counter Transmission 15 bit Reload Counter Reload Value v Count Value TXC Reload Reload Reset Start bit falling edge detection Reception clock Transmission clock SCKn external clock input Reset Reset Set Set Internal data bus SMRn register BGRn1 register BGRn0 register ...

Page 431: ...e machine clock b the baud rate and gaussian brackets mathematical rounding function Example of calculation If the machine clock is 16 MHz and the desired baud rate is 19200 bps baud then the reload value v is v 16 106 19200 1 832 The exact baud rate can then be recalculated bexact Φ v 1 here it is 16 106 833 19207 6831 Note Setting the reload value to 0 stops the reload counter For this reason th...

Page 432: ...400 103 0 16 153600 51 0 16 64 0 16 103 0 16 129 0 16 155 0 16 125000 63 0 79 0 127 0 159 0 191 0 115200 68 0 64 86 0 22 138 0 08 173 0 22 207 0 16 76800 103 0 16 129 0 16 207 0 16 259 0 16 311 0 16 57600 138 0 08 173 0 22 277 0 08 346 0 06 416 0 08 38400 207 0 16 259 0 16 416 0 08 520 0 03 624 0 28800 277 0 08 346 0 01 554 0 01 693 0 06 832 0 03 19200 416 0 08 520 0 03 832 0 03 1041 0 03 1249 0 1...

Page 433: ...mode 2 operating as slave device Note In any case the resulting clock signal is synchronized to the internal clock in the LIN UART module This means that indivisible clock rates will result in phase unstable signals Counting Example Assume the reload value is 832 Figure 20 6 2 demonstrates the behavior of both Reload Counters Figure 20 6 2 Counting Example of the Reload Counters Note The falling e...

Page 434: ...ansmission reload counter can be read by the baud rate generator register BGR1 BGR0 Count start When the reload value is written to the baud rate generator register BGR1 BGR0 the reload counter starts counting Restart If the REST bit of the Serial Mode Register SMR is set to 1 both Reload Counters are restarted at the next clock cycle This feature is intended to use the Transmission Reload Counter...

Page 435: ...egister to the incoming serial data stream Clearing reload counters The reload value of the baud rate generator register BGR1 BGR0 and the reload counters are cleared to 00 by the MCU global reset and the counters stops The reload counters are cleared to 00H by writing 1 to the UPCL bit in the SMR register However the value stored in the reload register is kept unchanged and the counters restart f...

Page 436: ...ion of LIN UART in a master slave connection system In Mode 3 the LIN UART function is locked to 8N1 Format LSB first If the mode is changed LIN UART cuts off all possible transmission or reception and awaits then new action Table 20 7 1 Operation Mode of LIN UART Operation mode Data length Synchronization of mode Length of stop bit Data bit format Parity disabled Parity enabled 0 Normal mode 7 or...

Page 437: ... Methods In asynchronous operation LIN UART reception clock is automatically synchronized to the falling edge of a received start bit In synchronous mode the synchronization is performed either by the clock signal of the master device or by LIN UART itself if operating as master Signal Mode LIN UART can treat data only in non return to zero NRZ format Operation Enable Bit LIN UART controls both tr...

Page 438: ...MSB first is determined by the BDS bit of the Serial Status Register SSR The parity bit if enabled is always placed between the last data bit and the first stop bit In operation mode 0 the length of the data frame can be 7 or 8 bits with or without parity and 1 or 2 stop bits In operation mode 1 the length of the data frame can be 7 or 8 bits with a following address data selection bit instead of ...

Page 439: ...D6 D7 SP SP ST D0 D1 D2 D3 D4 D5 D6 D7 P SP ST D0 D1 D2 D3 D4 D5 D6 SP SP ST D0 D1 D2 D3 D4 D5 D6 P SP ST D0 D1 D2 D3 D4 D5 D6 SP SP ST D0 D1 D2 D3 D4 D5 D6 P SP ST D0 D1 D2 D3 D4 D5 D6 D7 AD SP ST D0 D1 D2 D3 D4 D5 D6 AD SP ST D0 D1 D2 D3 D4 D5 D6 D7 AD ST D0 D1 D2 D3 D4 D5 D6 AD SP SP SP SP Operation mode 0 ST Start bit SP Stop mode P Parity bit AD Address data bit Without parity 8 bit data 7 bi...

Page 440: ... when it is enabled by the Reception Enable RXE flag bit of the SCR If a start bit is detected a data frame is received according to the data format specified by the SCR In case of errors the corresponding error flags are set SSR PE ORE FRE After the reception of the data frame the data is transferred from the reception shift register to the Reception Data Register RDR and the Receive Data Registe...

Page 441: ...smission or detect reception the parity bit The parity enable bit SCR PEN is used to specify whether there is parity or not and parity selection bit SCR P is selected the even odd parity In operation mode 1 the parity cannot be used Figure 20 7 2 Transmission Data when Parity Enabled Data signal type The data signal type is NRZ data format Data transition method The data bit transfer method can be...

Page 442: ...s set to 1 the serial clock is inverted Therefore in slave mode LIN UART samples the data bits at the falling edge of the received serial clock Note that in master mode if SCES is set to 1 the clock signal s mark level is 0 Figure 20 7 4 Transfer Data Format with Clock Inversion Start stop bits If the SSM bit of the Extended Communication Control Register ECCR is set to 1 the data format gets addi...

Page 443: ... or falling edge of the serial clock signal for the data sampling Figure 20 7 5 Delayed Transmitting Clock Signal SCDE 1 If the SCES bit of the ESCR register is 1 the serial clock signal is inverted Receiving data is sampled at the falling edge of the serial clock In this case the serial data must be valid value at the falling edge of the clock If the CCO bit of ESCR register is 1 master mode the ...

Page 444: ... if parity bit is added detected 0 if not P 0 for even parity 1 odd parity SBL 1 for 2 stop bits 0 for 1 stop bit Serial status register SSR BDS 0 for LSB first 1 for MSB first RIE 1 if reception interrupts are used 0 reception interrupts are disabled TIE 1 if transmission interrupts are used 0 transmission interrupts are disabled Extended communication control register ECCR SSM 0 if no start stop...

Page 445: ...sion interrupt the 0x55 can be written to the TDR just after writing the 1 to the LBR bit although the TDRE flag is 0 LIN UART as LIN slave In LIN slave mode LIN UART has to synchronize to the master s baud rate If Reception is disabled RXE 0 but LIN break interrupt is enabled LBIE 1 LIN UART will generate a reception interrupt if a synchronization break from the LIN master is detected and indicat...

Page 446: ...This causes an interrupt if the LIN Break Interrupt Enable LBIE bit is set to 1 Figure 20 7 7 LIN Synch Break Detection and Flag Set Timing The figure above demonstrates the LIN synch break detection and flag set timing Note that if reception is enabled RXE 1 and reception interrupt is enabled RIE 1 the Reception Data Framing Error FRE flag bit of the SSR will cause a reception interrupt 2 bit tim...

Page 447: ...bus RXE LBD IRQ0 RDRF IRQ ICU IRQ ICU SIN IRQ0 IRQ ICU LIN LBIE RIE No clock used calibration frame Old serial clock New calibrated serial clock ICU count Reception inter rupt enable LIN break begins LIN break detected and Interrupt IRQ cleared by CPU LBD 0 IRQ cleared Begin of ICU IRQ cleared Calculate set new baud rate LBIE disable Reception enable Falling edge of start bit Store one byte of rec...

Page 448: ...the SIOP bit of the ESCR register the SOTn value can be set arbitrarily In LIN mode this function can be used for reading back the own transmission and is used for error handling if something is physically wrong with the single wire LIN bus Notes Direct access is enabled only when the transmission is not ongoing transmission shift register is empty Write a value to the SIOP bit of ESCR register be...

Page 449: ...terconnect two CPUs in LIN UART mode 2 Figure 20 7 11 Connection Example of LIN UART Mode 2 Bidirectional Communication LBL1 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 PEN P SBL CL AD CRE RXE TXE MD1 MD0 OTO EXT REST UPCLSCKE SOE TDRE PE ORE FRE RDRF BDS RIE TIE Set conversion data during writing Retain reception data during reading LBIE L...

Page 450: ...12 shows an example of the bi directional communication flowchart Figure 20 7 12 Example of Master slave Communication Flowchart ANS NO NO YES YES Start Start Transmission side Reception side Operating mode setting either 0 or 2 Set 1 byte data to TDR and communicate With reception data Read reception data and process Operating mode setting match the transmission side Read reception data and proce...

Page 451: ...master CPU and multiple slave CPUs connected to two communication lines LIN UART can be used for the master or slave CPU Figure 20 7 14 Connection Example of LIN UART Master slave Communication bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 PEN P SBL CL AD CRE RXE TXE MD1 MD0 OTO EXT REST UPCL SCKE SOE PE ORE FRE RDRF TDRE BDS RIE TIE LBIE LBD...

Page 452: ...ram When the address data indicates the address assigned to a slave CPU the slave CPU communicates with the master CPU Figure 20 7 15 shows a flowchart of master slave communication multiprocessor mode Table 20 7 3 Selection of the Master slave Communication Function Operation mode Data Parity Synchron ization method Stop bit Bit direction Master CPU Slave CPU Address transmission and reception Mo...

Page 453: ...ial data input pin Set SOTn pin as the serial data output pin Set 7 or 8 data bits Set 1 or 2 stop bits Set 7 or 8 data bits Set 1 or 2 stop bits Set 1 in AD bit Transfer reception operation enabled Transfer reception operation enabled Send address to slave Receive byte AD bit 1 Set 0 in AD bit Communicate with slave CPU Iscommunication complete Communicate with another slave CPU Transfer receptio...

Page 454: ...w a communication system of one LIN Master device and a LIN Slave device LIN UART can operate both as LIN Master or LIN Slave Figure 20 7 17 Connection Example of a Small LIN Bus System LBIE LBD LBL1 LBL0 SOPE SIOP CCO SCES LBR MS SCDE SSM RBI TBI PEN P SBL CL AD CRE RXE TXE MD1 MD0 OTO EXT REST UPCL SCKE SOE PE ORE FRE RDRF TDRE BDS RIE TIE Set conversion data during writing Retain reception data...

Page 455: ...led Without error Error processing 2 Data Field reception Transmission data 1 set TDR Data 1 Transmission interrupt enabled Wake up 0x80 reception Synch field reception 1 Identify field set TDR lD RDRF 1 Reception interrupt RDRF 1 Reception interrupt Reception Transmission RDRF 1 Reception interrupt Data 1 reception 1 Data N reception 1 RDRF 1 Reception interrupt Transmission data N set TDR Data N...

Page 456: ...lag clear ICU interrupt ICU interrupt reception transmission RDRF 1 Reception interrupt Data 1 reception 1 Data N reception 1 RDRF 1 Reception interrupt Transmission data N set TDR Data N Transmission interrupt pro hibited Data 1 reception 1 Data 1 read Data N reception 1 Data N read Reception prohibited TDRE 1 Transmission interrupt RDRF 1 Reception interrupt RDRF 1 Reception interrupt 1 If an er...

Page 457: ... operation settings It is strongly recommended to reset LIN UART after changing operation settings Particularly if for example start stop bits added to or removed from the data format If settings in the serial mode register SMR are desired it is not useful to set the UPCL bit to 1 at the same time to reset LIN UART The correct operation settings are not guaranteed in this case Thus it is recommend...

Page 458: ...alue in the AD bit when one of the other bits in the same register is accessed by an instruction of this kind Therefore this bit should be written by the last register access before transmission Alternatively using byte wise access and writing the correct values for all bits at once avoids this problem Software reset of LIN UART Perform the software reset SMR UPCL 1 when the TXE bit of the SCR reg...

Page 459: ...sifying CAN Controller Registers 21 5 Transmission of CAN Controller 21 6 Reception of CAN Controller 21 7 Reception Flowchart of CAN Controller 21 8 How to Use CAN Controller 21 9 Procedure for Transmission by Message Buffer x 21 10 Procedure for Reception by Message Buffer x 21 11 Setting Configuration of Multi level Message Buffer 21 12 Setting the CAN Direct Mode Register 21 13 Precautions whe...

Page 460: ...orts transmission reception in standard frame and extended frame formats Supports transmitting of data frames by receiving remote frames 16 transmitting receiving message buffers 29 bit ID and 8 bytes data Multi level message buffer configuration Supports full bit comparison full bit mask and partial bit mask filtering Two acceptance mask registers in either standard frame format or extended frame...

Page 461: ...BLOST IDLE SUSPND transmit receive ERR OVRLD Output driver TX TBFx clear Transmitting buffer x decision TBFx TCANR TRTRR RFWTR TCR TIER RCR RIER RRTRR ROVRR AMSR AMR0 TBFx TBFx set clear Transmission complete interrupt generation Transmission complete interrupt Reception complete interrupt RBFx set Reception complete interrupt generation RBFx TBFx set clear RBFx set IDSEL 0 1 Acceptance filter Rec...

Page 462: ...Receive complete register RCR R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 000089H 00008AH Remote request receiving register RRTRR R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00008BH 00008CH Receive overrun register ROVRR R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00008DH 00008EH Receive interrupt enable register RIER R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00008FH 007D00H Control status register CSR R W R 0 0 XXX 0 0 0 0 XX...

Page 463: ...sk select register AMSR R W XXXXXXXX XXXXXXXX 007D11H 007D12H XXXXXXXX XXXXXXXX 007D13H 007D14H Acceptance mask register 0 AMR0 R W XXXXXXXX XXXXXXXX 007D15H 007D16H XXXXXXXX XXXXXXXX 007D17H 007D18H Acceptance mask register 1 AMR1 R W XXXXXXXX XXXXXXXX 007D19H 007D1AH XXXXXXXX XXXXXXXX 007D1BH Table 21 3 1 List of overall Control Register 2 2 Address Register Abbreviation Access Initial Value CAN...

Page 464: ...H ID register 1 IDR1 R W XXXXXXXX XXXXXXXX 007C25H 007C26H XXXXXXXX XXXXXXXX 007C27H 007C28H ID register 2 IDR2 R W XXXXXXXX XXXXXXXX 007C29H 007C2AH XXXXXXXX XXXXXXXX 007C2BH 007C2CH ID register 3 IDR3 R W XXXXXXXX XXXXXXXX 007C2DH 007C2EH XXXXXXXX XXXXXXXX 007C2FH 007C30H ID register 4 IDR4 R W XXXXXXXX XXXXXXXX 007C31H 007C32H XXXXXXXX XXXXXXXX 007C33H 007C34H ID register 5 IDR5 R W XXXXXXXX XX...

Page 465: ...07C4CH ID register 11 IDR11 R W XXXXXXXX XXXXXXXX 007C4DH 007C4EH XXXXXXXX XXXXXXXX 007C4FH 007C50H ID register 12 IDR12 R W XXXXXXXX XXXXXXXX 007C51H 007C52H XXXXXXXX XXXXXXXX 007C53H 007C54H ID register 13 IDR13 R W XXXXXXXX XXXXXXXX 007C55H 007C56H XXXXXXXX XXXXXXXX 007C57H 007C58H ID register 14 IDR14 R W XXXXXXXX XXXXXXXX 007C59H 007C5AH XXXXXXXX XXXXXXXX 007C5BH 007C5CH ID register 15 IDR15 ...

Page 466: ...007C68H DLC register 4 DLCR4 R W XXXXXXXX 007C69H 007C6AH DLC register 5 DLCR5 R W XXXXXXXX 007C6BH 007C6CH DLC register 6 DLCR6 R W XXXXXXXX 007C6DH 007C6EH DLC register 7 DLCR7 R W XXXXXXXX 007C6FH 007C70H DLC register 8 DLCR8 R W XXXXXXXX 007C71H 007C72H DLC register 9 DLCR9 R W XXXXXXXX 007C73H 007C74H DLC register 10 DLCR10 R W XXXXXXXX 007C75H 007C76H DLC register 11 DLCR11 R W XXXXXXXX 007C...

Page 467: ...W XXXXXXXX to XXXXXXXX 007CB0H to 007CB7H Data register 6 8 bytes DTR6 R W XXXXXXXX to XXXXXXXX 007CB8H to 007CBFH Data register 7 8 bytes DTR7 R W XXXXXXXX to XXXXXXXX 007CC0H to 007CC7H Data register 8 8 bytes DTR8 R W XXXXXXXX to XXXXXXXX 007CC8H to 007CCFH Data register 9 8 bytes DTR9 R W XXXXXXXX to XXXXXXXX 007CD0H to 007CD7H Data register 10 8 bytes DTR10 R W XXXXXXXX to XXXXXXXX 007CD8H to...

Page 468: ...ollowing 14 registers Message buffer valid register BVALR IDE register IDER Transmission request register TREQR Transmission RTR register TRTRR Remote frame receiving wait register RFWTR Transmission cancel register TCANR Transmission complete register TCR Transmission interrupt enable register TIER Reception complete register RCR Remote request receiving register RRTRR Receive overrun register RO...

Page 469: ...it NIE 0 1 Node status transition interrupt enable Node status transition interrupt enabled Node status transition interrupt disabled TOE 0 1 Transmit output enable General purpose port pin Transmit pin of TX HALT 0 1 Bus operation styop bit Write Stop of bus operation is released Read The state of bus operation is not stop mode Write Stops bus operation Read Bus operation in stop mode bit0 Reserv...

Page 470: ...eration CSR NT 1 when a node status is transferred When setting to 0 Interrupt generation is disabled When setting to 1 Interrupt generation is enabled bit1 Reserved Reserved bit This bit is always set to 0 When reading The value is always 0 bit0 HALT Bus operation halt bit This bit controls the bus halt The halt state of the bus can be checked by reading this bit Writing to this bit 0 Cancels bus...

Page 471: ...s operation is stopped HALT 1 the bus is in the intermission bus idle or a error overload frame is on the bus bit13 to bit11 Undefined bits When reading The value is undefined When writing No effect bit10 NT Node status transition flag When the node status changes from increment transition or off bus into error active this bit is set to 1 The condition that this bit is set to 1 is as follows At th...

Page 472: ...hown in Figure 21 4 3 Figure 21 4 3 Node Status Transition Diagram Table 21 4 3 Correspondence between NS1 and NS0 and Node Status NS1 NS0 Node status 0 0 Error active 0 1 Warning error active 1 0 Error passive 1 1 Bus off Error active Hardware reset Error passive TEC 256 REC 96 and TEC 96 After 0 has been written to the HALT bit of the register CSR continuous 11 bit High levels recessive bits are...

Page 473: ...as stopped always read the HALT bit Conditions for Canceling Bus Operation Stop HALT 0 The condition for canceling the bus operation if halt is writing 0 to HALT Notes Canceling the bus operation stop after hardware reset or by writing 1 to HALT as above conditions is performed after 0 is written to HALT and continuous 11 bit High levels recessive bits have been input to the receive input pin RX H...

Page 474: ...Unused X Undefined R W Read Write Reset value MBP1 MBP0 Message buffer pointer bits MBP2 MBP3 Message buffer 0 to 15 0000B to 1111B reset value 0000B RCE 0 1 0 1 0 1 Receive completion event bit The last event has not received Read Write Bit clear No effect The last event has received Read Write Bit clear No effect Read Write Bit clear No effect TCE Transmit completion event bit The last event has...

Page 475: ...1 This setting is not related to the setting of the transmit interrupt enable register TIER When this bit is 1 MBP3 to MBP0 bits show the message buffer number x to complete the transmission of the message in the last event At Write 0 Cleared 1 No effect At read by the instruction of the read modify write type Always read 1 bit5 RCE Receive completion event bit When this bit is 1 it indicates that...

Page 476: ...ning At Write 0 Cleared 1 No effect At read by the instruction of the read modify write type Always read 1 Note If LEIR is accessed within an CAN interrupt handler the event causing the interrupt is not necessarily the same as indicated by LEIR In the time from interrupt request to the LEIR access by the interrupt handler there may occur other CAN events Table 21 4 4 Function of Each Bit of the La...

Page 477: ... Reset value 0 0 0 0 0 0 0 0 B R R R R R R R R R Read only Table 21 4 5 Function of Each Bit of the Receive and Transmit Error Counters RTEC Bit Name Function bit15 to bit8 TEC7 to TEC0 Transmit error counter bits These are transmit error counters TEC7 to TEC0 values indicate 0 to 7 when the counter value is more than 256 and the subsequent increment is not counted for counter value In this case B...

Page 478: ...buffer segment 1 PHASE_SEG1 in the CAN specification bit7 bit6 RSJ1 RSJ0 Resynchronization jump width setting bits 1 0 These bits define the number of the time quanta TQ s for the resynchronization jump width bit5 to bit0 PSC5 to PSC0 Prescaler setting bits 5 to 0 These bits define the time quanta TQ of the CAN controller see below for details Note Please set CSR HALT 1 to bit timing register BTR ...

Page 479: ... segment Prescaler Settings The bit time segments defined in the CAN specification and the CAN controller are shown in Figure 21 4 7 and Figure 21 4 8 respectively Figure 21 4 7 Bit Time Segment in CAN Specification Figure 21 4 8 Bit Time Segment in CAN Controller Nominal bit time SYNC_SEG PROP_SEG PHASE_SEG1 PHASE_SEG2 Sample point Nominal bit time SYNC_SEG TSEG1 TSEG2 Sample point ...

Page 480: ...and 2 resynchronization jump width RSJ1 and RSJ0 1 frequency division For correct operation the following conditions should be met In order to meet the bit timing requirements defined in the CAN specification additions have to be met e g the propagation delay has to be considered TQ PSC 1 x CLK BT SYNC_SEG TSEG1 TSEG2 1 TS1 1 TS2 1 x TQ 3 TS1 TS2 x TQ RSJW RSJ 1 x TQ For 1 PSC 63 TSEG1 2TQ TSEG1 R...

Page 481: ...ng the messages Notes x indicates a message buffer number x 0 to 15 When invaliding a message buffer x by writing 0 to a bit BVALx execution of a bit manipulation instruction is prohibited until the bit is set to 0 To invalidate the message buffer by setting the BVALR BVAL bit to 0 while the CAN controller is operating for CAN communication the read value of the CSR HALT bit is 0 and the CAN contr...

Page 482: ... cause unnecessary received messages to be stored To invalidate the message buffer by setting the BVALR BVAL bit to 0 while the CAN controller is operating for CAN communication the read value of the CSR HALT bit is 0 and the CAN controller is operating for CAN bus communication to enable transmission and reception follow the procedure in 21 13 Precautions when Using CAN Controller Address bit15 b...

Page 483: ...te Frame Receiving Wait Register RFWTR 2 For cancellation of transmission see 21 4 14 Transmission Cancel Register TCANR and 21 4 15 Transmission Complete Register TCR Writing 0 to TREQx is ignored 0 is read when a Read Modify Write instruction is performed If clearing to 0 at completion of the transmit operation and setting by writing 1 are concurrent clearing is preferred If 1 is written to more...

Page 484: ...ster Function 0 Transmit data frame 1 Transmit remote frame Address bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 TRTRR1 Upper CAN1 007D0BH TRTR15 TRTR14 TRTR13 TRTR12 TRTR11 TRTR10 TRTR9 TRTR8 Reset value 0 0 0 0 0 0 0 0 B R W R W R W R W R W R W R W R W Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 TRTRR1 Lower CAN1 007D0AH TRTR7 TRTR6 TRTR5 TRTR4 TRTR3 TRTR2 TRTR1 TRTR0 Reset value 0 0 0 0 0 ...

Page 485: ...ransmission starts after waiting until remote frame received RRTRx of remote request receiving register RRTRR becomes 1 Notes Transmission starts immediately if RRTRx is already 1 when a request for transmission is set For remote frame transmission do not set RFWTx to 1 Address bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 RFWTR1 Upper CAN1 007D0DH RFWT15 RFWT14 RFWT13 RFWT12 RFWT11 RFWT10 RFWT9 R...

Page 486: ... message buffer x At completion of cancellation TREQx of the transmission request register TREQR becomes 0 Writing 0 to TCANx is ignored This is a write only register and its read value is always 0 Address bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 TCANR1 Upper CAN1 000085H TCAN15 TCAN14 TCAN13 TCAN12 TCAN11 TCAN10 TCAN9 TCAN8 Reset value 0 0 0 0 0 0 0 0 B W W W W W W W W Address bit7 bit6 bit5...

Page 487: ...ompletion of transmission write 0 to TCx to set it to 0 Writing 1 to TCx is ignored 1 is read when a Read Modify Write instruction is performed Note If setting to 1 by completion of the transmit operation and clearing to 0 by writing occur at the same time the bit is set to 1 Address bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 TCR1 Upper CAN1 000087H TC15 TC14 TC13 TC12 TC11 TC10 TC9 TC8 Reset v...

Page 488: ...6 Configuration of the Transmission Interrupt Enable Register TIER Register Function 0 Transmission interrupt disabled 1 Transmission interrupt enabled Address bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 TIER1 Upper CAN1 007D0FH TIE15 TIE14 TIE13 TIE12 TIE11 TIE10 TIE9 TIE8 Reset value 0 0 0 0 0 0 0 0 B R W R W R W R W R W R W R W R W Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 TIER1 Lower C...

Page 489: ...rite 0 to RCx to set it to 0 Writing 1 to RCx is ignored 1 is read when a Read Modify Write instruction is performed Note If setting to 1 by completion of the receive operation and clearing to 0 by writing occur at the same time the bit is set to 1 Address bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 RCR1 Upper CAN1 000089H RC15 RC14 RC13 RC12 RC11 RC10 RC9 RC8 Reset value 0 0 0 0 0 0 0 0 B R W R...

Page 490: ...is completed TCx of the transmission complete register TCR is 1 Writing 1 to RRTRx is ignored 1 is read when a Read Modify Write instruction is performed Note If setting to 1 by completion of the receive operation and clearing to 0 by writing occur at the same time the bit is set to 1 Address bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 RRTRR1 Upper CAN1 00008BH RRTR15 RRTR14 RRTR13 RRTR12 RRTR11...

Page 491: ...s overrun write 0 to ROVRx to set it to 0 1 is read when a Read Modify Write instruction is performed Note If setting to 1 by completion of the receive operation and clearing to 0 by writing occur at the same time the bit is set to 1 Address bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 ROVRR1 Upper CAN1 00008DH RVOR15 RVOR14 RVOR13 RVOR12 RVOR11 RVOR10 RVOR9 RVOR8 Reset value 0 0 0 0 0 0 0 0 B R ...

Page 492: ...gure 21 4 20 Configuration of the Reception Interrupt Enable Register RIER Register Function 0 Reception interrupt disabled 1 Reception interrupt enabled Address bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 RIER1 Upper CAN1 00008FH RIE15 RIE14 RIE13 RIE12 RIE11 RIE10 RIE9 RIE8 Reset value 0 0 0 0 0 0 0 0 B R W R W R W R W R W R W R W R W Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 RIER1 Lower...

Page 493: ... R W R W R W R W R W R W Address bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 AMSR1 Byte1 CAN1 007D11H AMS7 1 AMS7 0 AMS6 1 AMS6 0 AMS5 1 AMS5 0 AMS4 1 AMS4 0 Reset value XXXXXXXXB R W R W R W R W R W R W R W R W Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 AMSR1 Byte2 CAN1 007D12H AMS11 1 AMS11 0 AMS10 1 AMS10 0 AMS9 1 AMS9 0 AMS8 1 AMS8 0 Reset value XXXXXXXXB R W R W R W R W R W R W R W R W...

Page 494: ...e buffer by setting the BVALR BVAL bit to 0 while the CAN controller is operating for CAN communication the read value of the CSR HALT bit is 0 and the CAN controller is operating for CAN bus communication to enable transmission and reception follow the procedure in 21 13 Precautions when Using CAN Controller Table 21 4 7 Selection of Acceptance Mask AMSx 1 AMSx 0 Acceptance Mask 0 0 Full bit comp...

Page 495: ...it1 bit0 AMR01 Byte0 CAN1 007D14H AM28 AM27 AM26 AM25 AM24 AM23 AM22 AM21 Reset value XXXXXXXXB R W R W R W R W R W R W R W R W Address bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 AMR01 Byte1 CAN1 007D15H AM20 AM19 AM18 AM17 AM16 AM15 AM14 AM13 Reset value XXXXXXXXB R W R W R W R W R W R W R W R W Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 AMR01 Byte2 CAN1 007D16H AM12 AM11 AM10 AM9 AM8 AM7...

Page 496: ...BVALR BVAL bit to 0 while the CAN controller is operating for CAN communication the read value of the CSR HALT bit is 0 and the CAN controller is operating for CAN bus communication to enable transmission and reception follow the procedure in 21 13 Precautions when Using CAN Controller Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 AMR11 Byte0 CAN1 007D18H AM28 AM27 AM26 AM25 AM24 AM23 AM22 AM21 ...

Page 497: ... is received Data register x x 0 to 15 DTRx This register is a data register of the message buffer This register memorizes the setting or the reception message data of the transmission message data The message buffer x is used both for transmission and reception The lower numbered message buffers are assigned higher priority At transmission when a request for transmission is made to more than 1 me...

Page 498: ... write operation in bytes causes undefined data to be written to the upper byte at writing to the lower byte Writing to the upper byte is ignored When the BVALx bit of the message buffer valid register BVALR is 0 Invalid the message buffers x IDRx DLCRx and DTRx can be used as general purpose RAM During the receive transmit operation of the CAN controller the CAN Controller write read to from the ...

Page 499: ...bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 IDRx1 Byte1 CAN1 007C21H 4 x ID20 ID19 ID18 ID17 ID16 ID15 ID14 ID13 Reset value XXXXXXXXB R W R W R W R W R W R W R W R W Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 IDRx1 Byte2 CAN1 007C22H 4 x ID12 ID11 ID10 ID9 ID8 ID7 ID6 ID5 Reset value XXXXXXXXB R W R W R W R W R W R W R W R W Address bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 IDRx1 Byte3...

Page 500: ...s image of old message left in the receive shift register Notes A write operation to this register should be performed in words A write operation in bytes causes undefined data to be written to the upper byte at writing to the lower byte Writing to the upper byte is ignored This register should be set when the message buffer x is invalid BVALx of the message buffer valid register BVALR is 0 Settin...

Page 501: ...000B 0 to 8 bytes is prohibited Reception Store the data length byte count of a received message when a data frame is received RRTRx of the remote frame request receiving register RRTRR is 0 Store the data length byte count of a requested message when a remote frame is received RRTRx 1 Note A write operation to this register should be performed in words A write operation in bytes causes undefined ...

Page 502: ... 8 x D7 D6 D5 D4 D3 D2 D1 D0 Reset value XXXXXXXXB R W R W R W R W R W R W R W R W Address bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 DTRx1 Byte3 CAN1 007C83H 8 x D7 D6 D5 D4 D3 D2 D1 D0 Reset value XXXXXXXXB R W R W R W R W R W R W R W R W Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 DTRx1 Byte4 CAN1 007C84H 8 x D7 D6 D5 D4 D3 D2 D1 D0 Reset value XXXXXXXXB R W R W R W R W R W R W R W R W A...

Page 503: ...der of BYTE0 BYTE1 BYTE7 starting with the MSB Even if the received message data is less than 8 bytes the remaining bytes of the data register DTRx to which data are stored are undefined Note A write operation to this register should be performed in words A write operation in bytes causes undefined data to be written to the upper byte at writing to the lower byte Writing to the upper byte is ignor...

Page 504: ...urs during transmission the message buffer waits until the bus is idle and repeats retransmission until it is successful Canceling Transmission Request from CAN Controller Canceling by transmission cancel register TCANR A transmission request for message buffer x having not executed transmission during transmission pending can be canceled by writing 1 to TCANx of the transmission cancel register T...

Page 505: ... Transmission Flowchart of CAN Controller Figure 21 5 1 Transmission Flowchart of the CAN Controller Transmission request TREQx 1 TCx 0 TREQx 0 1 RFWTx 0 1 RRTRx 1 0 Is the bus idle NO TRTRx 0 1 A data frame is transmitted A remote frame is transmitted YES Is transmission successful NO YES RRTRx 0 TREQx 0 TCx 1 TIEx A transmission complete interrupt occurs 1 0 TCANx 1 0 TREQx 0 End of transmission...

Page 506: ...emote frames received messages are stored only in the IDRx and DLCRx and the DTRx remains unchanged If there is more than 1 message buffer including IDs passed through the acceptance filter the message buffer x in which received messages are to be stored is determined according to the following rules The order of priority of the message buffer x x 0 to 15 rises as its number lower in other words m...

Page 507: ... of data frame RRTRx of the remote request receiving register RRTRR becomes 0 TREQx of the transmission request register TREQR becomes 0 immediately before storing the received message A transmission request for message buffer x having not executed transmission will be canceled Note A request for transmission of either a data frame or remote frame is canceled Processing for reception of remote fra...

Page 508: ...ception complete register RCR becomes 1 after storing the received message If a reception interrupt is enabled RIEx of the reception interrupt enable register RIER is 1 an interrupt occurs Note This CAN controller will not receive any messages transmitted by itself ...

Page 509: ...1 0 NO YES NO YES RRTRx 0 RRTRx 1 TRTRx 0 1 TREQx 0 RCx 1 RCx 1 0 ROVRx 1 Detection of start of data frame or remote frame SOF Is any message buffer x passing to the acceptance filter found End of reception Is reception successful A reception interrupt occurs Received message Data frame Remote frame Store the received message in the message buffer x Determine message buffer x where received messag...

Page 510: ...message buffer x ID is used as a transmission message at transmission and is used as an acceptance code at reception This setting should be made when the message buffer x is invalid BVALx of the message buffer valid register BVALR is 0 Setting when the buffer is valid BVALx 1 may cause unnecessary received messages to be stored Setting Acceptance Filter The acceptance filter of the message buffer ...

Page 511: ...sumption Mode To set the F2 MC 16LX in a low power consumption mode Stop and Timebase timer write 1 to the bus operation stop bit HALT of the control status register CSR and then check that the bus operation has stopped HALT 1 ...

Page 512: ...ta length byte count of the requested message Note Setting other than 0000B to 1000B 0 to 8 bytes is prohibited Setting transmit data only for transmission of data frame For data frame transmission when TRTRx of the transmission register TRTRR is 0 set data as the count of byte transmitted in the data register DTRx Note Transmit data should be rewritten while the TREQx bit of the transmission requ...

Page 513: ... write 1 to TCANx of the transmission cancel register TCANR Check TREQx For TREQx 0 transmission cancellation is terminated or transmission is completed Check TCx of the transmission complete register TCR For TCx 0 transmission cancellation is terminated For TCx 1 transmission is completed Processing for completion of transmission If transmission is successful TCx of the transmission complete regi...

Page 514: ...x of the reception complete register RCR becomes 1 For data frame reception RRTRx of the remote request receiving register RRTRR becomes 0 For remote frame reception RRTRx becomes 1 If a reception interrupt is enabled RIEx of the reception interrupt enable register RIER is 1 an interrupt occurs After checking the reception completion RCx 1 process the received message After completion of processin...

Page 515: ...499 Figure 21 10 1 Example of Receive Interrupt Handling End Read received messages A 0 NO YES RCx 0 Interrupt with RCx 1 A ROVRx ROVRx 0 ...

Page 516: ...e combined message buffers If the bits of the acceptance mask select register AMSR are set to All Bits Compare AMSx 1 AMSx 0 0 0 multi level message configuration of message buffers is not allowed This is because All Bits Compare causes received messages to be stored irrespective of the value of the RCx bit of the receive completion register RCR so received messages are always stored in lower numb...

Page 517: ... 0000 000 0 0 0 0 1 0 Select AMR0 Message receiving The received message is stored in message buffer 13 RCR ROVRR 0 0 1 0 Message receiving Message buffer 13 Message buffer 14 Message buffer 15 0101 1111 001 0101 1111 000 0101 1111 001 0101 0000 000 0 0 0 0 1 0 Message receiving The received message is stored in message buffer 14 Message receiving The received message is stored in message buffer 1...

Page 518: ...e the clock modulation function So at using CAN controller the DIRECT bit of the register must be set 1 Initial value X X X X X X X 0 B Address H CAN0 00796E CDMR R W DIRECT 7 6 5 4 3 2 1 0 X R W Readable and writable Undefined value Undefined Table 21 12 1 Function of CAN Direct Mode Register CDMR Bit Name Function bit 7 to 1 Undefined bits bit 0 DIRECT If the clock modulation is set initial stat...

Page 519: ...request Do not use BVAL bit for suppressing transmission request use TCAN bit instead of it Operation for composing transmission message For composing a transmission message it is necessary to disable the message buffer by BVAL bit to change contents of ID and IDE registers In this case BVAL bit should reset BVAL 0 after checking if TREQ bit is 0 or after completion of the previous message transmi...

Page 520: ...B90360 does not provide the clock modulation function For this reason ensure that the DIRECT bit of the CAN direct mode register CDMR is set to 1 when CAN is used Note that the CAN controller will not normally operate without correct setting of the DIRECT bit ...

Page 521: ...ion and its operation 22 1 Overview of Address Match Detection Function 22 2 Block Diagram of Address Match Detection Function 22 3 Configuration of Address Match Detection Function 22 4 Explanation of Operation of Address Match Detection Function 22 5 Program Example of Address Match Detection Function ...

Page 522: ...n Function The address of the instruction to be processed next to the instruction currently processed by the program is always held in the address latch through the internal data bus The address match detection function always compares the value of the address held in the address latch with that of the address set in the detect address setting registers When these compared values match the next in...

Page 523: ...tection control register PACSR0 PACSR1 The address detection control register enables or disables output of an interrupt at an address match Detect address setting registers PADR0 to PADR5 The detect address setting registers set the address that is compared with the value of the address latch AD1E AD2E AD0E PACSR0 AD4E AD5E AD3E PACSR1 Address latch Detection address setting register 0 PADR0 24 b...

Page 524: ... 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Address detection control register 0 PACSR0 Address detection control register 1 PACSR1 Detection address setting register 0 PADR0 Low Detection address setting register 0 PADR0 Middle Detection address setting register 0 PADR0 High Detection address setting register 1 PADR1 Low Detection address setting register 1 PADR1 Middle Detection address setting register ...

Page 525: ...e served Re served Re served Re served Re served Address Reset value bit 0 Reserved Reserved bit 0 Always set to 0 bit 1 AD0E Address match detection enable bit 0 0 Disables address match detection in PADR0 1 Enables address match detection in PADR0 bit 2 Reserved Reserved bit 0 Always set to 0 bit 5 AD2E Address match detection enable bit 2 0 Disables address match detection in PADR2 1 Enables ad...

Page 526: ...ection operation with the detect address setting register 1 PADR1 is enabled or disabled When set to 0 Disables the address match detection operation When set to 1 Enables the address match detection operation When the value of detect address setting registers 1 PADR1 matches with the value of address latch at enabling the address match detection operation AD1E 1 the INT9 instruction is immediatel...

Page 527: ...etection enable bit 3 0 Disables address match detection in PADR3 1 Enables address match detection in PADR3 R W Read Write Reset value bit 10 Reserved Reserved bit 0 Always set to 0 bit 11 AD4E Address match detection enable bit 4 0 Disables address match detection in PADR4 1 Enables address match detection in PADR4 bit 12 Reserved Reserved bit 0 Always set to 0 bit 13 AD5E Address match detectio...

Page 528: ...etection operation with the detect address setting register 4 PADR4 is enabled or disabled When set to 0 Disables the address match detection operation When set to 1 Enables the address match detection operation When the value of detect address setting registers 4 PADR4 matches with the value of address latch at enabling the address match detection operation AD4E 1 the INT9 instruction is immediat...

Page 529: ...2H 0079E2H 0079F1H 0079E1H 0079F0H 0079E0H 0079F5H 0079E5H 0079F4H 0079E4H 0079F3H 0079E3H R W R W R W R W R W R W R W R W D11 D8 D9 D10 D15 D12 D13 D14 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 R W R W R W R W R W R W R W R W D3 D0 D1 D2 D7 D4 D5 D6 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 R W R W R W R W R W R W R W R W bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 R W R W R W R W R W R W R W...

Page 530: ...R0 AD1E High Set the upper 8 bits of detect address 1 bank Middle Set the middle 8 bits of detect address 1 Low Set the lower 8 bits of detect address 1 Detect address setting register 2 PADR2 PACSR0 AD2E High Set the upper 8 bits of detect address 2 bank Middle Set the middle 8 bits of detect address 2 Low Set the lower 8 bits of detect address 2 Detect address setting register 3 PADR3 PACSR1 AD3...

Page 531: ... PADR0 to PADR5 should be set after disabling the address match detection PACSR ADnE 0 of corresponding address match control registers If the detect address setting registers are changed without disabling the address match detection the address match detection function will work immediately after an address match occurs during writing address which may cause malfunction The address match detectio...

Page 532: ... address is set for address match detection PACSR0 AD0E 0 2 Set the detect address in the detection address setting register 0 PADR0 Set FFH at the higher bits 00H at the middle bits and 1FH at the lower bits of the detection address setting register 0 PADR0 3 Enable the detect address setting register 0 PADR0 where the detect address is set for address match detection PACSR0 AD0E 1 Program Execut...

Page 533: ...tion function System Configuration and E2 PROM Memory Map System configuration Figure 22 4 2 gives an example of the system configuration using the address match detection function Figure 22 4 2 Example of System Configuration Using Address Match Detection Function E2 PROM MCU F2MC16LX SIN Storing patch program Serial E2 PROM interface Pull up resistor Storing patch program from the outside Connec...

Page 534: ...e program address matches the detect address is stored Patch program 0 is allocated from any predetermined address Patch program 1 is allocated from the address indicating starting address of patch program 0 total byte count of patch program 0 It is similar for the correction program 2 to 5 PADR0 PADR1 PADR5 0 0 0 0 H 0 0 0 1 H 0 0 0 2 H 0 0 0 3 H 0 0 0 4 H 0 0 0 5 H 0 0 0 6 H 0 0 0 7 H 0 0 1 4 H ...

Page 535: ... 5 are read and set in the detection address setting registers 0 to 5 PADR0 to PADR5 The patch program main body is read according to the byte count of the patch program and written to RAM in the MCU F2 MC16LX The patch program main body is allocated to the address where the patch program is executed in the INT9 interrupt processing by the address match detection function Address match detection i...

Page 536: ...tch processing for patch program using the address match detection function ROM RAM 000000H FFFFFFH Patch program Detection address setting register Detection address setting reset sequence Serial E2 PROM interface E2PROM Patch program byte count Address for address detection Patch program Program error 1 2 3 4 1 Execution of detection address setting of reset sequence and normal program 2 Branch ...

Page 537: ...k area Detection address setting register Program error Patch program byte count 80H Detect address Low 00H Detect address Middle 80H Detect address High FFH Patch program Reset Read the 00H of E2PROM Read detect address E2 PROM 0001H to 0003H Å MCU Set to PADR0 Read patch program E2 PROM 0010H to 008FH Å MCU 000400H to 000047FH Enable address match detection PACSR AD0E 1 Execution of normal progr...

Page 538: ...xecuted Coding example PACSR0 EQU 00009EH Address detection control register 0 PADRL EQU 0079E0H Detection address setting register 0 Low PADRM EQU 0079E1H Detection address setting register 0 Middle PADRH EQU 0079E2H Detection address setting register 0 High Main program CODE CSEG START Stack pointer SP etc already initialized MOV PADRL 00H Set address detection register 0 Low MOV PADRM 00H Set a...

Page 539: ...ESS MATCH DETECTION FUNCTION RETI Return from interrupt processing CODE ENDS Vector setting VECT CSEG ABS 0FFH ORG 00FFD8H DSL WARI ORG 00FFDCH Set reset vector DSL START DB 00H Set to single chip mode VECT ENDS END START ...

Page 540: ...524 CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION ...

Page 541: ...OM MIRRORING MODULE This chapter describes the functions and operations of the ROM mirroring function select module 23 1 Overview of ROM Mirroring Function Select Module 23 2 ROM Mirroring Function Select Register ROMM ...

Page 542: ...to FF Bank by ROM Mirroring Function Figure 23 1 2 shows the location in memory when ROM mirroring function allows access to the 00 bank to read ROM data in the FF bank Figure 23 1 2 Access to FF Bank by ROM Mirroring Function ROM MI ROM mirror function select register ROMM Re served Re served Re served Re served Re served Re served Re served Address area 00 bank FF bank Address Data Internal data...

Page 543: ...ing Function Select Module Figure 23 1 4 List of Registers and Reset Values of ROM Mirroring Function Select Module RAM FFFFFFH 010000H 008000H 007900H 000100H 0000F0H 000000H Single chip ROM area ROM area image of FF bank Extended I O area General purpose register I O Internal Access disabled Product type Address 1 Address 2 MB90F362 T S MB90362 T S MB90F367 T S MB90367 T S FF0000H 000D00H MB90V3...

Page 544: ...ted X X X X X X X 1 B 12 13 11 10 9 8 15 14 W X W 00006FH MI Reset value bit8 MI ROM mirroring function select bit 0 ROM mirroring function disabled 1 ROM mirroring function enabled Address Write only Indeterminate Undefined Reset value Table 23 2 1 Functions of ROM Mirroring Function Select Register ROMM Bit Name Function bit8 MI ROM mirroring function select bit This bit enables or disables the ...

Page 545: ...s chapter explains Executing programs to write erase data 24 1 Overview of 512K bit Flash Memory 24 2 Block Diagram of the Entire Flash Memory and Sector Configuration of the Flash Memory 24 3 Write Erase Modes 24 4 Flash Memory Control Status Register FMCS 24 5 Starting the Flash Memory Automatic Algorithm 24 6 Confirming the Automatic Algorithm Execution State 24 7 Detailed Explanation of Writin...

Page 546: ...upts Minimum of 10 000 write erase operations Flash reading cycle time Minimum of 2 machine cycles Embedded AlgorithmTM is a trademark of Advanced Micro Devices Inc Note The manufacturer code and device code do not have the reading function These codes cannot be accessed by the command Writing to erasing Flash Memory The flash memory cannot be written to and erased at the same time That is when da...

Page 547: ... Figure 24 2 1 Block Diagram of the Entire Flash Memory Sector Configuration of the 512K bit Flash Memory Figure 24 2 2 shows the sector configuration of the 512K bit flash memory The addresses in the figure indicate the high order and low order addresses of each sector BYTE CE OE WE AQ0 to AQ18 DQ0 to DQ15 RY BY BYTE CE OE WE AQ0 to AQ15 AQ 1 DQ0 to DQ15 RY BY INT RESET RY BY Flash memory interfa...

Page 548: ...T S MB90F367 T S 7FFFFH 70000H FFFFFFH FF0000H Programmer address CPU address SA0 64K bytes The programmer address is equivalent to the CPU address when data is written to the flash memory using a paral lel programmer When a general programmer is used for writing erasing this address is used for writing erasing ...

Page 549: ...using a flash memory programmer In flash memory mode all operations supported by the flash memory automatic algorithm can be used Alternative Mode The flash memory is located in the FF bank in the CPU memory space and like ordinary mask ROM can be read accessed and program accessed from the CPU via the flash memory interface circuit Since writing erasing the flash memory is performed by instructio...

Page 550: ...Pin number Normal function Flash memory mode LQFP 42 P83 AQ16 A15 38 P87 CE CE 39 P86 OE OE 40 P43 WE WE 41 45 P42 P44 AQ17 AQ18 A16 37 P85 BYTE BYTE 11 P80 RY BY RY BY 12 to 19 P50 to P57 AQ8 to AQ15 A7 to A14 21 MD1 MD1 RESET VID 20 MD2 MD2 OE VID 3 to 10 P60 to P67 DQ0 to DQ7 DQ0 to DQ7 23 RST RESET RESET 29 to 36 P27 to P20 AQ0 to AQ7 A 1 A0 to A6 ...

Page 551: ...bled 1 Programming erasing terminated next data programming erasing enabled R W Read Write R Read only W Write only X Undefined Reset value bit1 Reserved Reserved bit 0 Always set to 0 bit2 Reserved Reserved bit 0 Always set to 0 bit3 Reserved Reserved bit 0 Always set to 0 bit5 WE Flash memory programming erasing enable bit 0 Programming erasing flash memory area disabled 1 Programming erasing fl...

Page 552: ...ed FMCS INTE 1 an interrupt is requested If the RDYINT bit is 0 programming erasing flash memory is disabled When set to 0 Cleared When set to 1 No effect If the read modify write RMW instructions are used 1 is always read bit5 WE Flash memory programming erasing enable bit This bit enables or disables the programming erasing of flash memory The WE bit should be set before starting the command to ...

Page 553: ...537 CHAPTER 24 512K BIT FLASH MEMORY Figure 24 4 2 Transitions of the RDYINT and RDY Bits Automatic algorithm end timing RDYINT bit RDY bit 1 Machine cycle ...

Page 554: ... write cycle 3rd bus write cycle 4th bus write cycle 5th bus write cycle 6th bus write cycle Address Data Address Data Address Data Address Data Address Data Address Data Read reset 1 FFXXXX XXF0 Read reset 4 FFAAAA XXAA FF5554 XX55 FFAAAA XXF0 RA RD Write program 4 FFAAAA XXAA FF5554 XX55 FFAAAA XXA0 PA even PD word Chip erase 6 FFAAAA XXAA FF5554 XX55 FFAAAA XX80 FFAAAA XXAA FF5554 XX55 FFAAAA X...

Page 555: ... are configured from the three bit output of DQ7 DQ6 and DQ5 The functions of these bits are those of the data polling flag DQ7 toggle bit flag DQ6 and timing limit exceeded flag DQ5 The hardware sequence flags can therefore be used to confirm that writing or chip erase has been completed or that erase code write is valid The hardware sequence flags can be accessed by read accessing the addresses ...

Page 556: ...creating a program use one of the flags to confirm that automatic writing erasing has terminated Then perform the next processing operation such as data read The following sections describe each hardware sequence flag separately Table 24 6 2 lists the functions of the hardware sequence flags Table 24 6 2 Hardware Sequence Flag Function State DQ7 DQ6 DQ5 State change for normal operation Write Writ...

Page 557: ...ress signal Chip erase Read access during execution of the chip erase algorithm causes the flash memory to output 0 Read access at the end of the automatic chip algorithm causes the flash memory to output 1 in the same way Note When the automatic algorithm is being started read access to the specified address is ignored Since termination of the data polling flag DQ7 can be accepted for a data read...

Page 558: ...to toggle the 1 or 0 state for every read cycle regardless of the value at the address specified by the address signal Continuous read access at the end of the automatic write algorithm and chip erase algorithm causes the flash memory to stop toggling bit 6 and output bit 6 DATA 6 of the read value of the address specified by the address signal Table 24 6 5 State Transition of Toggle Bit Flag Stat...

Page 559: ...the automatic algorithm is still being executed by the data polling function or toggle bit function For example writing 1 to a flash memory address where 0 has been written will cause the fail state to occur In this case the flash memory will lock and execution of the automatic algorithm will not terminate In rare cases normal termination may be seen as with the case where 1 can be written As a re...

Page 560: ...utomatic algorithm by issuing a command sequence see Table 24 5 1 for a write cycle to the bus to perform Read Reset Write or Chip Erase operations Each bus write cycle must be performed continuously In addition whether the automatic algorithm has terminated can be determined using the data polling or other function At normal termination the flash memory is returned to the read reset state Each op...

Page 561: ...nces that execute the first and third bus operations However there are no essential differences between these command sequences The read reset state is the initial state of the flash memory When the power is turned on and when a command terminates normally the flash memory is set to the read reset state In the read reset state other commands wait for input In the read reset state data is read by r...

Page 562: ...he time prescribed for writing is thus exceeded the timing limit exceeded flag DQ5 is determined to be an error Otherwise the data is viewed as if dummy data 1 had been written However when data is read in the read reset state the data remains 0 Data 0 can be set to data 1 only by erase operations All commands are ignored during execution of the automatic write algorithm If a hardware reset is sta...

Page 563: ...ming enabled Program command sequence 1 FxAAAA XXAA 2 Fx5554 XX55 3 FxAAAA XXA0 4 Program address Program data FMCS WE bit 5 Flash programming enabled Start writing Next address Internal address read Data polling flag DQ7 Timing limit DQ5 Internal address read Data polling flag DQ7 Last address Completed Programming error Check by hardware sequence flag ...

Page 564: ...tes 0 for verification before all of the cells are erased automatically Erasing Chip in the Flash Memory The hardware sequence flags see 24 6 Confirming the Automatic Algorithm Execution State can be used to determine the state of the automatic algorithm in the flash memory Figure 24 7 2 is an example of the procedure for erasing chip in the flash memory Here the toggle bit flag DQ6 is used to con...

Page 565: ... 1 FFAAAA XXAA 2 FF5554 XX55 3 FFAAAA XX80 4 FFAAAA XXAA 5 FF5554 XX55 6 FFAAAA XX10 FMCS WE bit 5 Disable flash memory erase Start writing Toggle bit DQ6 data1 DQ6 data2 DQ6 Read internal address 1 Timing limit DQ5 Toggle bit DQ6 data1 DQ6 data2 DQ6 Completed Erase error Check by hardware sequence flag Read internal address 2 Read internal address 1 Read internal address 2 ...

Page 566: ... undefined Canceling of a software reset and watchdog timer reset When the flash memory is being written to or erased with CPU access and if reset conditions occur while the automatic algorithm is active the CPU may run out of control This occurs because these reset conditions cause the automatic algorithm to continue without initializing the flash memory unit possibly preventing the flash memory ...

Page 567: ...urity Feature Performing the chip erase operation Behavior Under the Flash Security Feature Read operation invalid data read Write operation ignored Others 1 About configuration of the general purpose parallel programmer please follow to the specification of parallel programmer 2 Writing the protection code at the last of flash memory programming is recommended in order to prevent the device from ...

Page 568: ...552 CHAPTER 24 512K BIT FLASH MEMORY ...

Page 569: ...crocontroller programer from Yokogawa Digital Computer Corporation is used 25 1 Basic Configuration of Serial Programming Connection with MB90F362 T S MB90F367 T S 25 2 Example of Serial Programming Connection User Power Supply Used 25 3 Example of Serial Programming Connection Power Supplied from Programmer 25 4 Example of Minimum Connection to Flash Microcontroller Programmer User Power Supply U...

Page 570: ...icrocontroller programmer Figure 25 1 1 shows the basic configuration for the example serial programming connection of MB90F362 T S MB90F367 T S Figure 25 1 1 Basic Configuration MB90F362 T S MB90F367 T S Serial Programming Connection Note For information on the functions of and operational procedures related to the flash microcontroller programmer AF220 AF210 AF120 AF110 the general purpose commo...

Page 571: ...rial on board Programming Pin Function Additional information MD2 MD1 MD0 Mode pins Controls programming mode from the flash microcontroller programmer X0 X1 Oscillation pins In programming mode the CPU internal operation clock signal is one multiple of the PLL clock signal frequency Therefore because the oscillation clock frequency becomes the internal operation clock signal the oscillator used f...

Page 572: ... Digital Computer Corporation Model Function Main unit AF220 AC4P Ethernet interface built in model and 100 V to 220 V AC power adapter AF210 AC4P Standard model and 100 V to 220 V AC power adapter AF120 AC4P Single key Ethernet interface built in model and 100 V to 220 V AC power adapter AF110 AC4P Single key model and 100 V to 220 V AC power adapter AZ221 RS232C cable for programmer PC AT AZ210 ...

Page 573: ...d Figure 25 2 1 Example of Serial Programming Connection for MB90F362 T S MB90F367 T S Single chip Modes User power supply Used P83 MD0 MD1 TMODE TAUX3 MD2 Connector DX10 28S DX20 28S AF220 AF210 AF120 AF110 flash microcontroller programmer TAUX User User system X0 X1 10kΩ Vss Vcc GND SCK1 SOT1 SIN1 TRXD TTXD TCK DX10 28S Right angle type DX20 28S Straight type RST P84 TVcc User power supply C Con...

Page 574: ... is required in the same way that it is for P83 The TICS signal of the flash microcontroller programmer can be used to disconnect the user circuit during serial programming Figure 25 2 2 Control Circuit Connect the AF220 AF210 AF120 AF110 while the user power is off User 10kΩ write control pin AF220 AF210 AF120 AF110 write control pin AF220 AF210 AF120 AF110 TICS pin MB90F362 T S MB90F367 T S ...

Page 575: ...om programmer Figure 25 3 1 Example of Serial Programming Connection for MB90F362 T S MB90F367 T S Single chip Modes Power supplied from programmer P83 MD0 MD1 TMODE TAUX3 MD2 DX10 28S DX20 28S AF220 AF210 AF120 AF110 TAUX X0 X1 10kΩ Vss Vcc GND SCK1 SOT1 SIN1 TRXD TTXD TCK RST P84 TVcc C DX10 28S DX20 28S 4MHz to 16MHz 10kΩ 10kΩ TICS TRES 10kΩ 7 8 14 15 21 22 1 28 2 6 27 13 5 10 23 12 19 0 1µF 10...

Page 576: ... of the flash microcontroller programmer can be used to disconnect the user circuit during serial programming Figure 25 3 2 Control Circuit Connect the AF220 AF210 AF120 AF110 while the user power is off When the programming power is supplied from the AF220 AF210 AF120 AF110 be careful not to short circuit the user power supply User 10kΩ Write control pin AF220 AF210 AF120 AF110 write control pin ...

Page 577: ... Figure 25 4 1 Example of Minimum Connection to MB90F362 T S MB90F367 T S Flash Microcontroller Programmer User power supply Used 10kΩ MD1 MD2 AF220 AF210 AF120 AF110 MD0 10kΩ 10kΩ 10kΩ 10kΩ 10kΩ 1 for serial rewriting 0 for serial rewriting User circuit P83 10kΩ P84 User circuit 1 for serial rewriting X0 X1 4MHz to 16MHz Vss GND Connector 7 8 14 15 21 22 1 28 SIN1 TTXD 13 SOT1 TRXD 27 SCK1 TCK 6 ...

Page 578: ... the figure below is required The TICS signal of the flash microcontroller programmer can be used to disconnect the user circuit during serial programming Figure 25 4 2 Control Circuit Connect the AF220 AF210 AF120 AF110 while the user power is off User 10kΩ Write control pin AF220 AF210 AF120 AF110 write control pin AF220 AF210 AF120 AF110 TICS pin MB90F362 T S MB90F367 T S ...

Page 579: ...ns are set as Figure 25 5 1 Figure 25 5 1 Example of Minimum Connection to the MB90F362 T S MB90F367 T S Flash Microcontroller Programmer power supplied from programmer 10kΩ MD1 MD2 AF220 AF210 AF120 AF110 MD0 10kΩ 10kΩ 10kΩ 10kΩ 10kΩ 1 for serial rewrite 0 for serial rewrite User circuit P83 10kΩ P84 User circuit 1 for serial rewrite X0 X1 4MHz to 16MHz Vss GND Connector 7 8 14 15 21 22 1 28 4 9 ...

Page 580: ...ocontroller programmer can be used to disconnect the user circuit during serial programming Figure 25 5 2 Control Circuit Connect the AF220 AF210 AF120 AF110 while the user power is off When the programming power is supplied from the AF220 AF210 AF120 AF110 be careful not to short circuit the user power supply User 10kΩ Write control pin AF220 AF210 AF120 AF110 write control pin AF220 AF210 AF120 ...

Page 581: ...565 CHAPTER 26 ROM SECURITY FUNCTION This chapter explains the ROM security function 26 1 Overview of ROM Security Function ...

Page 582: ...nction The ROM security function protects the content of ROM Overview of ROM Security Function The ROM security function is a function to prevent ROM data being read to the third party by limiting the access to ROM Please contact to Fujitsu about details of this function ...

Page 583: ... APPENDIX The appendixes provide I O maps instructions and other information APPENDIX A I O Maps APPENDIX B Instructions APPENDIX C Timing Diagrams in Flash Memory Mode APPENDIX D List of Interrupt Vectors ...

Page 584: ... PDR8 R W Port 8 XXXXXXXXB 000009H to 00000AH Reserved 00000BH Analog input enable port 5 ADER5 R W Port 5 A D 1 1 1 1 1 1 1 1B 00000CH Analog input enable port 6 ADER6 R W Port 6 A D 1 1 1 1 1 1 1 1B 00000DH Reserved 00000EH Input level select register0 ILSR0 R W Ports XXXXXXXXB 00000FH Input level select register1 ILSR1 R W Ports XXXXXXXXB 000010H Reserved 000011H 000012H Port 2 direction regist...

Page 585: ...ter 1 SMR1 W R W UART1 0 0 0 0 0 0 0 0B 000029H Serial control register 1 SCR1 W R W 0 0 0 0 0 0 0 0B 00002AH Reception transmission data register 1 RDR1 TDR1 R W 0 0 0 0 0 0 0 0B 00002BH Serial status register 1 SSR1 R R W 0 0 0 0 1 0 0 0B 00002CH Extended communication control register1 ECCR1 R W R W 0 0 0 0 0 0 XXB 00002DH Extended status control register 1 ESCR1 R W 0 0 0 0 0 1 0 0B 00002EH Ba...

Page 586: ...tus 3 TMCSR3 R W 16 bit Reload Timer 3 0 0 0 0 0 0 0 0B 000067H Timer control status 3 TMCSR3 R W XXXX 0 0 0 0B 000068H A D control status 0 ADCS0 R W A D Converter 0 0 0 XXXX 0B 000069H A D control status 1 ADCS1 R W W 0 0 0 0 0 0 0 XB 00006AH A D data 0 ADCR0 R 0 0 0 0 0 0 0 0B 00006BH A D data 1 ADCR1 R XXXXXX 0 0B 00006CH ADC setting 0 ADSR0 R W 0 0 0 0 0 0 0 0B 00006DH ADC setting 1 ADSR1 R W...

Page 587: ...000B2H Interrupt control register 02 ICR02 W R W 0 0 0 0 0 1 1 1B 0000B3H Interrupt control register 03 ICR03 W R W 0 0 0 0 0 1 1 1B 0000B4H Interrupt control register 04 ICR04 W R W 0 0 0 0 0 1 1 1B 0000B5H Interrupt control register 05 ICR05 W R W 0 0 0 0 0 1 1 1B 0000B6H Interrupt control register 06 ICR06 W R W 0 0 0 0 0 1 1 1B 0000B7H Interrupt control register 07 ICR07 W R W 0 0 0 0 0 1 1 1B...

Page 588: ... External interrupt level 1 ELVR1 R W 0 0 0 0 0 0 0 0B 0000CDH External interrupt level 1 ELVR1 R W 0 0 0 0 0 0 0 0B 0000CEH External interrupt 1 source select EISSR R W 0 0 0 0 0 0 0 0B 0000CFH PLL subclock control register PSCCR W PLL XXXX 0 0 0 0B 0000D0H to 0000FFH Reserved Table A 1 I O Map 5 5 Address Register Abbreviation Access Peripheral Initial value ...

Page 589: ...ut capture 0 IPCP0 R Input Capture 0 1 XXXXXXXXB 7921H Input capture 0 IPCP0 R XXXXXXXXB 7922H Input capture 1 IPCP1 R XXXXXXXXB 7923H Input capture 1 IPCP1 R XXXXXXXXB 7924H Input capture 2 IPCP2 R Input Capture 2 3 XXXXXXXXB 7925H Input capture 2 IPCP2 R XXXXXXXXB 7926H Input capture 3 IPCP3 R XXXXXXXXB 7927H Input capture 3 IPCP3 R XXXXXXXXB 7928H to 793FH Reserved 7940H Timer data 0 TCDT0 R W ...

Page 590: ...XXXXXB 79E7H Detection address setting 2 PADR2 R W XXXXXXXXB 79E8H Detection address setting 2 PADR2 R W XXXXXXXXB 79E9H to 79EFH Reserved 79F0H Detection address setting 3 PADR3 R W Address Match Detection 1 XXXXXXXXB 79F1H Detection address setting 3 PADR3 R W XXXXXXXXB 79F2H Detection address setting 3 PADR3 R W XXXXXXXXB 79F3H Detection address setting 4 PADR4 R W XXXXXXXXB 79F4H Detection add...

Page 591: ...d write enabled R Only read enabled W Only write enabled Explanation of initial values 0 The initial value of this bit is 0 1 The initial value of this bit is 1 X The initial value of this bit is undefined 7D00H to 7DFFH Reserved for CAN interface 1 For more information see Table 21 3 2 7E00H to 7FFFH Reserved Table A 2 I O Map 7900H 7FFFH 3 3 Address Register Abbreviation Access Peripheral Initia...

Page 592: ... instructions used by the F2 MC 16LX B 1 Instruction Types B 2 Addressing B 3 Direct Addressing B 4 Indirect Addressing B 5 Execution Cycle Count B 6 Effective address field B 7 How to Read the Instruction List B 8 F2 MC 16LX Instruction List B 9 Instruction Map ...

Page 593: ...long word 12 increment decrement instructions byte word or long word 11 comparison instructions byte word or long word 11 unsigned multiplication division instructions word or long word 11 signed multiplication division instructions word or long word 39 logic instructions byte or word 6 logic instructions long word 6 sign inversion instructions byte or word 1 normalization instruction long word 18...

Page 594: ...h address addr24 I O direct io Abbreviated direct address dir Direct address addr16 I O direct bit address io bp Abbreviated direct bit address dir bp Direct bit address addr16 bp Vector address vct Register indirect RWj j 0 to 3 Register indirect with post increment RWj j 0 to 3 Register indirect with displacement RWi disp8 i 0 to 7 RWj disp16 j 0 to 3 Long register indirect with displacement RLi...

Page 595: ... Register indirect DTB 09 RW1 DTB 0A RW2 ADB 0B RW3 SPB 0C RW0 Register indirect with post increment DTB 0D RW1 DTB 0E RW2 ADB 0F RW3 SPB 10 RW0 disp8 Register indirect with 8 bit displacement DTB 11 RW1 disp8 DTB 12 RW2 disp8 ADB 13 RW3 disp8 SPB 14 RW4 disp8 Register indirect with 8 bit displacement DTB 15 RW5 disp8 DTB 16 RW6 disp8 ADB 17 RW7 disp8 SPB 18 RW0 disp16 Register indirect with 16 bi...

Page 596: ...ction stores the operand value in A Before execution A 2 2 3 3 4 4 5 5 After execution A 4 4 5 5 1 2 1 2 Some instructions transfer AL to AH Table B 3 1 Direct Addressing Registers General purpose register Byte R0 R1 R2 R3 R4 R5 R6 R7 Word RW0 RW1 RW2 RW3 RW4 R5W RW6 RW7 Long word RL0 RL1 RL2 RL3 Special purpose register Accumulator A AL Pointer SP Bank PCB DTB USB SSB ADB Page DPR Control PS CCR ...

Page 597: ... Bits 23 to 16 of the address are specified by the program bank register PCB Figure B 3 3 Example of Direct Branch Addressing addr16 MOV R0 A Before execution A 0 7 1 6 2 5 3 4 After execution A 0 7 1 6 2 5 6 4 This instruction transfers the eight low order bits of A to the general purpose register R0 R0 Memory space 3 4 R0 Memory space JMP 3B20H Before execution PC 3 C 2 0 After execution This in...

Page 598: ... accessed regardless of the data bank register DTB and direct page register DPR A bank select prefix for bank addressing is invalid if specified before an instruction using I O direct addressing Figure B 3 5 Example of I O Direct Addressing io JMPP 333B20H Before execution PC 3 C 2 0 After execution PCB 4 F PC 3 B 2 0 PCB 3 3 4F3C23H 3 3 4F3C22H 3 B 4F3C21H 2 0 4F3C20H 6 3 JMPP 333B20H Memory spac...

Page 599: ...to 23 are specified by the data bank register DTB A prefix instruction for access space addressing is invalid for this mode of addressing Figure B 3 7 Example of Direct Addressing addr16 4 4 5 5 1 2 1 2 6 6 6 6 1 2 4 4 5 5 1 2 1 2 7 7 DTB 7 7 DTB 776620H 776620H Before execution After execution MOVW S 20H A Memory space Memory space A A This instruction writes the contents of the eight low order b...

Page 600: ...bit LSB Figure B 3 9 Example of Abbreviated Direct Bit Addressing dir bp Direct bit addressing addr16 bp Specify arbitrary bits in 64K bytes explicitly Address bits 16 to 23 are specified by the data bank register DTB Bit positions are indicated by bp where the larger number indicates the most significant bit MSB and the lower number indicates the least significant bit LSB Figure B 3 10 Example of...

Page 601: ...on Vector address L Vector address H CALLV 0 XXFFFEH XXFFFFH CALLV 1 XXFFFCH XXFFFDH CALLV 2 XXFFFAH XXFFFBH CALLV 3 XXFFF8H XXFFF9H CALLV 4 XXFFF6H XXFFF7H CALLV 5 XXFFF4H XXFFF5H CALLV 6 XXFFF2H XXFFF3H CALLV 7 XXFFF0H XXFFF1H CALLV 8 XXFFEEH XXFFEFH CALLV 9 XXFFECH XXFFEDH CALLV 10 XXFFEAH XXFFEBH CALLV 11 XXFFE8H XXFFE9H CALLV 12 XXFFE6H XXFFE7H CALLV 13 XXFFE4H XXFFE5H CALLV 14 XXFFE2H XXFFE3...

Page 602: ...j as an address After operand operation RWj is incremented by the operand size 1 for a byte 2 for a word or 4 for a long word Address bits 16 to 23 are indicated by the data bank register DTB when RW0 or RW1 is used system stack bank register SSB or user stack bank register USB when RW3 is used or additional data bank register ADB when RW2 is used If the post increment results in the address of th...

Page 603: ...ddress that is the 24 low order bits obtained by adding an offset to the contents of general purpose register RLi The offset is 8 bits long and is added as a signed numeric value Figure B 4 4 Example of Long Register Indirect Addressing with Offset RLi disp8 i 0 to 3 MOVW A RW1 0 7 1 6 A D 3 0 F 2 5 3 4 RW1 F F E E 2 5 3 4 A D 3 1 1 F F E E RW1 7 8 DTB 7 8 DTB 78D310H 78D30FH Before execution Afte...

Page 604: ...termined by adding RW0 or RW1 to the contents of general purpose register RW7 Address bits 16 to 23 are indicated by the data bank register DTB Figure B 4 6 Example of Register Indirect Addressing with Base Index RW0 RW7 RW1 RW7 MOVW A PC 20H 0 7 1 6 A 2 5 3 4 C 5 PCB C 5 F F E E 0 0 2 0 MOVW A PC 20H 2 5 3 4 A F F E E PCB C5457BH C5457AH C54559H C54558H 9 E 7 3 C54557H C54556H C5455AH 20H 4 4 5 5...

Page 605: ...instructions Address bits 16 to 23 are indicated by the program bank register PCB Figure B 4 7 Example of Program Counter Relative Branch Addressing rel Register list rlst Specify a register to be pushed onto or popped from a stack Figure B 4 8 Configuration of the Register List BRA 3B20H 3 C 2 0 PC 4 F PCB 3 B 2 0 PC 4 F PCB Before execution After execution Memory space This instruction causes an...

Page 606: ... RW1 RW2 RW3 RW4 RW5 RW6 RW7 0 4 0 3 34FDH 34FCH 34FEH 0 2 0 1 34FBH 34FAH SP 3 4 F E SP 0 1 0 2 RW0 RW1 RW2 RW3 RW4 RW5 RW6 RW7 0 3 0 4 0 4 0 3 34FDH 34FCH 34FEH 0 2 0 1 34FBH 34FAH SP Before execution After execution Memory space Memory space This instruction transfers memory data indicated by the SP to multiple word registers indicated by the register list MOVW A A 0 7 1 6 A 2 5 3 4 DTB F F E E...

Page 607: ...irect specification branch addressing ear The address of the branch destination is the word data at the address indicated by ear Figure B 4 12 Example of Indirect Specification Branch Addressing ear JMP A 6 6 7 7 A 3 B 2 0 6 1 3 C 2 0 PC 4 F PCB 6 6 7 7 A 3 B 2 0 3 B 2 0 PC 4 F PCB 4F3C20H JMP A 4F3B20H Before execution After execution Memory space This instruction causes an unconditional branch b...

Page 608: ...ated by eam Figure B 4 13 Example of Indirect Specification Branch Addressing eam JMP RW0 0 0 3 C 2 0 PC 3 B 2 0 PW0 4 F PCB 3 B 2 0 PC 3 B 2 0 PW0 4 F PCB 4F3C21H 7 3 4F3C20H JMP RW0 4F3B20H Before execution After execution Memory space This instruction causes an unconditional branch by register indirect addressing Next instruction ...

Page 609: ...it bus the program fetches the instruction being executed in word increments Therefore intervening in data access increases the execution cycle count Similarly in the mode of fetching an instruction from memory connected to an 8 bit external bus the program fetches every byte of an instruction being executed Therefore intervening in data access increases the execution cycle count In CPU intermitte...

Page 610: ...ddressing Mode Code Operand a Register access count in each addressing mode Execution cycle count in each addressing mode 00 07 Ri Rwi RLi See the instruction list See the instruction list 08 0B RWj 2 1 0C 0F RWj 4 2 10 17 RWi disp8 2 1 18 1B RWi disp16 2 1 1C 1D 1E 1F RW0 RW7 RW1 RW7 PC disp16 addr16 4 4 2 1 2 2 0 0 a is used for cycle count and B correction value in B 8 F2 MC 16LX Instruction Li...

Page 611: ...1 Cycle count Access count Cycle count Access count Cycle count Access count Internal register 0 1 0 1 0 2 Internal memory Even address 0 1 0 1 0 2 Internal memory Odd address 0 1 2 2 4 4 External data bus 2 16 bit even address 1 1 1 1 2 2 External data bus 2 16 bit odd address 1 1 4 2 8 4 External data bus 2 8 bits 1 1 4 2 8 4 1 b c and d are used for cycle count and B correction value in B 8 F2 ...

Page 612: ...0A RW2 0B RW3 0C RW0 Register indirect with post increment 0 0D RW1 0E RW2 0F RW3 10 RW0 disp8 Register indirect with 8 bit displacement 1 11 RW1 disp8 12 RW2 disp8 13 RW3 disp8 14 RW4 disp8 15 RW5 disp8 16 RW6 disp8 17 RW7 disp8 18 RW0 disp16 Register indirect with 16 bit displacement 2 19 RW1 disp16 1A RW2 disp16 1B RW3 disp16 1C RW0 RW7 Register indirect with index 0 1D RW1 RW7 Register indirec...

Page 613: ...e correction value for CPU intermittent operation B Indicates the correction value used to calculate the actual number of cycles during instruction execution The actual number of cycles during instruction execution can be determined by adding the value in the column to this value Operation Indicates the instruction operation LH Indicates the special operation for bits 15 to 08 of the accumulator Z...

Page 614: ...s of AL and AH AH 16 high order bits of A AL 16 low order bits of A SP Stack pointer USP or SSP PC Program counter PCB Program bank register DTB Data bank register ADB Additional data bank register SSB System stack bank register USB User stack bank register SPB Current stack bank register SSB or USB DPR Direct page register brg1 DTB ADB SSB USB DPR PCB SPB brg2 DTB ADB SSB USB DPR SPB Ri R0 R1 R2 ...

Page 615: ...gn extension of 8 bit immediate data disp8 8 bit displacement disp16 16 bit displacement bp Bit offset vct4 Vector number 0 to 15 vct8 Vector number 0 to 255 b Bit address rel PC relative branch ear Effective addressing code 00 to 07 eam Effective addressing code 08 to 1F rlst Register list Table B 7 2 Explanation on Symbols in the Instruction List 2 2 Symbol Explanation ...

Page 616: ... X MOVX A ear 2 2 1 0 byte A ear X MOVX A eam 2 3 a 0 b byte A eam X MOVX A io 2 3 0 b byte A io X MOVX A imm8 2 2 0 0 byte A imm8 X MOVX A A 2 3 0 b byte A A X MOVX A RWi disp8 2 5 1 b byte A RWi disp8 X MOVX A RLi disp8 3 10 2 b byte A RLi disp8 X MOV dir A 2 3 0 b byte dir A MOV addr16 A 3 4 0 b byte addr16 A MOV Ri A 1 2 1 0 byte Ri A MOV ear A 2 2 1 0 byte ear A MOV eam A 2 3 a 0 b byte eam A...

Page 617: ... 0 word SP A MOVW RWi A 1 2 1 0 word RWi A MOVW ear A 2 2 1 0 word ear A MOVW eam A 2 3 a 0 c word eam A MOVW io A 2 3 0 c word io A MOVW RWi disp8 A 2 5 1 c word RWi disp8 A MOVW RLi disp8 A 3 10 2 c word RLi disp8 A MOVW RWi ear 2 3 2 0 word RWi ear MOVW 2 4 a 1 c word RWi eam MOVW ear Rwi 2 4 2 0 word ear RWi MOVW eam Rwi 2 5 a 1 c word eam RWi MOVW RWi imm16 3 2 1 0 word RWi imm16 MOVW io imm1...

Page 618: ...B eam A 2 5 a 0 2 x b byte eam eam A SUBC A 1 2 0 0 byte A AH AL C Z SUBC A ear 2 3 1 0 byte A A ear C Z SUBC A eam 2 4 a 0 b byte A A eam C Z SUBDC A 1 3 0 0 byte A AH AL C decimal Z ADDW A 1 2 0 0 word A AH AL ADDW A ear 2 3 1 0 word A A ear ADDW A eam 2 4 a 0 c word A A eam ADDW A imm16 3 2 0 0 word A A imm16 ADDW ear A 2 3 2 0 word ear ear A ADDW eam A 2 5 a 0 2 x c word eam eam A ADDCW A ear ...

Page 619: ... 5 a 0 2 x c word eam eam 1 DECW ear 2 3 2 0 word ear ear 1 DECW eam 2 5 a 0 2 x c word eam eam 1 INCL ear 2 7 4 0 long ear ear 1 INCL eam 2 9 a 0 2 x d long eam eam 1 DECL ear 2 7 4 0 long ear ear 1 DECL eam 2 9 a 0 2 x d long eam eam 1 Table B 8 5 11 Compare Instructions byte word long word Mnemonic RG B Operation L H A H I S T N Z V C R M W CMP A 1 1 0 0 byte AH AL CMP A ear 2 2 1 0 byte A ear ...

Page 620: ... 8 0 0 byte AH byte AL word A MULU A ear 2 9 1 0 byte A byte ear word A MULU A eam 2 10 0 b byte A byte eam word A MULUW A 1 11 0 0 word AH word AL Long A MULUW A ear 2 12 1 0 word A word ear Long A MULUW A eam 2 13 0 c word A word eam Long A 1 3 Division by 0 7 Overflow 15 Normal 2 4 Division by 0 8 Overflow 16 Normal 3 6 a Division by 0 9 a Overflow 19 a Normal 4 4 Division by 0 7 Overflow 22 No...

Page 621: ...e A byte ear word A MUL A eam 2 10 0 b byte A byte eam word A MULW A 2 11 0 0 word AH word AL Long A MULW A ear 2 12 1 0 word A word ear Long A MULW A eam 2 13 0 c word A word eam Long A 1 3 Division by 0 8 or 18 Overflow 18 Normal 2 4 Division by 0 11 or 22 Overflow 23 Normal 3 5 a Division by 0 12 a or 23 a Overflow 24 a Normal 4 When dividend is positive 4 Division by 0 12 or 30 Overflow 31 Nor...

Page 622: ...0 2 x b byte eam eam xor A R NOT A 1 2 0 0 byte A not A R NOT ear 2 3 2 0 byte ear not ear R NOT eam 2 5 a 0 2 x b byte eam not eam R ANDW A 1 2 0 0 word A AH and A R ANDW A imm16 3 2 0 0 word A A and imm16 R ANDW A ear 2 3 1 0 word A A and ear R ANDW A eam 2 4 a 0 c word A A and eam R ANDW ear A 2 3 2 0 word ear ear and A R ANDW eam A 2 5 a 0 2 x c word eam eam and A R ORW A 1 2 0 0 word A AH or ...

Page 623: ... 2 6 2 0 long A A xor ear R XORL A eam 2 7 a 0 d long A A xor eam R Table B 8 10 6 Sign Inversion Instructions byte word Mnemonic RG B Operation L H A H I S T N Z V C R M W NEG A 1 2 0 0 byte A 0 A X NEG ear 2 3 2 0 byte ear 0 ear NEG eam 2 5 a 0 2 x b byte eam 0 eam NEGW A 1 2 0 0 word A 0 A NEGW ear 2 3 2 0 word ear 0 ear NEGW eam 2 5 a 0 2 x c word eam 0 eam Table B 8 11 1 Normalization Instruc...

Page 624: ... byte A Arithmetic right shift A 1 bit LSR A R0 2 1 1 0 byte A Logical right barrel shift A R0 LSL A R0 2 1 1 0 byte A Logical left barrel shift A R0 ASRW A 1 2 0 0 word A Arithmetic right shift A 1 bit LSRW A SHRW A 1 2 0 0 word A Logical right shift A 1 bit R LSLW A SHLW A 1 2 0 0 word A Logical left shift A 1 bit ASRW A R0 2 1 1 0 word A Arithmetic right barrel shift A R0 LSRW A R0 2 1 1 0 word...

Page 625: ... Branch on C or Z 0 BRA rel 2 1 0 0 Unconditional branch JMP A 1 2 0 0 word PC A JMP addr16 3 3 0 0 word PC addr16 JMP ear 2 3 1 0 word PC ear JMP eam 2 4 a 0 c word PC eam JMPP ear 3 2 5 2 0 word PC ear PCB ear 2 JMPP eam 3 2 6 a 0 d word PC eam PCB eam 2 JMPP addr24 4 4 0 0 word PC ad24 0 15 PCB ad24 16 23 CALL ear 4 2 6 1 c word PC ear CALL addr16 5 2 7 a 0 2 x c word PC eam CALL eam 4 3 6 0 c ...

Page 626: ...rrupt R S INT addr16 3 16 0 6 x c Software interrupt R S INTP addr24 4 17 0 6 x c Software interrupt R S INT9 1 20 0 8 x c Software interrupt R S RETI 1 8 0 7 Return from interrupt LINK imm8 2 6 0 c Saves the old frame pointer in the stack upon entering the function then sets the new frame pointer and reserves the local pointer area UNLINK 1 5 0 c Recovers the old frame pointer from the stack upon...

Page 627: ...8 MOV ILM imm8 2 2 0 0 byte ILM imm8 MOVEA RWi ear 2 3 1 0 word RWi ear MOVEA RWi eam 2 2 a 1 0 word RWi eam MOVEA A ear 2 1 0 0 word A ear MOVEA A eam 2 1 a 0 0 word A eam ADDSP imm8 2 3 0 0 word SP ext imm8 ADDSP imm16 3 3 0 0 word SP imm16 MOV A brg1 2 1 0 0 byte A brg1 Z MOV brg2 A 2 1 0 0 byte brg2 A NOP 1 1 0 0 No operation ADB 1 1 0 0 Prefix code for AD space access DTB 1 1 0 0 Prefix code ...

Page 628: ...bp rel 4 1 0 b Branch on dir bp b 0 BBC addr16 bp rel 5 1 0 b Branch on addr16 bp b 0 BBC io bp rel 4 2 0 b Branch on io bp b 0 BBS dir bp rel 4 1 0 b Branch on dir bp b 1 BBS addr16 bp rel 5 1 0 b Branch on addr16 bp b 1 BBS io bp rel 4 1 0 b Branch on io bp b 1 SBBS addr16 bp rel 5 3 0 2 x b Branch on addr16 bp b 1 bit 1 WBTS io bp 3 4 0 5 Waits until io bp b 1 WBTC io bp 3 4 0 5 Waits until io ...

Page 629: ... 5 3 byte fill AH AL counter RW0 MOVSW MOVSWI 2 2 5 6 word transfer AH AL counter RW0 MOVSWD 2 2 5 6 word transfer AH AL counter RW0 SCWEQ SCWEQI 2 1 5 7 word search AH AL counter RW0 SCWEQD 2 1 5 7 word search AH AL counter RW0 FILSW FILSWI 2 6m 6 5 6 word fill AH AL counter RW0 1 5 when RW0 is 0 4 7 x RW0 when the counter expires or 7n 5 when a match occurs 2 5 when RW0 is 0 otherwise 4 8 x RW0 ...

Page 630: ...as the NOP instruction that ends in one byte is completed within the basic page An instruction such as the MOVS instruction that requires two bytes recognizes the existence of byte 2 when it references byte 1 and can check the following one byte by referencing the map for byte 2 Figure B 9 2 shows the correspondence between an actual instruction code and instruction map Basic page map Bit operatio...

Page 631: ...nstruction code Some instructions do not contain byte 2 1 The extended page map is a generic name of maps for bit operation instructions character string operation instructions 2 byte instructions and ea instructions Actually there are multiple extended page maps for each type of instructions Table B 9 1 Example of an Instruction Code Instruction Byte 1 from basic page map Byte 2 from extended pag...

Page 632: ...peration instruction Character string opera tion instruction 2 byte instruction ea instruc tion 1 ea instruc tion 2 ea instruc tion 3 ea instruc tion 4 ea instruc tion 5 ea instruc tion 6 ea instruc tion 7 ea instruc tion 8 ea instruc tion 9 Ri ea ...

Page 633: ...617 APPENDIX B Instructions Table B 9 3 Bit Operation Instruction Map first byte 6CH ...

Page 634: ...618 APPENDIX Table B 9 4 Character String Operation Instruction Map first byte 6EH ...

Page 635: ...619 APPENDIX B Instructions Table B 9 5 2 byte Instruction Map first byte 6FH MUL MULW DIVU A A A ...

Page 636: ...620 APPENDIX Table B 9 6 ea Instruction 1 first byte 70H Use prohibited Use prohibited Use prohibited Use prohibited Use prohibited Use prohibited Use prohibited Use prohibited ...

Page 637: ...621 APPENDIX B Instructions Table B 9 7 ea Instruction 2 first byte 71H ...

Page 638: ...622 APPENDIX Table B 9 8 ea Instruction 3 first byte 72H ...

Page 639: ...623 APPENDIX B Instructions Table B 9 9 ea Instruction 4 first byte 73H ...

Page 640: ...624 APPENDIX Table B 9 10 ea Instruction 5 first byte 74H ...

Page 641: ...625 APPENDIX B Instructions Table B 9 11 ea Instruction 6 first byte 75H ...

Page 642: ...626 APPENDIX Table B 9 12 ea Instruction 7 first byte 76H ...

Page 643: ...627 APPENDIX B Instructions Table B 9 13 ea Instruction 8 first byte 77H ...

Page 644: ...628 APPENDIX Table B 9 14 ea Instruction 9 first byte 78H ...

Page 645: ...629 APPENDIX B Instructions Table B 9 15 MOVEA RWi ea Instruction first byte 79H ...

Page 646: ...630 APPENDIX Table B 9 16 MOV Ri ea Instruction first byte 7AH ...

Page 647: ...631 APPENDIX B Instructions Table B 9 17 MOVW RWi ea Instruction first byte 7BH ...

Page 648: ...632 APPENDIX Table B 9 18 MOV Ri ea Instruction first byte 7CH ...

Page 649: ...633 APPENDIX B Instructions Table B 9 19 MOVW ea Rwi Instruction first byte 7DH ...

Page 650: ...634 APPENDIX Table B 9 20 XCH Ri ea Instruction first byte 7EH ...

Page 651: ...635 APPENDIX B Instructions Table B 9 21 XCHW RWi ea Instruction first byte 7FH ...

Page 652: ...diagram for the external pins of the Flash devices in MB90360 series during Flash Memory mode is shown below Data Read by Read Access Figure C 1 Timing Diagram for Read Access AQ16 to AQ0 CE OE WE DQ7 to DQ0 tRC tACC tOE tOEH tCE tDF tOH High Z Address stable Output defined ...

Page 653: ...s the last 2 bus cycle of 4 bus cycle sequences Fx in FxAAAA described as address is any of FF tCH tCS tWP tWHWH1 tWC CE OE tRC AQ18 to AQ0 DQ7 to DQ0 tGHWL tCE tOE tWPH tDS tDH DQ7 PD A0H DOUT DOUT WE FxAAAAH PA PA tOH tAS tAH tDF PA Write address PD Write data DQ7 Reverse output of write data DOUT Output of write data 3rd bus cycle Data polling ...

Page 654: ...he last 2 bus cycle of 4 bus cycle sequences Fx in FxAAAA described as address is any of F AQ18 to AQ0 WE OE CE DQ7 to DQ0 tWC PA tAS tAH PA tWHWH1 tCP tWS tCPH tDH tDS A0H PD DQ7 tGHWL tWH Dout FxAAAAH 3rd bus cycle Data polling PA Write address PD Write data DQ7 Reverse output of write data DOUT Output of write data ...

Page 655: ... Write Access chip erasing sector erasing Notes SA is the sector address at erasing sector The address is FxAAAAH at erasing sector Fx in FxAAAA described as address is any of F AAH SA 55H 80H AAH 55H 10H 30H tAH tAS tGHWL tDH tWPH tWP tCS tDS tVCS AQ18 to AQ0 CE OE WE DQ7 to DQ0 VCC FxAAAAH Fx5555H FxAAAAH FxAAAAH Fx5555H ...

Page 656: ...t Figure C 6 Timing Diagram for Toggle Bit Note DQ6 stops toggling The device terminates automatic operation CE OE WE DQ7 DQ7 DQ6 to DQ0 tOE tCE tCH tOEH tOH tDF tOE High Z DQ7 valid data DQ6 to DQ0 valid data DQ6 to DQ0 flag output tWHWH1 or tWHWH2 CE WE OE tOES tOE tOEH DQ6 Stop toggling Data DQ7 to DQ0 DQ7 to DQ0 valid DQ6 Toggle DQ6 Toggle ...

Page 657: ...riting erasing Figure C 7 Timing Diagram for Output of RY BY Signal during Writing erasing RST and RY BY Timing Figure C 8 Timing Diagram for Output of RY BY Signal at Hardware Reset CE WE RY BY tBUSY Rising edge of last write pulse Writing or erasing CE RY BY RST tRP tReady ...

Page 658: ...tor Protect Figure C 9 Enable Sector Protect verify Sector Protect AQ18 to AQ9 AQ8 AQ2 AQ1 MD0 MD2 OE WE CE DQ7 to DQ0 SAX SAY AQ8 AQ2 AQ1 0 1 0 12 V 5 V 12 V 5 V 01H tOE tVLHT tVLHT tWPP tOESP tCSP SAX First sector address SAY Next sector address ...

Page 659: ...43 APPENDIX C Timing Diagrams in Flash Memory Mode Temporary Sector Protect Cancellation Figure C 10 Temporary Sector Protect Cancellation MD1 CE WE RY BY 12 V 5 V tVLHT 5 V Write erase command sequence ...

Page 660: ...3 CAN1 RX ICR01 0000B1H FFFFC8H FFFFC9H FFFFCAH Unused INT 14 CAN1 TX NS FFFFC4H FFFFC5H FFFFC6H Unused INT 15 Reserved ICR02 0000B2H FFFFC0H FFFFC1H FFFFC2H Unused INT 16 Reserved FFFFBCH FFFFBDH FFFFBEH Unused INT 17 Reserved ICR03 0000B3H FFFFB8H FFFFB9H FFFFBAH Unused INT 18 Reserved FFFFB4H FFFFB5H FFFFB6H Unused INT 19 16 bit reloadtimer2 ICR04 0000B4H FFFFB0H FFFFB1H FFFFB2H Unused INT 20 1...

Page 661: ... INT 39 Reserved ICR14 0000BEH FFFF60H FFFF61H FFFF62H Unused INT 40 Reserved FFFF5CH FFFF5DH FFFF5EH Unused INT 41 Flash Memory ICR15 0000BFH FFFF58H FFFF59H FFFF5AH Unused INT 42 Delayed interrupt module FFFF54H FFFF55H FFFF56H Unused INT 43 FFFF50H FFFF51H FFFF52H Unused INT 254 FFFC04H FFFC05H FFFC06H Unused INT 255 FFFC00H FFFC01H FFFC02H Unused When PCB is FFH the vector area for the CALLV i...

Page 662: ...000B1H CAN 1 TX NS N 14 FFFFC4H Reserved N 15 FFFFC0H ICR02 0000B2H Reserved N 16 FFFFBCH Reserved N 17 FFFFB8H ICR03 0000B3H Reserved N 18 FFFFB4H 16 bit reload timer 2 Y1 19 FFFFB0H ICR04 0000B4H 16 bit reload timer 3 Y1 20 FFFFACH Reserved N 21 FFFFA8H ICR05 0000B5H Reserved N 22 FFFFA4H PPG C D N 23 FFFFA0H ICR06 0000B6H PPG E F N 24 FFFF9CH Time base timer N 25 FFFF98H ICR07 0000B7H External ...

Page 663: ...ile one interrupt is enabled the other interrupt must be disabled UART 1 RX Y2 37 FFFF68H ICR13 0000BDH UART 1 TX Y1 38 FFFF64H Reserved N 39 FFFF60H ICR14 0000BEH Reserved N 40 FFFF5CH Flash memory N 41 FFFF58H ICR15 0000BFH Delayed interrupt generation module N 42 FFFF54H Y1 An EI2OS interrupt clear signal or EI2OS register read access clears the interrupt request flag Y2 An EI2OS interrupt clea...

Page 664: ...648 APPENDIX ...

Page 665: ...649 INDEX INDEX The index follows on the next page This is listed in alphabetic order ...

Page 666: ...g State of 16 bit Timer Register 253 Operation as 16 bit Timer Register Underflows 255 260 24 bit Operand 24 bit Operand Specification 33 512K bit Flash Memory 512K bit Flash Memory Features 530 Sector Configuration of the 512K bit Flash Memory 531 8 8 bit PPG Setting for 8 8 bit PPG Output Operation Mode 307 8 10 bit A D Converter 8 10 bit A D Converter Interrupt and EI2 OS 358 A D converted Data...

Page 667: ... ADCS MD1 MD0 11B 359 Single shot Conversion Mode ADCS MD1 MD0 00B or 01B 359 Address Detection Control Register Address Detection Control Register 0 PACSR0 509 Address Detection Control Register 1 PACSR1 511 Address Match Detection Block Diagram of Address Match Detection Function 507 List of Registers and Reset Values of Address Match Detection Function 508 Operation of Address Match Detection F...

Page 668: ...ng Bus Operation Stop HALT 1 457 State during Bus Operation Stop HALT 1 457 BVAL Caution for Disabling Message Buffers By BVAL Bits 503 BY Timing RST and RY BY Timing 641 RY BY Timing during Writing erasing 641 C CAN Controller Block Diagram of CAN Controller 445 Canceling Transmission Request from CAN Controller 488 Features of CAN Controller 444 Reception Flowchart of the CAN Controller 493 Star...

Page 669: ...nversion Mode 361 Pause conversion Mode ADCS MD1 MD0 11B 359 Setting of Continuous Conversion Mode 362 Setting of Pause conversion Mode 364 Setting of Single shot Conversion Mode 360 Single shot Conversion Mode ADCS MD1 MD0 00B or 01B 359 Counting Example Counting Example 417 CPU Outline of CPU Memory Space 29 Outline of the CPU 28 CPU Intermittent Operating Mode CPU Intermittent Operating Mode 13...

Page 670: ...er DIRR 87 DIV Precautions for Use of DIV A Ri and DIVW A RWi Instructions 52 Use of the DIV A Ri and DIVW A RWi Instructions without Precautions 53 DIVW Precautions for Use of DIV A Ri and DIVW A RWi Instructions 52 Use of the DIV A Ri and DIVW A RWi Instructions without Precautions 53 DLC Registers List of Message Buffers DLC Registers and Data registers 450 DQ5 Timing Limit Exceeded Flag DQ5 54...

Page 671: ...ligent I O Service Descriptor ISD 76 Extended Status control Register Extended Status control Register ESCR 401 External Clock Connection of an Oscillator or an External Clock to the Microcontroller 108 External Interrupt Block Diagram of DTP External Interrupt 315 DTP External Interrupt Enable Register ENIR1 321 DTP External Interrupt Factor Register EIRR1 319 DTP External Interrupt Function 314 ...

Page 672: ...rupt 67 Hardware Sequence Flags Hardware Sequence Flags 539 I I O Area I O Area 30 I O Maps I O Maps 00XX Addresses 568 I O Pins Status of I O Pins Single chip Mode 156 I O Port I O Port Registers 169 I O Ports 168 I O Timer 16 bit I O Timer Interrupt and EI2 OS 228 Block Diagram of 16 bit I O Timer 211 Functions of 16 bit I O Timer 210 Generation of Interrupt Request from 16 bit I O Timer 216 Int...

Page 673: ...ration and Flag Set Timing 409 Restrictions on Interrupt Disable Instructions and prefix Instructions 51 Software Interrupt Operation 72 Software Interrupts 57 72 Structure of Hardware Interrupt 67 Structure of Software Interrupts 72 Transmission Interrupt Generation and Flag Set Timing 411 Watch Timer Interrupt 275 Watch Timer Interrupt and EI2 OS Transfer Function 275 Interrupt Causes Interrupt ...

Page 674: ...nter the Standby Mode 158 LPMCR Low Power Consumption Mode Control Register LPMCR 139 Notes on Accessing the Low Power Consumption Mode Control Register LPMCR to Enter the Standby Mode 158 LVRC Low Voltage CPU Operating Detection Reset Control Register LVRC 376 M Machine Clock Machine Clock 104 Mask ROM Block Diagram of Flash Mask ROM Version 11 Master slave Communication Master slave Communicatio...

Page 675: ...lock Supply of Operation Clock 191 Operation Enable Bit Operation Enable Bit 421 Operation Mode CPU Intermittent Operation Mode 142 Operation in Asynchronous LIN Mode operation mode 3 429 Operation in Synchronous Mode operation mode 2 426 Operation Modes of 16 bit Reload Timer 238 Setting for 16 bit PPG Output Operation Mode 304 Setting for 8 8 bit PPG Output Operation Mode 307 Setting for 8 bit P...

Page 676: ...r 299 Interrupts of 8 16 bit PPG Timer 299 List of Registers and Reset Values of 8 16 bit PPG Timer 291 Operation Modes of 8 16 bit PPG Timer 283 Operation of 8 16 bit PPG Timer 300 Pins of 8 16 bit PPG Timer 290 Precautions when Using 8 16 bit PPG Timer 310 PPGC Operation Mode Control Register PPGC Operation Mode Control Register PPGCC 292 PPGC D Count Clock Select Register PPGC D Count Clock Sel...

Page 677: ...it Reload Timer 242 Precautions when Using 16 bit Reload Timer 262 Setting of 16 bit Reload Timer 252 Remote Frame Processing for Reception of Data Frame and Remote Frame 491 Reset 16 bit Reload Timer Registers and Reset Value 243 Block Diagrams of the External Reset Pin 125 Causes of a Reset 120 Clock Selection Register and List of Reset Value 97 List of Registers and Reset Values 86 List of Regi...

Page 678: ... 557 Serial Status Register Serial Status Register SSR 397 Setting Setting for 16 bit PPG Output Operation Mode 304 Signal Mode Signal Mode 421 Single Clock Sub clock Mode with External Single Clock Product 116 Single chip Mode Status of I O Pins Single chip Mode 156 Single shot Conversion Mode Operation of Single shot Conversion Mode 361 Setting of Single shot Conversion Mode 360 Single shot Conv...

Page 679: ...er Control Register TBTC 185 Timebase Timer Mode Return from Timebase Timer Mode 150 Switching to the Timebase Timer Mode 150 Timer Control Status Register Timer Control Status Register Lower TCCSL 218 Timer Control Status Register Upper TCCSH 217 Timer Control Status Registers High TMCSR H 245 Timer Control Status Registers Low TMCSR L 247 Timer Data Register Timer Data Register TCDT 220 Timer Re...

Page 680: ...Enable Sector Protect verify Sector Protect 642 W Watch Mode Return from Watch Mode 148 Switching to the Watch Mode 148 Watch Timer Block Diagram of Watch Timer 270 Generation of Interrupt Request from Watch Timer 272 List of Registers and Reset Values of Watch Timer 272 Program Example of Watch Timer 278 Watch Timer Counter 276 Watch Timer Interrupt 275 Watch Timer Interrupt and EI2 OS Transfer F...

Page 681: ...1E FUJITSU SEMICONDUCTOR CONTROLLER MANUAL F2MCTM 16LX 16 BIT MICROCONTROLLER MB90360 Series HARDWARE MANUAL April 2005 the first edition Published FUJITSU LIMITED Electronic Devices Edited Business Promotion Dept ...

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