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CHAPTER 8 LOW-POWER CONSUMPTION MODE
Table 8.3-1 Functions of Low-power Consumption Mode Control Register (LPMCR)
Bit name
Function
bit7
STP:
Stop mode bit
This bit transits to the stop mode.
When the bit is set to "0": No effect.
When the bit is set to "1": The CPU enters the stop mode.
Read: "0" is always read.
•
The bit is initialized to "0" when a reset or external interrupt occurs.
bit6
SLP:
Sleep mode bit
This bit shift to sleep mode
When the bit is set to "0": No effect.
When the bit is set to "1": The CPU enters the sleep mode.
Read: "0" is always read.
•
The bit is initialized to "0" when a reset or external interrupt occurs.
•
When the STP and SLP bits are set to "1" at the same time, the STP bit
supersedes the SLP bit, causing a transition to stop mode.
bit5
SPL:
Pin state specification bit
The bit is used to set the state of input/output pins after transition to the stop
mode, watch mode, or timebase timer mode.
When the bit is set to "0": The current level of input/output pins is held.
When the bit is set to "1": The I/O pins enter a high impedance state.
•
The bit is initialized to "0" at a reset.
bit4
RST:
Internal reset signal
generation bit
This bit generates software reset.
When the bit is set to "0": An internal reset signal for three machine cycles
is generated.
When the bit is set to "1": No effect
Read: "1" is always read.
bit3
TMD:
Watch mode bit
This bit shift to watch mode or timebase timer mode
When the bit is set to "0": If the main clock mode or PLL clock mode is
used, the bit transits to the timebase timer mode.
If the sub-clock mode is used, the bit transits to
the watch mode.
When the bit is set to "1": No effect
•
The bit is set to "1" when a reset or interrupt occurs.
Read: "1" is always read.
bit1
bit2
CG1, CG0:
CPU suspended cycle
number select bits
These bits are used to set the halt cycle count of the CPU clock in the CPU
intermittent operation mode.
•
Any reset causes the bit to return to the reset value.
bit0
Reserved: reserved bit
Always set this bit to "0".
Summary of Contents for F2MCTM-16LX
Page 2: ......
Page 3: ...FUJITSU LIMITED F2MCTM 16LX 16 BIT MICROCONTROLLER MB90360 Series HARDWARE MANUAL ...
Page 4: ......
Page 42: ...26 CHAPTER 1 OVERVIEW ...
Page 70: ...54 CHAPTER 2 CPU ...
Page 134: ...118 CHAPTER 6 CLOCK SUPERVISOR ...
Page 176: ...160 CHAPTER 8 LOW POWER CONSUMPTION MODE ...
Page 194: ...178 CHAPTER 10 I O PORTS ...
Page 252: ...236 CHAPTER 13 16 Bit I O TIMER ...
Page 282: ...266 CHAPTER 14 16 BIT RELOAD TIMER ...
Page 296: ...280 CHAPTER 15 WATCH TIMER ...
Page 386: ...370 CHAPTER 18 8 10 BIT A D CONVERTER ...
Page 426: ...410 CHAPTER 20 LIN UART Figure 20 5 2 ORE Flag Set Timing RDRF ORE Reception data ...
Page 540: ...524 CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION ...
Page 568: ...552 CHAPTER 24 512K BIT FLASH MEMORY ...
Page 633: ...617 APPENDIX B Instructions Table B 9 3 Bit Operation Instruction Map first byte 6CH ...
Page 634: ...618 APPENDIX Table B 9 4 Character String Operation Instruction Map first byte 6EH ...
Page 637: ...621 APPENDIX B Instructions Table B 9 7 ea Instruction 2 first byte 71H ...
Page 638: ...622 APPENDIX Table B 9 8 ea Instruction 3 first byte 72H ...
Page 639: ...623 APPENDIX B Instructions Table B 9 9 ea Instruction 4 first byte 73H ...
Page 640: ...624 APPENDIX Table B 9 10 ea Instruction 5 first byte 74H ...
Page 641: ...625 APPENDIX B Instructions Table B 9 11 ea Instruction 6 first byte 75H ...
Page 642: ...626 APPENDIX Table B 9 12 ea Instruction 7 first byte 76H ...
Page 643: ...627 APPENDIX B Instructions Table B 9 13 ea Instruction 8 first byte 77H ...
Page 644: ...628 APPENDIX Table B 9 14 ea Instruction 9 first byte 78H ...
Page 645: ...629 APPENDIX B Instructions Table B 9 15 MOVEA RWi ea Instruction first byte 79H ...
Page 646: ...630 APPENDIX Table B 9 16 MOV Ri ea Instruction first byte 7AH ...
Page 647: ...631 APPENDIX B Instructions Table B 9 17 MOVW RWi ea Instruction first byte 7BH ...
Page 648: ...632 APPENDIX Table B 9 18 MOV Ri ea Instruction first byte 7CH ...
Page 649: ...633 APPENDIX B Instructions Table B 9 19 MOVW ea Rwi Instruction first byte 7DH ...
Page 650: ...634 APPENDIX Table B 9 20 XCH Ri ea Instruction first byte 7EH ...
Page 651: ...635 APPENDIX B Instructions Table B 9 21 XCHW RWi ea Instruction first byte 7FH ...
Page 664: ...648 APPENDIX ...
Page 665: ...649 INDEX INDEX The index follows on the next page This is listed in alphabetic order ...
Page 682: ......