Fujitsu F2MCTM-16LX, Hardware Manual

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21.4.17 Reception Complete Register (RCR)
At completion of storing received message in the message buffer (x), RCx becomes 1.
If RIEx of the reception complete interrupt enable register (RIER) is 1, an interrupt
occurs.
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Register Configuration
Figure 21.4-17 Configuration of the Reception Complete Register (RCR)
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Register Function
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Conditions for RCx = 0
Write 0 to RCx.
After completion of handling received message, write 0 to RCx to set it to 0. Writing 1 to RCx is ignored.
1 is read when a Read Modify Write instruction is performed.
Note:
If setting to 1 by completion of the receive operation and clearing to 0 by writing occur at the same
time, the bit is set to 1.
Address bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 RCR1(Upper)
CAN1: 000089
H
RC15 RC14 RC13 RC12 RC11 RC10 RC9 RC8 Reset value
0 0 0 0 0 0 0 0
B
R/W R/W R/W R/W R/W R/W R/W R/W
Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 RCR1(Lower)
CAN1: 000088
H
RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 Reset value
0 0 0 0 0 0 0 0
B
R/W R/W R/W R/W R/W R/W R/W R/W
R/W : Read/Write