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CHAPTER 20 LIN-UART
20.7.6
Master-Slave Communication Function (Multiprocessor
Mode)
LIN-UART communication with multiple CPUs connected in master-slave mode is
available for both master or slave systems in the operation mode 1.
■
Master-slave Communication Function
The settings shown in Figure 20.7-13 are required to operate LIN-UART in multiprocessor mode
(operation mode 1).
Figure 20.7-13 Settings for LIN-UART Operation Mode 1
●
Inter-CPU connection
As shown in Figure 20.7-14 , a communication system consists of one master CPU and multiple slave
CPUs connected to two communication lines. LIN-UART can be used for the master or slave CPU.
Figure 20.7-14 Connection Example of LIN-UART Master-slave Communication
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
PEN
P
SBL
CL
AD
CRE RXE TXE MD1 MD0 OTO EXT
REST UPCL SCKE
SOE
PE
ORE FRE
RDRF TDRE
BDS RIE
TIE
LBIE LBD LBL1
SOPE
SIOP CCO
SCES
LBR
MS
SCDE
SSM
RBI
TBI
LBL0
Set conversion data (during writing)
Retain reception data (during reading)
SCRn, SMRn
SSRn, TDRn/RDRn
ESCRn, ECCRn
: Used bit
: Unused bit
: Set 1
: Set 0
: Bit automatically set to correct value
n = 0, 1
Mode 1
Mode 1
Mode 1
SOT
SIN
SOT
SIN
SOT
SIN
Master CPU
Slave CPU#0
Slave CPU#1
Summary of Contents for F2MCTM-16LX
Page 2: ......
Page 3: ...FUJITSU LIMITED F2MCTM 16LX 16 BIT MICROCONTROLLER MB90360 Series HARDWARE MANUAL ...
Page 4: ......
Page 42: ...26 CHAPTER 1 OVERVIEW ...
Page 70: ...54 CHAPTER 2 CPU ...
Page 134: ...118 CHAPTER 6 CLOCK SUPERVISOR ...
Page 176: ...160 CHAPTER 8 LOW POWER CONSUMPTION MODE ...
Page 194: ...178 CHAPTER 10 I O PORTS ...
Page 252: ...236 CHAPTER 13 16 Bit I O TIMER ...
Page 282: ...266 CHAPTER 14 16 BIT RELOAD TIMER ...
Page 296: ...280 CHAPTER 15 WATCH TIMER ...
Page 386: ...370 CHAPTER 18 8 10 BIT A D CONVERTER ...
Page 426: ...410 CHAPTER 20 LIN UART Figure 20 5 2 ORE Flag Set Timing RDRF ORE Reception data ...
Page 540: ...524 CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION ...
Page 568: ...552 CHAPTER 24 512K BIT FLASH MEMORY ...
Page 633: ...617 APPENDIX B Instructions Table B 9 3 Bit Operation Instruction Map first byte 6CH ...
Page 634: ...618 APPENDIX Table B 9 4 Character String Operation Instruction Map first byte 6EH ...
Page 637: ...621 APPENDIX B Instructions Table B 9 7 ea Instruction 2 first byte 71H ...
Page 638: ...622 APPENDIX Table B 9 8 ea Instruction 3 first byte 72H ...
Page 639: ...623 APPENDIX B Instructions Table B 9 9 ea Instruction 4 first byte 73H ...
Page 640: ...624 APPENDIX Table B 9 10 ea Instruction 5 first byte 74H ...
Page 641: ...625 APPENDIX B Instructions Table B 9 11 ea Instruction 6 first byte 75H ...
Page 642: ...626 APPENDIX Table B 9 12 ea Instruction 7 first byte 76H ...
Page 643: ...627 APPENDIX B Instructions Table B 9 13 ea Instruction 8 first byte 77H ...
Page 644: ...628 APPENDIX Table B 9 14 ea Instruction 9 first byte 78H ...
Page 645: ...629 APPENDIX B Instructions Table B 9 15 MOVEA RWi ea Instruction first byte 79H ...
Page 646: ...630 APPENDIX Table B 9 16 MOV Ri ea Instruction first byte 7AH ...
Page 647: ...631 APPENDIX B Instructions Table B 9 17 MOVW RWi ea Instruction first byte 7BH ...
Page 648: ...632 APPENDIX Table B 9 18 MOV Ri ea Instruction first byte 7CH ...
Page 649: ...633 APPENDIX B Instructions Table B 9 19 MOVW ea Rwi Instruction first byte 7DH ...
Page 650: ...634 APPENDIX Table B 9 20 XCH Ri ea Instruction first byte 7EH ...
Page 651: ...635 APPENDIX B Instructions Table B 9 21 XCHW RWi ea Instruction first byte 7FH ...
Page 664: ...648 APPENDIX ...
Page 665: ...649 INDEX INDEX The index follows on the next page This is listed in alphabetic order ...
Page 682: ......