Epson S5U1C17001C, Manual

Page: 634 / 742

S5U1C17001C ManUal
EPSOn
11-7
(C COMPilEr PaCkagE fOr S1C17 faMily) (Ver. 1.5.0)
11 OTHEr TOOlS
11
Tools
11.1.5 Macro Definition and reference
You can define a character string as a macro in a make file and can refer to defined character strings using the
macro names. The following shows the formats in which a macro can be defined and referenced.
Definition: <macro name>
=
<character string>
Reference:
$(
<macro name>
)
Example:
TARGET= sample
:
TOOL_DIR = /cygdrive/c/EPSON/gnu17
:
LD= $(TOOL_DIR)/ld
LIB_DIR= $(TOOL_DIR)/lib
:
LDFLAGS= -T $(TARGET).lds -Map $(TARGET).map -N
:
OBJS= boot.o \
main.o \
:
OBJLDS=
:
LIBS= $(LIB_DIR)/libc.a $(LIB_DIR)/libgcc.a
:
$(LD) $(LDFLAGS) -o $@ $(OBJS) $(OBJLDS) $(LIBS)
The last line that refers macros in the example above is a command line to invoke the linker. If the macros have
been defined as the example, this line will be executed after the macro names are replaced as below.
/cygdrive/c/EPSON/gnu17/ld -T sample.lds -Map sample.map -N -o sample.elf boot.o main.o
/cygdrive/c/EPSON/gnu17/lib/libc.a /cygdrive/c/EPSON/gnu17/lib/libgcc.a
Predefined macros
$@
used in the example above is a predefined macro. The following three predefined macros are available.
Note, however, that they can be used only in the command lines in dependency lists.
$@
This will be replaced with the target file name (including the extension) currently being processed.
Example:
sample.elf : . . .
ld -o $@ . . .
(=
ld -o sample.elf
. . .)
$*
This will be replaced with the target file name (not including the extension) currently being processed.
Example:
sample.elf : . . .
ld $*.o . . .
(=
ld sample.o
. . .)
$<
This will be replaced with the first dependency file (including the extension) of the target currently being
processed.
Example:
main.o : main.c
...
xgcc -o $@ $<
(
= xgcc -o main.o main.c
)
Precaution
When the same macro name is defined twice or more, the newest defined macro is effective.