21 I
2
S
S1C33L26 TECHNICAL MANUAL
Seiko Epson Corporation
21-21
Setting OEIE to 1 enables I
2
S FIFO one empty interrupt requests to the ITC. Setting it to 0 disables in-
terrupts.
Note: Always be sure to select only one interrupt mode by setting one of the interrupt enable bit (WEIE,
HEIE, or OEIE).
I
2
S FIFO Register (I2S_FIFO)
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
I
2
S FIFO
Register
(I2S_FIFO)
0x301410
(16 bits)
D15–0 I2SFIFO
[31:0]
I
2
S FIFO (L-channel output data)
0 to 0xffffffff
0x0
W 0 when being read.
0x301412
(16 bits)
D15–0
I
2
S FIFO (R-channel output data)
D[15:0] I2SFIFO[15:0]: I
2
S FIFO (Output Data) Bits
Write audio data to the FIFO through this address.
Up to four stereo data (16 bits
×
2 channels (L & R)
×
4) can be written to the FIFO. Once the FIFO be-
comes absolutely empty, the I
2
S module stops shifting audio data and waits until the FIFO becomes full
with four stereo data.
Example:
After the I
2
S module starts by setting I2SSTART to 1, the FIFO becomes absolutely empty.
During audio playing, the interrupt handler may not be invoked in time and the FIFO may become
absolutely empty.
In these cases, the I
2
S module enters INIT/EMPTY state and does not shift out data until the FIFO
becomes full by the interrupt handler or DMA transfer.
When writing data in the interrupt handler routine
When writing data in the interrupt handler routine, use a 16-bit memory write (
ld.h [%rb],%rs
)
instruction or a 32-bit memory write (
ld.w [%rb],%rs
) instruction. Note that 8-bit memory
write instructions cannot be used.
When using a 16-bit memory write (
ld.h [%rb],%rs
) instruction, first write L-channel data to
address 0x301410, then R-channel data to address 0x301412. Both channel data must be written as
a pair even if “mono” is selected as the output channel mode.
Write the first to fourth data to the same addresses (0x301410, 0x301412) without changing.
When using a 32-bit memory write (
ld.w [%rb],%rs
) instruction, write both L-channel data
(low-order 16 bits) and R-channel data (high-order 16 bits) to address 0x301410 with a single 32-
bit memory write instruction.
Write the first to fourth data to the same address (0x301410) without changing.
When writing data via DMAC
When L-channel and R-channel audio data are sequentially stored in a memory area, use a DMAC
channel (Ch.0 or Ch.1) and perform 32-bit data transfer to write both L (low-order 16 bits) and R
(high-order 16 bits) data to address 0x301410 (fixed) for each DMA request. Note that 16-bit and
8-bit data transfer cannot be specified.
When L-channel and R-channel audio data are stored in different locations, use DMAC Ch.0 and
Ch.1. In this case, perform 16-bit data transfer to write L-channel data to address 0x301410 (fixed)
using DMAC Ch.0 and to write R-channel data to address 0x301412 (fixed) using DMAC Ch.1.
The I
2
S one-empty DMA request is sent to DMAC Ch.0 and Ch.1 simultaneously. However, DMAC
Ch.0 starts a DMA transfer first as it priority over Ch.1. Therefore, DMAC Ch.0 must be used for
L-channel data transfer. Note that 8-bit and 32-bit data transfer cannot be specified when dual DMA
channels are used.
