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11 CACHE CONTROLLER (CCU)

11-6

Seiko Epson Corporation

S1C33L26 TECHNICAL MANUAL

If a higher priority interrupt occurs while an interrupt handler routine is being executed, the cache lock is
released as IL[2:0] is altered. In this case, the cache will be locked again after the handler routine for the higher

priority interrupt ends by the reti instruction as IL[2:0] returns to level 1.

Example 2: When all the LKPRI[7:0] bits to 1 (0xff)

The cache is locked immediately after this setting, then no refilling will occur. When no cached data is hit, the
program is executed at the store location in the memory. If LKPRI[7:0] is altered and the bit corresponding to
the interrupt level set in IL[2:0] is reset to 0, the cache lock is released.

Read ICLKS/CCU_STAT register and DCLKS/CCU_STAT register to check whether the instruction and data cach-
es are locked or not. If the status bit is 1, the cache is locked. If the bit is 0, the cache is not locked.
To release the lock status, set all the LKPRI[7:0] bits to 0.

Caching Operation during Debugging

11.5

In debugging mode, the automatic lock function works on both the instruction cache and the data cache.
To execute the program in debugging mode with the same timings and performance as normal operating mode, set
SBRK/CCU_CFG register to 0 and use only the hardware PC break function for suspending program execution.
Setting SBRK to 1 (default) allows use of both hardware PC break and software PC break. However, execution tim-
ings and performance will not be the same as those in normal operating mode.

Note: When SBRK is set to 0, a software PC break point cannot be set in the a target area for caching.

Cache Data Integrity

11.6

The CCU does not support a snooping function (for maintaining the data in the cache memory to match those in the
external memory). The cache and the external memory are maintained in synch if reading/writing is only executed
in the C33 PE Core. When data are transferred to the area subject to caching via DMAC or when data are written to
the program area subject to caching by the CPU, flush the cache or otherwise ensure data integrity using software.

Control Register Details

11.7

7.1 List of CCU Registers

Table 11.

Address

Register name

Function

0x302300 CCU_CFG

Cache Configuration Register

Enable instruction and data caches

0x302304 CCU_AREA

Cacheable Area Select Register

Select cacheable areas

0x302308 CCU_LK

Cache Lock Register

Configure cache lock function

0x30230c CCU_STAT

Cache Status Register

Indicate cache statuses

0x302318 CCU_WB_STAT

Cache Write Buffer Status Register

Indicate write buffer status

0x302360 CCU_CCLKDV

CCLK Division Ratio Select Register

Set CCLK clock frequency.

The following describes each CCU register. These are all 32-bit registers.

Note: When data is written to the registers, the “Reserved” bits must always be written as 0 and not 1.

Cache Configuration Register (CCU_CFG)

Register name Address

Bit

Name

Function

Setting

Init. R/W

Remarks

Cache
Configuration
Register
(CCU_CFG)

0x302300

(32 bits)

D31–9 –

reserved

–

–

–

0 when being read.

D8

WBEN

Write buffer enable

1 Enable

0 Disable

1

R/W

D7–4 –

reserved

–

–

–

0 when being read.

D3

–

reserved

–

–

–

Do not set to 1.

D2

SBRK

Software break enable

1 Enable

0 Disable

1

R/W

D1

IC

Instruction cache enable

1 Enable

0 Disable

0

R/W

D0

DC

Data cache enable

1 Enable

0 Disable

0

R/W

D[31:9] Reserved

D8

WBEN: Write Buffer Enable Bit

Enables the write buffer.

1 (R/W): Enabled (default)

0 (R/W): Disabled

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Summary of Contents for S1C33L26

Page 1: ...Rev 1 1 CMOS 32 BIT SINGLE CHIP MICROCONTROLLER S1C33L26 Technical Manual ...

Page 2: ...igh level reliability such as medical prod ucts Moreover no license to any intellectual property rights is granted by implication or otherwise and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party This material or portions thereof may contain technology or the subject relating to strate...

Page 3: ... not fixed Specification Package D die form F QFP B BGA Model number Model name C microcomputer digital products Product classification S1 semiconductor Development tools S5U1 C 33000 H2 1 Packing specifications 00 standard packing Version 1 Version 1 Tool type Hx ICE Dx Evaluation board Ex ROM emulation board Mx Emulation memory for external ROM Tx A socket for mounting Cx Compiler package Sx Mid...

Page 4: ...Area 3 IVRAM DSTRAM 3 3 3 4 1 IVRAM 3 3 3 4 2 DSTRAM 3 3 3 5 Area 6 I O Area 3 4 3 6 External Memory Area 3 4 3 7 Bus Masters and Accessible Memories 3 4 3 8 Memory Access Rate 3 4 4 Power Supply 4 1 4 1 Power Supply Pins 4 1 4 2 Operating Voltage LVDD 4 2 4 3 Power Supply for PLL PLLVDD PLLVSS 4 2 4 4 Power Supply for RTC RTCVDD 4 2 4 5 I O Interface Voltage HVDD 4 2 4 6 Power Supply for Analog C...

Page 5: ...dule Clock LCLK 6 13 6 7 6 SRAMC and SDRAMC Clock SDCLK 6 13 6 7 7 USB Clocks USBCLK USBREGCLK 6 14 6 8 Clock External Output CMU_CLK 6 14 6 9 Standby Modes 6 15 6 9 1 HALT Mode 6 15 6 9 2 SLEEP Mode 6 15 6 10 Control Register Details 6 16 Clock Source Select Register CMU_OSCSEL 6 16 Oscillation Control Register CMU_OSCCTL 6 17 LCDC Clock Division Ratio Select Register CMU_LCLKDIV 6 18 Clock Contr...

Page 6: ...SRAMC 9 1 9 1 SRAMC Module Overview 9 1 9 2 SRAMC Pins 9 1 9 3 SRAMC Operating Clock 9 2 9 4 External Memory Areas 9 2 9 4 1 Chip Enable Signals 9 3 9 4 2 Area Condition Settings 9 3 9 5 Connection of External Devices and Bus Operation 9 5 9 5 1 Connecting External Devices 9 5 9 5 2 Data Configuration in Memory 9 5 9 5 3 External Bus Operation 9 6 9 6 Bus Access Timing Charts 9 7 9 6 1 SRAM Read W...

Page 7: ...6 11 6 Cache Data Integrity 11 6 11 7 Control Register Details 11 6 Cache Configuration Register CCU_CFG 11 6 Cacheable Area Select Register CCU_AREA 11 7 Cache Lock Register CCU_LK 11 8 Cache Status Register CCU_STAT 11 8 Cache Write Buffer Status Register CCU_WB_STAT 11 9 CCLK Division Ratio Select Register CCU_CCLKDV 11 10 12 Interrupt Controller ITC 12 1 12 1 ITC Module Overview 12 1 12 2 Vect...

Page 8: ... 14 7 T8 Ch x Reload Data Registers T8_TRx 14 7 T8 Ch x Counter Data Registers T8_TCx 14 8 T8 Ch x Control Registers T8_CTLx 14 8 T8 Ch x Interrupt Control Registers T8_INTx 14 9 15 16 bit PWM Timer T16A5 15 1 15 1 T16A5 Module Overview 15 1 15 2 T16A5 Input Output Pins 15 2 15 3 Count Clock 15 2 15 4 T16A5 Operating Modes 15 3 15 4 1 Comparator Mode and Capture Mode 15 3 15 4 2 Repeat Mode and On...

Page 9: ... 16 12 T16P Running Control Register T16P_RUN 16 14 T16P Internal Clock Control Register T16P_CLK 16 15 T16P Interrupt Control Register T16P_INT 16 15 17 Watchdog Timer WDT 17 1 17 1 WDT Module Overview 17 1 17 2 WDT Input Output Pins 17 1 17 3 WDT Operating Clock 17 2 17 4 Control of the Watchdog Timer 17 2 17 4 1 Setting Up the Watchdog Timer 17 2 17 4 2 Starting Stopping the Watchdog Timer 17 3...

Page 10: ...aster Slave Mode Interrupt Flag Register USI_SIF 18 30 USI I2C Master Mode Trigger Register USI_IMTG 18 31 USI I2C Master Mode Interrupt Enable Register USI_IMIE 18 32 USI I2C Master Mode Interrupt Flag Register USI_IMIF 18 32 USI I2C Slave Mode Trigger Register USI_ISTG 18 33 USI I2C Slave Mode Interrupt Enable Register USI_ISIE 18 34 USI I2C Slave Mode Interrupt Flag Register USI_ISIF 18 35 18 9...

Page 11: ...guration Register USIL_LSCFG 19 44 USIL LCD SPI Mode Interrupt Enable Register USIL_LSIE 19 45 USIL LCD SPI Mode Interrupt Flag Register USIL_LSIF 19 45 USIL LCD SPI Mode Data Configuration Register USIL_LSDCFG 19 46 USIL LCD Parallel I F Mode Configuration Register USIL_LPCFG 19 47 USIL LCD Parallel I F Mode Interrupt Enable Register USIL_LPIE 19 48 USIL LCD Parallel I F Mode Interrupt Flag Regis...

Page 12: ...ata Output Control 21 6 21 6 I2S Interrupt and DMA 21 11 21 6 1 Interrupts 21 11 21 6 2 DMA Transfer 21 12 21 7 Control Register Details 21 12 I2S Control Register I2S_CTL 21 13 I2S Master Clock Division Ratio Register I2S_DV_MCLK 21 16 I2S Audio Clock Division Ratio Register I2S_DV_AUDIO_CLK 21 16 I2S Start Stop Register I2S_START 21 18 I2S FIFO Status Register I2S_FIFO_STAT 21 18 I2S Interrupt C...

Page 13: ... 19 FPTC F Interrupt Flag Register GPIO_FPTCF_FLG 24 20 FPT0 1 Interrupt Chattering Filter Control Register GPIO_FPT01_CHAT 24 20 FPT2 3 Interrupt Chattering Filter Control Register GPIO_FPT23_CHAT 24 21 FPT4 5 Interrupt Chattering Filter Control Register GPIO_FPT45_CHAT 24 22 FPT6 7 Interrupt Chattering Filter Control Register GPIO_FPT67_CHAT 24 22 FPT8 9 Interrupt Chattering Filter Control Regis...

Page 14: ... 25 6 25 5 A D Converter Interrupts and DMA 25 8 25 6 Control Register Details 25 8 A D Conversion Result Register ADC10_ADD 25 9 A D Trigger Channel Select Register ADC10_TRG 25 9 A D Control Status Register ADC10_CTL 25 11 A D Clock Control Register ADC10_CLK 25 13 26 LCD Controller LCDC 26 1 26 1 LCDC Module Overview 26 1 26 2 Block Diagram 26 2 26 3 LCDC Output Pins 26 3 26 4 System Settings 2...

Page 15: ...CDC_SUBADR 26 47 Sub Screen Address Offset Register LCDC_SUBOFS 26 47 Sub Window Start Position Register LCDC_SUBSP 26 48 Sub Window End Position Register LCDC_SUBEP 26 48 Monochrome Look up Table Registers 0 and 1 LCDC_MLUT0 1 26 49 27 Graphics Engine GE 27 1 27 1 GE Module Overview 27 1 27 2 Operating Clock 27 2 27 3 Drawing Functions 27 2 27 3 1 Drawing Area 27 2 27 3 2 Drawing Basic Objects 27...

Page 16: ...ransparent Color Register GE_MAGIC 27 62 Updated Area Start Position Register GE_UPDT_ST 27 62 Updated Area End Position Register GE_UPDT_END 27 63 Palette 1 GE_PALETTE1 27 63 CCT1 4 bit Entries GE_CCT1_4BIT 27 63 CCT1 2 bit Entries GE_CCT1_2BIT 27 64 CCT1 1 bit Entries GE_CCT1_1BIT 27 64 27 7 LCDC Settings 27 64 28 USB Function Controller USB 28 1 28 1 USB Function Controller Overview 28 1 28 2 P...

Page 17: ...1 EPa Configuration 1 28 47 EPbMaxSize_H EPb Max Packet Size HIGH 28 47 EPbMaxSize_L EPb Max Packet Size LOW 28 47 EPbConfig_0 EPb Configuration 0 28 48 EPbConfig_1 EPb Configuration 1 28 48 EPcMaxSize_H EPc Max Packet Size HIGH 28 49 EPcMaxSize_L EPc Max Packet Size LOW 28 49 EPcConfig_0 EPc Configuration 0 28 49 EPcConfig_1 EPc Configuration 1 28 49 EPdMaxSize_H EPd Max Packet Size HIGH 28 50 EP...

Page 18: ...l 29 2 29 3 2 Snooze Control 29 2 29 3 3 USB Interrupt Enable 29 2 29 4 RAM Location 29 2 29 5 Boot Register 29 2 29 6 Control Register Details 29 3 RTC Wait Control Register MISC_RTCWT 29 3 USB Configuration Register MISC_USB 29 3 Internal RAM Wait Control Register MISC_RAMWT 29 4 Boot Register MISC_BOOT 29 5 RAM Location Select Register MISC_RAM_LOC 29 5 Misc Protect Register MISC_PROTECT 29 6 3...

Page 19: ...178 8 bit Timer T8 Ch 7 AP A 44 0x301180 0x30118c 16 bit PWM Timer T16A5 Ch 0 AP A 45 0x301190 0x30119c 16 bit PWM Timer T16A5 Ch 1 AP A 46 0x301200 0x30120e 16 bit Audio PWM Timer T16P AP A 47 0x301300 0x301306 A D Converter ADC10 AP A 48 0x301400 0x301412 I2S AP A 49 0x301500 0x301506 Remote Controller REMC AP A 50 0x302000 0x302094 LCD Controller LCDC AP A 51 0x302100 0x30211c DMA Controller DM...

Page 20: ...e CPU load and image data ROM size As for DSP functions a 32 bit 32 bit multiplier MUL and a 16 bit 16 bit divider DIV are implemented These functions help reduce CPU load for ADPCM audio data playback processing Also the embedded I2S inter face module is capable of being used to connect an external audio DAC The S1C33L26 has adopted the EPSON SoC System on Chip design technology using 0 18 µm low...

Page 21: ...ement algorithm Automatic lock function during debug mode and the interrupt process of specified priority The instruction cache RAM and data cache RAM can be used as a general purpose RAM when the cache function is disabled DMA Controller DMAC Eight channels of table DMA Supports table reloading and low priority channel pausing functions Trigger sources USI SPI UART USIL SPI UART Built in RAM LCD ...

Page 22: ...up to four SDRAM banks and bank active mode Built in 12 bit auto refresh counter Intelligent self refresh function for low power operation Arbitrates ownership of the external bus between the CPU DMAC LCDC and GE Clock Management Unit Oscillators PLL CMU Selects the system clock source OSC3 PLL OSC1 Turns the OSC3 and OSC1 oscillator circuits on and off Controls frequency multiplication rate of th...

Page 23: ...parison functions Each channel has built in two comparison capture data buffers Can generate compare capture interrupts Supports DMA transfer Watchdog Timer WDT 30 bit watchdog timer to generate an NMI or a reset Programmable watchdog timer overflow period NMI or reset interrupt period The watchdog timer overflow signal can be output outside the IC Real Time Clock RTC Contains time counters second...

Page 24: ...es Can generate receive buffer full transmit buffer empty and overrun error interrupts Supports DMA transfer I2C mode Supports both master single master only and slave modes 7 bit addressing mode 10 bit addressing is possible by software control Supports clock stretch wait functions Can generate start stop data transfer ACK NAK transfer and overrun error interrupts LCD SPI mode Data length is conf...

Page 25: ...panel used Supports up to 16M color for color TFT 4K color for color STN and 16 level gray scale for monochrome STN display modes Display configuration when the internal VRAM 20KB is used 320 240 pixels 2 bpp 4 level gray scale display Display configuration when an external memory is used 320 240 pixels 16 bpp QVGA 64K colors display 400 240 pixels 16 bpp WQVGA 64K colors display 640 480 pixels 16...

Page 26: ...7 V to 1 9 V 1 8 V typ when a ceramic resonator is used RTCVDD RTC BBRAM power voltage 1 65 V to 1 95 V 1 8 V typ or 1 7 V to 1 9 V 1 8 V typ when a ceramic resonator is used LVDD PLLVDD RTCVDD The S1C33L26 does not support 5 V tolerant I O Operating Temperatures 40 to 85 C 0 to 70 C when the USB module and a ceramic resonator are used Current Consumption No I O current is included During SLEEP 2 ...

Page 27: ...s SRAMC SDRAMC LUT 256 half words LCDC Arbiter GE IRAM 12K bytes Cache 2K bytes IRAM 20K bytes Area 0 IVRAM 20K bytes Area 3 Bus controller FSIO 2 ch USB PSC WDT T8F 4 ch T8 4 ch T16A5 2 ch T16P ADC10 I2S REMC LCDC Reg DMAC Reg SDRAMC Reg SRAMC Reg CCU Reg GE Reg RTC BBRAM 16 bytes AHB 1 SAPB AHB 2 External bus Software switch Software switch RTCVDD S1C33L26 2 1 Block Diagram Figure 1 ...

Page 28: ...LK WDT_NMI USBVBUS USBDP USBDM V SS 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 P97 FPDAT7 LCD_D7 P96 FPDAT6 LCD_D6 P95 FPDAT5 LCD_D5 P94 FPDAT4 LCD_D4 P93 FPDAT3 LCD_D3 SRDY0 P92 FPDAT2 LCD_D2 SCLK0 HVDD P91 FPDAT1 LCD_D1 ...

Page 29: ...6 SCLK0 I2S_SCLK PWM_H PB4 FPDAT12 FPDAT20 PB5 FPDAT13 FPDAT21 P05 SOUT0 I2S_WS T16A_ATMB_0 P04 SIN0 I2S_SDO T16A_ATMA_0 LV DD P60 WAIT WDT_CLK WDT_NMI USBVBUS USBDP USBDM V SS 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137...

Page 30: ...3 FPDAT11 I2S_MCLK PWM_L P82 FPSHIFT USIL_DI PB2 FPDAT10 I2S_SCLK PWM_H P80 FPFRAME USIL_CS P81 FPLINE USIL_CK MCLKO MCLKI PLLVSS VCP PLLVDD P71 AIN1 T16A_EXCL_1 P70 AIN0 T16A_EXCL_0 P72 AIN2 PWM_EXCL P73 AIN3 AVDD P75 AIN5 WAIT ADTRIG STBY P74 AIN4 RTCCLKO RTCCLKI RTCVDD P03 USI_CK SRDY1 REMC_I P00 USI_DI SIN1 NAND_WR P02 USI_CS SCLK1 REMC_O WAKEUP RESET NMI P01 USI_DO SOUT1 NAND_RD DCLK P34 PA2 ...

Page 31: ... 0 V Type 3 IOH IOL 8 mA HVDD 3 0 V See DC Characteristics in the Electrical Characteristics chapter PU PD PU Pull up PD Pull down PUc Pull up with software control en Enabled by default dis Disabled by default 3 2 1 List of Power Supply Pins Table 1 No Pin name I O Description Pin No Power voltage TQFP15 128 TQFP24 144 PFBGA 180 1 HVDD I O power supply pin 1 28 58 82 109 1 32 65 92 121 C9 D4 D9 F...

Page 32: ...o Data bus D7 84 94 F13 9 D8 I o Data bus D8 default 85 95 F12 PC0 i o I O port 10 D9 I o Data bus D9 default 86 96 E14 PC1 i o I O port 11 D10 I o Data bus D10 default 87 97 E12 PC2 i o I O port 12 D11 I o Data bus D11 default 88 98 E13 PC3 i o I O port 13 D12 I o Data bus D12 default 89 99 D12 PC4 i o I O port 14 D13 I o Data bus D13 default 90 100 D14 PC5 i o I O port 15 D14 I o Data bus D14 de...

Page 33: ... Flash read signal output 39 A22 O L Address bus A22 default 4 4 C1 P41 i o I O port FPDAT17 o LCD data output NAND_WR o NAND Flash write signal output 40 A23 O L Address bus A23 default 5 5 D3 P42 i o I O port FPDAT16 o LCD data output 41 A24 O L Address bus A24 default 140 C3 PA4 i o I O port T16A_ATMA_1 i o T16A5 Ch 1 capture A signal input compare A signal output REMC_O o REMC transmit signal ...

Page 34: ...sh write signal output 2 P01 I o I O port default 30 34 L3 USI_DO o USI data output see Table 1 3 2 8 SOUT1 o FSIO Ch 1 data output see Table 1 3 2 10 NAND_RD o NAND Flash read signal output 3 P02 I o I O port default 31 35 M2 USI_CS i o USI slave select input data input output see Table 1 3 2 8 SCLK1 i o FSIO Ch 1 clock input output see Table 1 3 2 10 REMC_O o REMC transmit signal output 4 P03 I ...

Page 35: ...ault 19 21 H1 TFT_CTL1 o LCDC TFT I F control signal 1 output T16A_ATMB_0 i o T16A5 Ch 0 capture B signal input compare B signal output 16 P32 I o I O port default 20 22 H3 P2 LVCMOS Schmitt Type 3 100k PUc dis TFT_CTL2 o LCDC TFT I F control signal 2 output REMC_O o REMC transmit signal output 17 P33 I o I O port default 21 23 J3 P2 LVCMOS Schmitt Type 1 100k PUc dis TFT_CTL3 o LCDC TFT I F contr...

Page 36: ...nput output SOUT0 o FSIO Ch 0 data output see Table 1 3 2 10 31 P92 I o I O port default 59 66 M11 FPDAT2 o LCD data output LCD_D2 i o USIL LCD data input output SCLK0 i o FSIO Ch 0 clock input output see Table 1 3 2 10 32 P93 I o I O port default 60 67 P12 FPDAT3 o LCD data output LCD_D3 i o USIL LCD data input output SRDY0 i o FSIO Ch 0 ready signal input output see Table 1 3 2 10 33 P94 I o I O...

Page 37: ...ta output FPDAT20 o LCD data output 47 PB5 I o I O port default 81 K12 FPDAT13 o LCD data output FPDAT21 o LCD data output 48 PB6 I o I O port default 104 E11 FPDAT14 o LCD data output FPDAT22 o LCD data output 49 PB7 I o I O port default 105 D11 FPDAT15 o LCD data output FPDAT23 o LCD data output 3 2 5 List of USB Pins Table 1 No Pin name I O Description Pin No PWR DC characteristics TQFP15 128 T...

Page 38: ... USI_CK Unused input Clock output spi_ck Clock input spi_ck Clock input output i2c_sck Clock input output i2c_sck USI_CS Unused input Unused input Slave select input spi_ss Data input output i2c_sda Data input output i2c_sda Note In I2C mode both the USI_DI and USI_CS pins can be configured as I2C data input output pins However they can not be used for I2C data input output at the same time 3 2 9 ...

Page 39: ...lock input Clock output Clock input SRDY0 Unused input Unused input Ready signal input Ready signal output Ch 1 SIN1 Data input Data input Data input Data input SOUT1 Data output Data output Data output Data output SCLK1 Unused input Clock input Clock output Clock input SRDY1 Unused input Unused input Ready signal input Ready signal output Package 1 3 3 TQFP15 128pin Package Unit mm 65 96 33 64 IN...

Page 40: ...anual Seiko Epson Corporation 1 21 TQFP24 144pin Package Unit mm 16 18 16 18 37 72 1 36 108 73 144 109 INDEX 1 0 1 1 2 max 0 13min 0 23max 0 4 1 0 3min 0 7max 0 09min 0 2max 0 min 8 max 3 3 2 TQFP24 144pin Package Dimensions Figure 1 ...

Page 41: ...w Bottom View A1 Corner A1 Corner Index D E A A 1 e SD S S y P N M L K J H G F E D C B A Symbol D E A A1 e b x y SD SE Min 0 38 Dimension in Millimeters Nom 12 12 0 3 0 8 0 4 0 4 Max 1 2 0 48 0 08 0 1 φ φ b x M e S E 1 2 3 4 5 6 7 8 9 10 11 12 13 14 3 3 3 PFBGA12U 180 Package Dimensions Figure 1 ...

Page 42: ...ndless condition with the sample mounted on a measurement board size 114 76 1 6 mm thick FR4 4 layered board 2 When suspended alone windless condition Thermal resistance 90 100 C W This value indicates the thermal resistance of the package when measured under a windless condition with the sample suspended alone Thermal resistance of the PFBGA package 1 When mounted on a board windless condition Th...

Page 43: ...the S1C33 Family C33 PE Core Manual Features of the C33 PE Core 2 1 Processor type Seiko Epson original 32 bit RISC processor 32 bit internal data processing Contains a 32 bit 8 bit multiplier Operating clock frequency Depends on the processor model and process technology Instruction set Code length 16 bit fixed length Number of instructions 125 Execution cycle Main instructions executed in one cy...

Page 44: ... general purpose register and immediate sp imm10 Addition of SP and immediate with immediate zero extended adc rd rs Addition with carry between general purpose registers sub rd rs Subtraction between general purpose registers rd imm6 Subtraction of general purpose register and immediate sp imm10 Subtraction of SP and immediate with immediate zero extended sbc rd rs Subtraction with carry between ...

Page 45: ...nded rd rb Postincrement possible rd sp imm6 Stack byte general purpose register zero extended ld h rd rs General purpose register halfword general purpose register sign extended rd rb Memory halfword general purpose register sign extended rd rb Postincrement possible rd sp imm6 Stack halfword general purpose register sign extended rb rs General purpose register halfword memory rb rs Postincrement...

Page 46: ...he register rd imm5 Arithmetic shift to the right Bits 0 31 shifted as specified by immediate sla rd rs Arithmetic shift to the left Bits 0 31 shifted as specified by the register rd imm5 Arithmetic shift to the left Bits 0 31 shifted as specified by immediate rr rd rs Rotate to the right Bits 0 31 rotated as specified by the register rd imm5 Rotate to the right Bits 0 31 rotated as specified by i...

Page 47: ...t instructions indicate the number of bits shifted while those in bit manipulation indicate bit positions sign6 sign8 Signed immediate numerals indicating bit length Debug Mode 2 4 The C33 PE Core has debug mode to assist in software development by the user The debug mode provides the following functions Instruction Break A debug exception is generated before the set instruction address is execute...

Page 48: ... indicates the chip core type ID Chip Core Type 0x02 C33 standard macro core C33 STD Core 0x03 C33 mini macro core 0x04 C33 advanced macro core C33 ADV Core 0x05 C33 PE Core 0x06 C33 PE little endian core The S1C33L26 has adopted the C33 PE little endian core so the chip core ID is 0x06 Product Series ID Bits D 7 0 0x20009 These bits provide an 8 bit ID code that indicates the product series of th...

Page 49: ...0 Area 19 0x1fff ffff 0x1000 0000 Area 18 0x0fff ffff 0x0C00 0000 Area 17 0x0bff ffff 0x0800 0000 Area 16 0x07ff ffff 0x0600 0000 Area 15 0x05ff ffff 0x0400 0000 Area 14 0x03ff ffff 0x0300 0000 Internal RAM area External Memory 16M bytes External Memory 4M bytes External Memory 4M bytes External Memory 2M bytes External Memory 2M bytes External Memory 1M bytes External Memory 1M bytes External Mem...

Page 50: ...er T16P 16 bit PWM Timer Ch 0 Ch 1 T16A5 8 bit Timer Ch 0 Ch 7 T8 Watchdog Timer WDT Reserved Prescaler PSC USB Function Controller Reserved BBRAM Real time Clock RTC Reserved Port MUX PMUX Reserved Serial Interface with FIFO Ch 0 Ch 1 FSIO Universal Serial Interface with LCD Interface USIL Universal Serial Interface USI I O Ports GPIO Interrupt Controller ITC Clock Management Unit CMU Misc Regist...

Page 51: ...at addresses 0x1fc00 to 0x1ffff and can be used as a data cache Each 1K byte RAM is enabled as a cache memory by setting the cache controller For more information on the caches see the Cache Controller CCU chapter Areas 1 and 2 Reserved for System 3 3 Areas 1 and 2 are reserved for the system Be sure to avoid accessing these areas from the user program and the de bugger Area 3 IVRAM DSTRAM 3 4 IVR...

Page 52: ...D Flash can be connected to Area 9 4M bytes or Area 22 2G bytes An SDRAM can be connected to Area 7 2M bytes or Area 19 256M bytes The external VRAM used for the graphics engine and LCD controller can be connected to Ar eas 4 to 22 Bus Masters and Accessible Memories 3 7 The table below lists the bus masters and the memories that can be accessed 7 1 Bus Masters and Accessible Memories Table 3 Memo...

Page 53: ...F register is set to 1 self refresh enabled When SDON is set to 0 SDRAMC disabled or SELEN is set to 0 self refresh disabled the SRAM will be accessed according to the setup hold and wait cycle conditions set using the SRAMC register The S1C33L26 is designed under the assumption that the CPU is set in HALT status and the LCDC only is ac tive while the SDRAM is placed into self refresh mode The SDR...

Page 54: ...H 1 2 W 1 H 1 0x0 0x2 W H 5 3 W 1 H 1 3 W 1 H 1 0x1 0x2 W H 5 2 2 W 1 H 1 3 W 1 H 1 0x2 0x2 W H 5 1 2 W 1 H 1 3 W 1 H 1 0x3 0x2 W H 5 4 3 W 1 H 1 3 W 1 H 1 0x4 0x2 W H 5 3 W 1 H 1 3 W 1 H 1 0x5 0x2 W H 6 1 2 2 W 1 H 1 3 W 1 H 1 0x6 0x2 W H 7 1 1 2 W 1 H 1 3 W 1 H 1 0x7 0x2 W H 8 1 4 3 W 1 H 1 3 W 1 H 1 0x8 0x2 W H 9 1 3 W 1 H 1 3 W 1 H 1 0x9 0x2 W H 10 1 2 2 W 1 H 1 3 W 1 H 1 0xa 0x2 W H 11 1 1 2 ...

Page 55: ... 2 CPU DMAC GE single random read 6 T24NS 2 CAS 6 T24NS 2 CAS CPU DMAC GE bulk read 6 CAS 6 CAS Cache burst read 1 11 T24NS 2 CAS DMAC burst read 2 11 T24NS 2 CAS LCDC burst read 3 19 T24NS 2 CAS T24NS Value set in T24NS 1 0 SDRAMC_CFG register CAS CAS latency set in CAS 1 0 SDRAMC_APP register The values in the table do NOT take the following conditions into consideration When the SDRAM is in aut...

Page 56: ...L8 M8 1 8 V typ 1 65 to 1 95 V or 1 7 to 1 9 V when a ce ramic resonator is used 4 RTCVDD RTC BBRAM power supply pin 33 37 N2 1 8 V typ LVDD 5 VSS Ground pin 8 22 36 51 65 76 91 104 113 124 8 24 40 56 73 86 101 116 127 138 B4 C10 D8 D10 E5 E6 E7 E8 E9 E10 F5 F10 G5 G10 H4 H5 H10 H11 J4 J5 J10 K5 K6 K7 K8 K9 K10 K11 L4 L5 L6 L7 M6 M13 N3 N8 GND 6 PLLVDD PLL power supply pin 47 52 M7 1 8 V typ LVDD ...

Page 57: ...evel as the LVDD to the RTCVDD pin RTCVDD LVDD VSS GND The RTCVDD is also used for the battery backup RAM BBRAM I O Interface Voltage HV 4 5 DD The HVDD voltage is used for interfacing with external I O signals For the output interface of the S1C33L26 the HVDD voltage is used as high level and the VSS voltage as low level The VSS pin is used for the ground common with LVDD The effective HVDD volta...

Page 58: ... occur in the device or the characteristics may be degraded due to flow through current of the HVDD or AVDD Latch up The CMOS device may be in the latch up condition This is the phenomenon caused by conduction of the para sitic PNPN junction thyristor contained in the CMOS IC resulting in a large current between LVDD and VSS and leading to breakage Latch up occurs when the voltage applied to the i...

Page 59: ...igure 5 1 1 1 to assert the internal reset signal low level must be continuously detected at least three times in this sampling The RESET signal should be held low for at least three OSC3 clock cycles to ensure that the chip is reset Also the internal reset signal is negated when the default OSC3 oscillation stabilization wait time has elapsed after the RESET pin goes high The S1C33L26 is reset by...

Page 60: ...Reset Status 5 1 4 The C33 PE Core and internal peripheral circuits are initialized while the internal reset signal is at kept 0 The fol lowing shows the reset status of the internal IC with the initial reset 1 4 1 Initial Reset Status Table 5 Item Boot mode Initial reset status CPU TTBR NOR Flash external ROM boot Initialized to 0x20000000 SPI EEPROM boot PC RS232C boot ICD debug Initialized to 0...

Page 61: ...low speed OSC1 oscillator circuit requires a longer time for oscil lation to stabilize than the high speed OSC3 oscillator circuit See the electrical characteristics table To pre vent erratic operation due to an unstable clock the OSC1 clock should not be used only after this stabilization time elapsed I O ports and I O pins Initial reset initializes the I O port control and data registers therefo...

Page 62: ...I signal changes from a high to a low level 2 The NMI pin is maintained at a low level for three or more system clock cycles NMI by the Watchdog Timer 5 2 2 The S1C33L26 has a built in watchdog timer to detect runaway of the CPU The watchdog timer outputs a signal if it is not reset with software due to CPU runaway in the programmed cycles The output signal can generate either NMI or reset Write 1...

Page 63: ... shows the clock system and CMU module configuration OSC3 oscillator 48 MHz OSC1 oscillator 32 768 kHz Reset NMI control NMI RESET CMU WDT NMI RESET MCLKI MCLKO OSC3 OSC1 PLL OSC CLKSEL 1 0 CCLK HALT SLEEP Wakeup Power down control Gate To C33 PE Core CMU_CLK RTCCLKI RTCCLKO RTC WAKEUP STBY Divider 1 1 1 32 Gate Gate C33 PE Core IRAM Cache GE LCDC SAPB Bus DMAC DSTRAM IVRAM LCDC AHB CMU SRAMC_SDRA...

Page 64: ...t generates the main clock for high speed operation of the C33 PE Core and peripheral circuits Structure of the OSC3 oscillator circuit The OSC3 oscillator circuit accommodates a crystal ceramic oscillator and external clock input Figure 6 3 1 1 shows the structure of the OSC3 oscillator circuit Oscillation circuit control signal SLEEP control Oscillation circuit control signal SLEEP control VSS M...

Page 65: ...6 cycles 0x1 2 097 152 cycles 0x0 4 194 304 cycles Default 0xf This is set to 128 cycles OSC3 clock after an initial reset Notes The OSC3 oscillation stabilization wait timer cannot be used when the OSC3 oscillator is turned on with software Therefore a software wait routine must be implemented Oscillation stability will vary depending on the resonator and other external components Carefully consi...

Page 66: ... oscillator circuit connect the RTCCLKI pin to VSS and leave the RTCCLKO pin open OSC1 oscillation on off The OSC1 oscillator circuit stops oscillating when OSC1EN CMU_OSCCTL register is set to 0 and starts os cillating when set to 1 After an initial reset OSC1EN is set to 1 and the OSC1 oscillator circuit is activated The OSC1 oscillator circuit does not stop oscillating in SLEEP mode Note A fini...

Page 67: ...etting the Frequency Multiplication Rate 6 4 3 The PLL frequency multiplication rate can be specified as shown in the table below using PLLN 3 0 CMU_ PLLCTL0 register 4 3 1 PLL Frequency Multiplication Rates Table 6 PLLN 3 0 Multiplication rate 0xf x16 0xe x15 0xd x14 0xc x13 0xb x12 0xa x11 0x9 x10 0x8 x9 0x7 x8 0x6 x7 0x5 x6 0x4 x5 0x3 x4 0x2 x3 0x1 x2 0x0 x1 Default 0x0 PLL output clock frequen...

Page 68: ...alue RS value of the PLL by using PLL RS 3 0 CMU_PLLCTL1 register 4 4 3 RS Value Settings Table 6 PLLRS 3 0 fREFCK MHz 0xa 5 fREFCK 20 0x8 20 fREFCK 150 Other Setting prohibited Default 0x8 LPF capacitance value CS value Bits to set the LPF capacitance value CS value is provided in the CMU control registers PLLCS 1 0 CMU_ PLLCTL2 register However do not alter the value of these bits and leave them...

Page 69: ...k is selected as the system clock source since in this case the SS modulation is effective for all the operating clocks for the core and peripheral circuits except the RTC that uses the OSC1 clock Note When the OSC3 or OSC1 clock is selected as the system clock source SS modulation is not per formed for the operating clock system clock About spectrum spread SS modulation The SSCG performs SS modul...

Page 70: ...iate value according to the PLL output clock frequency as shown in the table below using SSMCIDT 3 0 CMU_SSCG1 register The maximum frequency change width will be about 2 of the PLL output clock by the above setting 5 2 1 Maximum Frequency Change Width Settings Table 6 PLL output clock frequency f MHz SSMCIDT 3 0 f 19 8 0xf 19 8 f 21 2 0xe 21 2 f 22 5 0xd 22 5 f 24 2 0xc 24 2 f 25 9 0xb 25 9 f 28 ...

Page 71: ...3 oscillator off to reduce current consumption if the CMU_CLK output circuit has not used the OSC3 clock OSC3EN 0 Switching the system clock to PLL from OSC3 1 Configure the PLL input clock and the PLL parameters such as the multiplication rate before activating the PLL 2 Enable the PLL PLLPOWR 1 3 Wait until the PLL operation is stabilized 4 Stop the peripheral circuits being currently operated e...

Page 72: ...ency Setting 6 6 2 The source clock frequency can be divided by 1 to 32 to generate the system clock using SYSCLKDIV 2 0 CMU_ SYSCLKDIV register Setting the system clock to the lowest frequency possible according to the processing can reduce current consumption 6 2 1 System Clock Division Ratio Table 6 SYSCLKDIV 2 0 Division ratio OSC n 0x7 0x6 1 1 0x5 1 32 0x4 1 16 0x3 1 8 0x2 1 4 0x1 1 2 0x0 1 1...

Page 73: ...tion on CLK_DOWN 1 0 see the Cache Controller CCU chapter 7 1 1 Core Clock Division Ratio Selection Table 6 CLK_DOWN 1 0 Division ratio 0x3 1 8 0x2 1 4 0x1 1 2 0x0 1 1 Default 0x0 Bus Clock BCLK 6 7 2 BCLK BCLK_EN HALT MCLK 7 2 1 BCLK Control Circuit Figure 6 The BCLK clock is used to operate the modules listed below IVRAM Area 3 DSTRAM Area 3 SRAM controller SRAMC SDRAM controller SDRAMC DMA cont...

Page 74: ...er LCDC registers The peripheral module clock PCLK1 PCLK2 supply can be controlled using the clock enable bit PCLK1_EN PCLK2_EN The default setting of the clock enable bit is 1 which enables the clock supply Disable the clock supply by setting the clock enable bit to 0 to reduce current consumption unless all the modules that use the clock need to be running The clock is supplied even in HALT mode...

Page 75: ...10 1 17 0x0 1 1 Default 0x7 LCLK_EN CMU_CLKCTL register is used for clock supply control default off Before using the LCDC set LCLK_EN to 1 Note that PCLK2 is required to set the LCDC registers In HALT mode LCLK does not stop if LCLK_EN is set to 1 To stop supplying the clock in HALT mode LCLK_ EN should be set to 0 before executing the halt instruction In SLEEP mode when the slp instruction is ex...

Page 76: ...P mode when the slp instruction is executed USBCLK stops even if USBCLK_EN is set to 1 The USBREGCLK clock is the clock for accessing the USB registers USBREGCLK_EN CMU_CLKCTL register is used for clock supply control The default setting of USBREGCLK_EN is 0 which disables the clock supply Enable the clock supply by setting USBREGCLK_EN to 1 before the USB registers can be accessed USBREGCLK is su...

Page 77: ...executing the slp instruction and enters SLEEP mode In SLEEP mode the CPU stops operating and the CMU stops supplying clocks Therefore all peripheral modules except for the OSC1 oscillator circuit and RTC stop operating The CPU is reawaken from SLEEP mode by initial reset an RTC interrupt an NMI or other interrupt from an ex ternal device port input interrupt The C33 PE Core can restart from SLEEP...

Page 78: ...er write protection The CMU module registers are described in detail below These are 8 bit registers Notes When data is written to the registers the Reserved bits must always be written as 0 and not 1 The CMU control registers at addresses 0x300100 0x30010d are write protected Before the CMU control registers can be rewritten write protection of these registers must be removed by writing data 0x96...

Page 79: ...0 3 OSC3 Oscillation Stabilization Wait Time Settings Table 6 OSC3WT 3 0 Oscillation stabilization wait time 0xf 128 cycles 0xe 256 cycles 0xd 512 cycles 0xc 1 024 cycles 0xb 2 048 cycles 0xa 4 096 cycles 0x9 8 192 cycles 0x8 16 384 cycles 0x7 32 768 cycles 0x6 65 536 cycles 0x5 131 072 cycles 0x4 262 144 cycles 0x3 524 288 cycles 0x2 1 048 576 cycles 0x1 2 097 152 cycles 0x0 4 194 304 cycles Defa...

Page 80: ...ister CMU_ LCLKDIV 0x300103 8 bits D7 5 reserved 0 when being read D4 0 LCLKDIV 4 0 LCDC clock division ratio select LCLKDIV 4 0 Division ratio 0x7 R W Clock source OSC3 Write protected 0x1f 0x1e 0x1d 0x1c 0x1b 0x1a 0x19 0x18 0x17 0x16 0x15 0x14 0x13 0x12 0x11 0x10 0xf 0xe 0xd 0xc 0xb 0xa 0x9 0x8 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 1 32 1 31 1 30 1 29 1 28 1 27 1 26 1 25 1 24 1 23 1 22 1 21 1 20 1 19 ...

Page 81: ... W D1 PCLK1_EN PCLK1 clock enable 1 Enable 0 Disable 1 R W D0 GCLK_EN GCLK clock enable 1 Enable 0 Disable 1 R W D7 USBREGCLK_EN USB I O Register Clock Enable Bit Enables or disables the USBREGCLK clock supply to the USB function controller 1 R W Enabled on 0 R W Disabled off default The USBREGCLK_EN default setting is 0 which stops the clock supply Setting USBREGCLK_EN to 1 supplies USBREGCLK to ...

Page 82: ...roller LCDC bus interface Clock management unit CMU registers Bus arbiters BCLK is required for bus and memory operations therefore it is always supplied to the modules listed above in normal mode However the BCLK supply in HALT mode can be disabled to reduce current consumption by setting BCLK_EN to 0 if the LCDC and DMA do not need bus operations D2 PCLK2_EN PCLK2 Clock Enable Bit Enables or dis...

Page 83: ...to reduce current consumption System Clock Division Ratio Select Register CMU_SYSCLKDIV Register name Address Bit Name Function Setting Init R W Remarks System Clock Division Ratio Select Register CMU_ SYSCLKDIV 0x300105 8 bits D7 5 reserved 0 when being read D4 MCLKDIV MCLK clock divider select 1 1 2 0 1 1 0 R W Write protected D3 reserved 0 when being read D2 0 SYSCLKDIV 2 0 System clock divisio...

Page 84: ...te protected 0xf 0xb 0xa 0x9 0x8 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 reserved OSC 32 OSC 16 OSC 8 OSC 4 OSC 2 OSC 1 LCLK BCLK PLL OSC1 OSC3 D 7 5 Reserved D 4 0 CMU_CLKSEL 4 0 CMU_CLK Select Bits Selects an internally generated clock to be output from the CMU_CLK pin to external devices 10 6 CMU_CLK Selections Table 6 CMU_CLKSEL 4 0 CMU_CLK 0xf 0xb Reserved 0xa OSC 32 0x9 OSC 16 0x8 OSC 8 0x7 OSC 4 0x...

Page 85: ... 4 1 3 1 2 1 1 D 7 4 Reserved D 3 0 PLLINDIV 3 0 PLL Input Clock Division Ratio Select Bits Selects the PLL input clock OSC3 division ratio 10 7 PLL Input Clock OSC3 Division Ratio Selections Table 6 PLLINDIV 3 0 Division ratio OSC3 n 0xf 0xa 1 8 0x9 1 10 0x8 1 9 0x7 1 8 0x6 1 7 0x5 1 6 0x4 1 5 0x3 1 4 0x2 1 3 0x1 1 2 0x0 1 1 Default 0x7 Notes The PLL input clock can only be selected when the PLL ...

Page 86: ...ned off PLLPOWR 0 before altering D 7 4 in this register D 7 4 PLLN 3 0 PLL Multiplication Rate Setup Bits Sets the frequency multiplication rate of the PLL 10 8 PLL Frequency Multiplication Rates Table 6 PLLN 3 0 Multiplication rate 0xf x16 0xe x15 0xd x14 0xc x13 0xb x12 0xa x11 0x9 x10 0x8 x9 0x7 x8 0x6 x7 0x5 x6 0x4 x5 0x3 x4 0x2 x3 0x1 x2 0x0 x1 Default 0x0 PLL output clock frequency PLL inpu...

Page 87: ...ther 360 fVCO 400 320 fVCO 360 280 fVCO 320 240 fVCO 280 200 fVCO 240 160 fVCO 200 120 fVCO 160 100 fVCO 120 Not allowed D3 0 PLLRS 3 0 PLL LPF resistance setup PLLRS 3 0 fREFCK MHz 0x8 R W 0xa 0x8 Other 5 fREFCK 20 20 fREFCK 150 Not allowed Note Make sure that the PLL is turned off PLLPOWR CMU_PLLCTL0 register 0 before altering this register D 7 4 PLLVC 3 0 PLL VCO Kv Setup Bits Sets the VCO Kv c...

Page 88: ...SMCON SSCG Enable Bit Turns the SSCG on or off 1 R W On 0 R W Off Default Setting this bit to 1 causes the SSCG to start operating Setting this bit to 0 causes the SSCG to stop al lowing the clock to bypasses the SSCG SSCG Macro Control Register 1 CMU_SSCG1 Register name Address Bit Name Function Setting Init R W Remarks SSCG Macro Control Register 1 CMU_SSCG1 0x30010d 8 bits D7 4 SSMCITM 3 0 SSCG...

Page 89: ... flag Writing 10010110 0x96 removes the write protection of the CMU registers 0x300100 0x30010d Writing another value set the write protection 0x0 R W D 7 0 CMUP 7 0 CMU Register Write Protect Flag Bits Enables or disables write protection of the CMU control registers 0x300100 0x30010d 0x96 R W Disable write protection Other than 0x96 R W Write protect the register default 0x0 Before altering any ...

Page 90: ...mable timer T8 Ch 7 1 1 Prescaler Configuration Figure 7 PSC Ch 0 and PSC Ch 1 are controlled by PRUN PSC_CTL register To operate the prescalers write 1 to PRUN Writing 0 to PRUN stops the prescalers Stopping the prescalers while the timer and interface modules are halted enables the current consumption to be reduced The prescalers are stopped at initial reset Note PCLK1 and PCLK2 must be supplied...

Page 91: ... PRUN to operate PSC Ch 0 and PSC Ch 1 Write 0 to PRUN to stop PSC Ch 0 and PSC Ch 1 To reduce current consumption stop PSC Ch 0 and PSC Ch 1 if the modules listed below are al ready stopped Modules that use PSC Ch 0 output clocks 16 bit PWM timer T16A5 Ch 0 1 16 bit audio PWM timer T16P 8 bit programmable timer T8 Ch 0 clock source for USI 8 bit programmable timer T8 Ch 2 trigger source for A D c...

Page 92: ...interrupts are possible Interrupt period can be selected from 1 512 second 1 256 second 1 128 second 1 64 second 1 second 1 min ute or 1 hour Level interrupt mode Independent power supply so that the RTC can continue operating even when system power is turned off A built in OSC1 oscillator circuit crystal oscillator or external clock input that generates a 32 768 kHz typ operating clock See the Cl...

Page 93: ...our counter This 4 bit BCD counter counts in units of hours It counts from 0 to 9 with 1 carried over from the 10 min ute counter This counter is reset to 0 after 9 and outputs a carry over of 1 to the 10 hour counter Depending whether 12 hour or 24 hour mode is selected the counter is reset at 12 o clock or 24 o clock The count data is read out and written using RTCHL 3 0 RTC_HOUR register 10 hou...

Page 94: ... counts from 0 to 9 with 1 carried over from the 1 year counter The count data is read out and written using RTCYH 3 0 RTC_YEAR register Days of week counter This is a septenary counter that counts from 0 to 6 representing the days of the week It counts with the same timing as the 1 day counter The count data is read out and written using RTCWK 2 0 RTC_WEEK register The correspondence between the ...

Page 95: ... S1C33L26 is able to operate with RTCWT 2 0 1 RTC Initial Sequence 8 3 2 Immediately after power on the contents of RTC registers are indeterminate After powering on follow the proce dure below to let the RTC start ticking the time Later sections detail the contents of each control 1 Power on 2 System initialization processing and waiting for OSC1 stabilization Although the OSC1 oscillator circuit...

Page 96: ...ount data exceeding 60 seconds 60 minutes 12 or 24 hours 31 days 12 months or 99 years Settings nonexistent in the calendar Do not set such nonexistent dates as April 31 or February 29 2006 Even if such settings are made the counters operate normally so that when 1 is carried over from the hour counter to the 1 day counter the day counter counts up to the first day of the next month For April 31 t...

Page 97: ...nter data can be written to After 1 is written to RTCHLD the counters stop operating So RTCBSY is fixed at 0 as carry will not take place In this case the counter hold function is also actuated with a carry over of 1 to the 1 second counter dis abled in hardware The divider counter for less than one second continues operating Write data to the counter registers After writing data reset RTCHLD to 0...

Page 98: ...orrection processing has completed or not A repeat checking RTCADJ or B check RTCADJ after waiting for 4 ms Accessing the counters while RTCADJ 1 is prohibited Writing 0 to RTCADJ and writing 1 to RTCRST are also prohibited because it would cause the RTC to operate erratically Writing 1 to RTCADJ when RTCBSY is 1 may corrupt the counter values Always make sure that RTCBSY is set to 0 before writin...

Page 99: ... 64 second RTCT 2 0 should be set while RTC interrupts are disabled See the procedure for enabling and disabling inter rupts described below Setting interrupt conditions The RTC of the S1C33L26 supports level sensed interrupt only Enabling and disabling interrupts The RTC interrupt requests output to the ITC are enabled by setting RTCIEN RTC_INTMODE register to 1 and disabled by setting it to 0 RT...

Page 100: ...pt or software This output can control the external regulator to turn the system power LVDD PLLVDD HVDD AVDD on and off Note that leakage current flows to the RTCVDD system if the system power is turned off when the STBY pin is set to a high level Therefore the STBY pin must be set to a low level before the system power is turned off Figure 8 5 1 shows an example of system standby wakeup circuit u...

Page 101: ...s an output port and set the port output level to 1 high This signal is fed to the STBY pin resulting that the RTCVDD system circuits will be connected to the system 5 Write 0x2 to the RTC_WAKEUP register to set the WAKEUP polarity to active high and enable the WAKE UP pin to output 1 high This control fixes the regulator output to be enabled thus the POWER SW can be released turned off 6 Read the...

Page 102: ...de Register Sets up RTC interrupt modes 0x300a02 RTC_CNTL0 RTC Control 0 Register Controls the RTC 0x300a03 RTC_CNTL1 RTC Control 1 Register 0x300a04 RTC_SEC RTC Second Register Second counter data 0x300a05 RTC_MIN RTC Minute Register Minute counter data 0x300a06 RTC_HOUR RTC Hour Register Hour counter data 0x300a07 RTC_DAY RTC Day Register Day counter data 0x300a08 RTC_MONTH RTC Month Register Mo...

Page 103: ...ss Bit Name Function Setting Init R W Remarks RTC Interrupt Mode Register RTC_INTMODE 0x300a01 8 bits D7 5 reserved 0 when being read D4 2 RTCT 2 0 RTC interrupt cycle setup RTCT 2 0 Cycle X 0x1 R W 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 reserved 1 128 second 1 256 second 1 512 second 1 hour 1 minute 1 second 1 64 second D1 RTCIMD reserved 1 X 1 R W Always set to 1 D0 RTCIEN RTC interrupt enable 1 Enable...

Page 104: ...24 hour mode may be selected when starting the counters Note Rewriting RTC24H may corrupt the count data for hours days months years or days of the week Therefore after changing the RTC24H setting be sure to set data back in these coun ters again D3 Reserved D2 RTCADJ 30 second Adjustment Bit This bit executes 30 second correction 1 W Execute 30 second correction 0 W Has no effect 1 R 30 second co...

Page 105: ...reset value In order to prevent carry over during reading counters the RTC includes a read buffer to hold counter data Before reading counter data set RTCRDHLD to 1 to load the current counter data to the read buf fer While RTCRDHLD is set to 1 the buffered data is read out from the counter registers Be sure to reset RTCRDHLD to 0 after the buffered data is read out This operation does not affect ...

Page 106: ...ter counts from 0 to 5 with a carry over of 1 from the 1 second counter This counter is reset to 0 after 5 and outputs a carry over of 1 to the 1 minute counter D 3 0 RTCSL 3 0 RTC 1 second Counter Bits These bits comprise a 4 bit BCD counter used to count units of seconds The counter counts from 0 to 9 synchronously with a 1 second signal derived from the 32 768 kHz OSC1 clock This counter is res...

Page 107: ...er counts from 0 to 1 when 12 hour mode is selected or from 0 to 2 when 24 hour mode is selected The counter is reset at 12 o clock or 24 o clock and outputs a carry over of 1 to the 1 day counter D 3 0 RTCHL 3 0 RTC 1 hour Counter Bits These bits comprise a 4 bit BCD counter used to count units of hours The counter counts from 0 to 9 with a carry over of 1 from the 10 minute counter This counter ...

Page 108: ...bit is reset to 0 along with the 1 month counter and a carry over of 1 is output to the 1 year counter D 3 0 RTCMOL 3 0 RTC 1 month Counter Bits These bits comprise a 4 bit BCD counter used to count units of months The counter counts from 0 to 9 with a carry over of 1 from the day counter This counter is reset to 0 af ter 9 and outputs a carry over of 1 to the 10 month counter The counter is reset...

Page 109: ...ts at the same timing as the 1 day counter The correspondence between the counter values and days of the week can be set in a program as de sired Table 8 6 3 lists the basic correspondence 6 3 Correspondence between Counter Values and Days of the Week Table 8 RTCWK 2 0 Days of the week 0x6 Saturday 0x5 Friday 0x4 Thursday 0x3 Wednesday 0x2 Tuesday 0x1 Monday 0x0 Sunday Default indeterminate softwa...

Page 110: ... Flash ROM SRAM and other devices such as an LCD driver Programmable bus access wait cycle 0 to 15 cycles Supports little endian access Supports memory mapped I O devices Supports either A0 or BS bus strobe access type Supports external wait requests via the WAIT pin SRAMC Pins 9 2 Table 9 2 1 lists the pins used by the SRAMC 2 1 SRAMC Pin List Table 9 Pin name I O Qty Function D 15 0 I O 16 Exter...

Page 111: ...5 0x002f ffff 0x0020 0000 Area 4 0x001f ffff 0x0010 0000 Area 15 0x05ff ffff 0x0400 0000 Area 14 0x03ff ffff 0x0300 0000 External memory 16M bytes Reserved Reserved External memory 4M bytes External memory 4M bytes External memory 2M bytes External memory 2M bytes External memory 1M bytes External memory 1M bytes Area 18 0x0fff ffff 0x0c00 0000 Area 17 0x0bff ffff 0x0800 0000 Area 16 0x07ff ffff 0...

Page 112: ...t for two or more areas accommodated by the respective CEx signals This section describes the parameters to be set individually for each CEx area and the relevant control bits The SRAMC control registers are initialized by an initial reset These registers should be set up in software to suit the external device configuration or specification as required Note Letter x in the control bit and CE name...

Page 113: ...e specifications of the connected device set an appropriate wait cycle using CExWAIT 3 0 in the SRAMC_TMG47 and SRAMC_TMG810 reg isters If CExWAIT 3 0 is set to 0 no static wait cycle is inserted In this case the minimum read write pulse width will be one cycle 4 2 4 Static Wait Cycle Settings Table 9 CExWAIT 3 0 Static wait cycle Read write cycle 0xf 15 cycles 16 cycles WAIT 0xe 14 cycles 15 cycl...

Page 114: ...ory addresses aligned to the boundary of the data size must be specified Specifying other addresses generates address misaligned exceptions Instructions e g stack manipulating and branch instructions that rewrite the contents of the stack pointer SP or program counter PC forcibly alter the address specified to a boundary address to prevent address misaligned ex ceptions For details of address misa...

Page 115: ...ata size R W A1 A0 A0 mode BSL mode Access count Valid signal D 15 8 pins D 7 0 pins Valid signal D 15 8 pins D 7 0 pins 8 bits Byte W WRL D 7 0 1 R RD D 7 0 1 Halfword W 0 WRL D 7 0 1st 1 D 15 8 2nd R 0 RD D 7 0 1st 1 D 15 8 2nd Word W 0 0 WRL D 7 0 1st 0 1 D 15 8 2nd 1 0 D 23 16 3rd 1 1 D 31 24 4th R 0 0 RD D 7 0 1st 0 1 D 15 8 2nd 1 0 D 23 16 3rd 1 1 D 31 24 4th 16 bits Byte W 0 WRL D 7 0 WR BS...

Page 116: ...1 1 SRAM read write timings with no static wait cycles Example settings Device size 16 bits Number of static wait cycles 0 cycles CE setup hold time 1 cycle CLK A 25 0 CEx RD D 15 0 WAIT valid valid 6 1 1 SRAM Read Timing with No Static Wait Cycle Figure 9 CLK A 25 0 CEx WR D 15 0 WAIT valid valid 6 1 2 SRAM Write Timing with No Static Wait Cycle Figure 9 ...

Page 117: ...xample settings Device size 16 bits Number of static wait cycles 2 cycles CE setup hold time 1 cycle CLK A 25 0 CEx RD D 15 0 WAIT valid valid Static wait cycle 6 1 3 SRAM Read Timing with Static Wait Cycle Figure 9 CLK A 25 0 CEx WR D 15 0 WAIT valid valid Static wait cycle 6 1 4 SRAM Write Timing with Static Wait Cycle Figure 9 ...

Page 118: ...ore the read or write signal goes high A wait state is entered while the WAIT signal is sampled active low and subsequent operation resumes when the WAIT signal is sampled inactive high Example settings Device size 16 bits Number of static wait cycles 0 cycles see Note below CE setup hold time 1 cycle see Note below CLK A 25 0 CEx RD D 15 0 WAIT valid valid Wait cycle 6 2 1 SRAM Read Timing with E...

Page 119: ...8 Access Timing Configuration Register Set CE 10 8 access conditions 0x302228 SRAMC_TYPE CE 10 4 Device Configuration Register Set CE 10 4 device types The following describes each SRAMC register These are all 32 bit registers Note When data is written to the registers the Reserved bits must always be written as 0 and not 1 CE 7 4 Access Timing Configuration Register SRAMC_TMG47 Register name Addr...

Page 120: ...CE10WAIT 3 0 CE10 static wait cycle CE10WAIT 3 0 Wait cycle 0xf R W 0xf 0xe 0x1 0x0 15 cycles 14 cycles 1 cycle 0 cycles D15 14 CE9SETUP 1 0 CE9 setup cycle CE9SETUP 1 0 Setup cycle 0x3 R W 0x3 0x0 4 cycles 1 cycle D13 12 CE9HOLD 1 0 CE9 hold cycle CE9HOLD 1 0 Hold cycle 0x3 R W 0x3 0x0 4 cycles 1 cycle D11 8 CE9WAIT 3 0 CE9 static wait cycle CE9WAIT 3 0 Wait cycle 0xf R W 0xf 0x0 15 cycles 0 cycl...

Page 121: ...longed for the number of specified cycles when the area is accessed If CExWAIT 3 0 is set to 0 no static wait cycle is inserted In this case the minimum read write pulse width will be one cycle 7 4 Static Wait Cycle Settings Table 9 CExWAIT 3 0 Static wait cycle Read write cycle 0xf 15 cycles 16 cycles WAIT 0xe 14 cycles 15 cycles WAIT 0x1 1 cycle 2 cycles WAIT 0x0 0 cycles 1 cycle WAIT Default 0x...

Page 122: ... R W D9 8 CE8TYPE 1 0 CE8 device type 0x0 R W D7 6 CE7TYPE 1 0 CE7 device type 0x0 R W D5 4 reserved 0 when being read D3 2 CE5TYPE 1 0 CE5 device type CExTYPE 1 0 Device type 0x0 R W 0x3 0x2 0x1 0x0 8 bit device 16 bit BSL type 16 bit A0 type D1 0 CE4TYPE 1 0 CE4 device type 0x0 R W D 31 14 D 5 4 Reserved D 13 12 D 11 10 D 9 8 D 7 6 D 3 2 D 1 0 CExTYPE 1 0 CEx Device Type Bits Selects the device ...

Page 123: ...AM BA1 and BA0 outputs Row address range 2K SDA10 SDA0 4K SDA11 SDA0 or 8K SDA12 SDA0 Column address range 256 SDA7 SDA0 512 SDA8 SDA0 or 1K SDA9 SDA0 Supports byte writes with the DQML and DQMH pins Includes a programmable 12 bit auto refresh counter Necessary refreshing enabled irrespective of the clock frequency used Provided with intelligent self refresh mode for low power operation Supports t...

Page 124: ...ccessing the SDRAMC control registers For details on how to set and control the clock refer to the Clock Management Unit CMU chapter Double frequency mode The SDRAMC supports double frequency mode in which the SDRAM can be operated with a clock two times faster than the CPU clock For example when the CPU runs with a 30 MHz clock the SDRAM can be oper ated with a 60 MHz clock To set the SDRAMC in d...

Page 125: ...n also sets up the bank size column address size page size and row address size 4 2 2 SDRAM Size Selections and SDRAM Address Table 10 ADDRC 2 0 0x0 default 0x1 0x2 0x3 0x7 0x4 0x5 0x6 SDRAM device 16 bit device Two 8 bit devices Capacity M bit 16 64 128 256 512 64 2 128 2 Data width 16 bits Row size 2048 4096 4096 8192 8192 4096 4096 Column size 256 256 512 512 1024 512 1024 Number of banks 2 4 4...

Page 126: ... CKE CS RAS CAS WE DQMU DQML 4 2 1 64MB SDRAM Connection Example Figure 10 S1C33L26 SDBA 1 0 SDA 11 0 D 15 0 SDCLK SDCKE SDCS SDRAS SDCAS SDWE DQMH DQML SDRAM 8M 16 bits 4 banks BA 1 0 A 11 0 DQ 15 0 CLK CKE CS RAS CAS WE DQMU DQML S1C33L26 SDBA 1 0 SDA 11 0 D 15 8 D 7 0 SDCLK SDCKE SDCS SDRAS SDCAS SDWE DQMH DQML SDRAM 8M 8 bits 4 banks 2 BA 1 0 A 11 0 DQ 7 0 CLK CKE CS RAS CAS WE DQM BA 1 0 A 11...

Page 127: ...efresh mode tRFC tXSR 1 cycle tRP NOP 4 2 3 SDRAM Timing Parameters Figure 10 1 CAS Latency CAS latency refers to the number of SDCLK clock cycles that run until data is output from the SDRAM after the READ command is issued In this SDRAM interface CAS latency can be set from 1 to 3 using CAS 1 0 SDRAMC_APP register 4 2 3 CAS Latency Settings Table 10 CAS 1 0 CAS latency 0x3 3 0x2 2 0x1 1 0x0 Rese...

Page 128: ... SRAM access rate while the SDRAM is in self refresh status in Sec tion 3 8 3 tRAS tRAS ACTIVE to PRECHARGE command period This timing parameter can be set from 1 to 8 cycles in SDCLK using T60NS 2 0 SDRAMC_CFG register 4 2 5 Table 10 tRAS Settings T60NS 2 0 tRAS 0x7 8 cycles 0x6 7 cycles 0x1 2 cycles 0x0 1 cycle Default 0x0 4 tRP tRCD tRP PRECHARGE to ACTIVE command period tRCD ACTIVE to READ WRI...

Page 129: ...SDRAM used Example 1 PALL REF REF MRS EMRS Example 2 PALL MRS REF REF REF REF REF REF REF REF Refer to the specifications of the SDRAM to be used for the initialization sequence Each command can be executed separately using the control bit shown below To execute the PALL Precharge All command Write 0x12 to the SDRAMC_INIT register to set INIPRE to 1 Then write any data to any address in the SDRAM ...

Page 130: ...he MRS command must be the same as the setting for CAS 1 0 SDRAMC_APP register After the initial sequence commands are executed the command enable bit must be set to 0 Write 0x10 to the SDRAMC_INIT register after the last initialization command has been ex ecuted The self refresh function must be disabled until the SDRAM has finished initialization 4 Checking if the SDRAM has been initialized INID...

Page 131: ...ELF H L L L L H End Self Refresh L H H Data Write Output Enable H L Data Write Output Disable H H V Valid Optional Unknown L Low level H High level Because all of these commands are output by the SDRAM controller as necessary they do not need to be controlled by the user program except for initializing the SDRAM SDRAM Bus Operations 10 5 3 The external data bus of the S1C33L26 is sized to 16 bits ...

Page 132: ...ML DQ 15 0 ACTV H NOP PRE NOP READ NOP READ BA BA ROW D 1 1 D 1 2 D 2 1 D 2 2 tRCD tRP CAS latency CAS latency ROW COL1 BA COL2 BA 5 4 1 Burst Read in the Same Page Figure 10 Figure 10 5 4 2 shows an example of a timing chart in cases where the row address is changed during burst read Parameter setting example CAS latency 2 tRCD 2 cycles tRAS 4 cycles tRP 2 cycles SDCLK Command SDCKE SDCS SDRAS SD...

Page 133: ...ame page Figure 10 Bank interleaved access Multiple banks up to four banks can be activated at the same time This makes it possible to access the SDRAM successively one bank after another without issuing the ACTV Active command Parameter setting example CAS latency 2 tRCD 2 cycles tRAS 4 cycles tRP 2 cycles SDCLK Command SDCKE SDCS SDRAS SDCAS SDWE SDBA 1 0 SDA10 SDA 12 11 9 0 DQMH DQML DQ 15 0 Ba...

Page 134: ...y and the count value set in AURCO 11 0 SDRAMC_REF register AURCO 11 0 should be set to the appropriate value meeting the specifications of the SDRAM The count value is obtained by the equation below RFP AURCO fCLK BL CL 2 tRP tRCD 3 ROWS RFP Maximum refresh period s ROWS Row address size fCLK SDCLK clock frequency Hz BL Burst length 2 CL CAS latency tRP PRECHARGE command period Number of cycles t...

Page 135: ...has finished the SDRAMC sends another self refresh command when the designated count is reached again When the auto refresh command is issued or an SDRAM access occurs the counter will restart if the self refresh command has not been sent to the SDRAM Therefore the self refresh counter value to be set must be smaller than the auto refresh counter value SELF L PALL tRP SDCLK Command SDCKE SDCS SDRA...

Page 136: ... Execute the slp instruction Perform the following procedure when the CPU wakes up from SLEEP status 1 The CPU wakes up from SLEEP status 2 Configure the port functions for the SDRAM 3 Release the data and address buses from forced low driving 4 Turn the SDRAM power on 5 Wait at least 100 or 200 µs for the SDRAM to be stabilized according to the SDRAM specifications 6 Set SDON SDRAMC_INIT register...

Page 137: ...IT Register name Address Bit Name Function Setting Init R W Remarks SDRAM Initialization Register SDRAMC_INIT 0x302200 32 bits D31 5 reserved 0 when being read D4 SDON SDRAM controller enable 1 Enable 0 Disable 0 R W D3 INIDO SDRAM initialization status 1 Finished 0 Busy 0 R D2 INIMRS MRS command enable for init 1 Enable 0 Disable 0 R W D1 INIPRE PALL command enable for init 1 Enable 0 Disable 0 R...

Page 138: ...fied in the MRS command must be the same as the setting for CAS 1 0 SDRAMC_APP register D1 INIPRE PALL Command Enable for Initialization Bit Enables to output the PALL Precharge All command for initializing the SDRAM 1 R W Enabled 0 R W Disabled default To execute the PALL Precharge All command write 0x12 to this register to set INIPRE to 1 Then write any data to any address in the SDRAM This dumm...

Page 139: ...figuration ADDRC 2 0 Configuration 0x0 R W Do not set to 0x4 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 512M bits 128M bits x 2 64M bits x 2 reserved 256M bits 128M bits 64M bits 16M bits D 31 14 Reserved D 13 12 T24NS 1 0 Number of SDRAM tRP and tRCD Cycles Bits Sets the tRP and tRCD SDRAM timing parameters tRP PRECHARGE to ACTIVE command period tRCD ACTIVE to READ WRITE delay time 7 3 Table 10 tRP and tRCD...

Page 140: ...not set ADDRC 2 0 to 0x4 0x3 4 8K 512 16M 16 bits 1 32M bytes 0x2 4 4K 512 8M 16 bits 1 16M bytes 0x1 4 4K 256 4M 16 bits 1 8M bytes 0x0 2 2K 256 1M 16 bits 1 2M bytes Default 0x0 SDRAM Refresh Register SDRAMC_REF Register name Address Bit Name Function Setting Init R W Remarks SDRAM Refresh Control Register SDRAMC_REF 0x302208 32 bits D31 26 reserved 0 when being read D25 SREFDO SDRAM self refres...

Page 141: ...be specified 3 Read SREFDO to check if self refresh mode is canceled SREFDO 1 D 22 16 SELCO 6 0 SDRAM Self Refresh Counter Bits Sets the value for the self refresh counter Default 0x7f If SELEN is set to 1 self refresh enabled the self refresh counter starts counting up on the SDCLK clock edges beginning with 0 after accessing or auto refreshing the SDRAM When the count specified here is reached t...

Page 142: ...Hz max Set DBF to 0 to use the SDRAM clock at the same frequency as the CPU clock 60 MHz max D4 Reserved D 3 2 CAS 1 0 CAS Latency Setup Bits Sets the CAS latency CAS latency refers to the number of SDCLK clock cycles counted until data is output from the SDRAM after issuing the READ command 7 7 CAS Latency Settings Table 10 CAS 1 0 CAS latency 0x3 3 0x2 2 0x1 1 0x0 Reserved Default 0x2 D1 Reserve...

Page 143: ...with specification of the interrupt level An automatic flush function is provided for the instruction cache to work in response to software PC break in de bugging The instruction cache RAM and data cache RAM can be used as a general purpose RAM when the cache func tion is disabled 1 1 Table 11 Cache Speed Status Number of cycles Reading from the instruction or data cache upon hitting 2 cycles 1 Co...

Page 144: ...ing four lines 4 4 words and one Way consists of four frames Four frames located at the corresponding area in each Way are managed under one LRU entry Data to a cache from the external memory are loaded in units of a line four words Figure 11 2 2 shows the cache configuration Frame 0 Frame 1 Frame 2 Frame 3 TAG DATA Way 0 Way 1 Way 2 Way 3 Line 3 Line 2 Line 1 Line 0 Way 0 Way 1 Way 2 Way 3 2 2 Ca...

Page 145: ...he data cache in ARDC 2 0 CCU_AREA register respectively 3 2 1 Selecting Area to Be Cached Table 11 ARIC 2 0 ARDC 2 0 Areas to be cached 0x7 Area 22 0x80000000 to 0xffffffff 0x6 Area 21 0x40000000 to 0x7fffffff 0x5 Area 20 0x20000000 to 0x3fffffff 0x4 Area 19 0x10000000 to 0x1fffffff 0x3 Area 18 0x0c000000 to 0x0fffffff 0x2 Area 17 0x08000000 to 0x0bffffff 0x1 Areas 15 and 16 0x04000000 to 0x07fff...

Page 146: ...cached from the external memory At this stage which Way is hit is determined If no matching Way is found in Step 3 it is judged as mishit For example if Way 0 is hit at A 7 6 0b01 A 5 4 0b10 and A 3 2 0b11 reading writing is performed from to Way 0 Frame 1 Line 2 W3 in the cache memory Reading Operation 11 3 4 The following describes operations for cases where any data are hit or not hit in readin...

Page 147: ... to a low speed external device Flush 11 3 6 Flushing refers to nullifying all data in the cache To flush the instruction cache set IC CCU_CFG register to 0 to disable the instruction cache To flush the data cache set DC CCU_CFG register to 0 to disable the data cache Set these bits back to 1 to enable the caches again Note that the cache is flushed several cycles after writing 0 to IC or DC Befor...

Page 148: ...in the a target area for caching Cache Data Integrity 11 6 The CCU does not support a snooping function for maintaining the data in the cache memory to match those in the external memory The cache and the external memory are maintained in synch if reading writing is only executed in the C33 PE Core When data are transferred to the area subject to caching via DMAC or when data are written to the pr...

Page 149: ...everal cycles after writing 0 to IC Before resuming caching operation check ICS CCU_STAT register to ensure that flushing is completed D0 DC Data Cache Enable Bit Enables the data cache 1 R W Enabled 0 R W Disable default By setting DC to 1 addresses 0x1fc00 to 0x1ffff 1KB in Area 0 are set for use as the data cache after which the cache is used for reading data from the specified area Data is wri...

Page 150: ...nlock 0 R W D2 LKPRI2 Interrupt level 2 cache lock enable 1 Lock 0 Unlock 0 R W D1 LKPRI1 Interrupt level 1 cache lock enable 1 Lock 0 Unlock 0 R W D0 LKPRI0 Interrupt level 0 cache lock enable 1 Lock 0 Unlock 0 R W D 31 8 Reserved D 7 0 LKPRI 7 0 Interrupt Level 7 0 Cache Lock Enable Bits Selects the interrupt levels to lock the cache the interrupt levels of the interrupt handler routines to dis ...

Page 151: ...e data cache Default undefined 1 R Active 0 R Inactive Setting DC CCU_CFG register to 1 activates the data cache and sets DCS to 1 Setting DC to 0 flushes the data cache and disables caching Note that the data cache is flushed several cycles after writing 0 to DC When flushing finishes DCS is reset to 0 To resume caching after flushing check that flushing has completed by reading DCS Cache Write B...

Page 152: ...egister name Address Bit Name Function Setting Init R W Remarks CCLK Division Ratio Select Register CCU_ CCLKDV 0x302360 32 bits D31 2 reserved 0 when being read D1 0 CLK_ DOWN 1 0 CCLK division ratio select CLK_DOWN 1 0 Division ratio 0x0 R W Source clock MCLK 0x3 0x2 0x1 0x0 1 8 1 4 1 2 1 1 D 31 2 Reserved D 1 0 CLK_DOWN 1 0 CCLK Division Ratio Select Bits Selects the division ratio to set the C...

Page 153: ... systems USB interrupt one system Supports seven interrupt levels 1 to 7 to prioritize the interrupt sources The ITC enables the interrupt level priority for determining the processing sequence when multiple interrupts oc cur simultaneously to be set for each interrupt system separately Each interrupt system includes one or more interrupt causes Settings to enable or disable interrupts for differe...

Page 154: ... 2 FPT8 B input rising falling edge or high low level 19 0x13 TTBR 0x4c Port input interrupt 3 FPTC F input rising falling edge or high low level 20 0x14 TTBR 0x50 DMAC Ch 0 2 interrupt End of DMA transfer 21 0x15 TTBR 0x54 DMAC Ch 1 3 interrupt End of DMA transfer 22 0x16 TTBR 0x58 DMAC Ch 4 6 interrupt End of DMA transfer 23 0x17 TTBR 0x5c DMAC Ch 5 7 interrupt End of DMA transfer 24 0x18 TTBR 0...

Page 155: ...bled the flag state will be sent to the ITC as an interrupt request signal generating an interrupt request to the C33 PE Core The corresponding interrupt enable bits should be set to 0 for those causes for which interrupts are not desired In this case although the interrupt flag is set to 1 if the interrupt cause occurs the interrupt request signal sent to the ITC will not be asserted The interrup...

Page 156: ...300219 16 bit PWM timer T16A5 Ch 1 interrupt ITC_T16A1_LV 0x30021a LCDC interrupt ITC_LCDC_LV 0x30021b 8 bit timer T8 Ch 0 4 interrupt ITC_T804_LV 0x30021d 8 bit timer T8 Ch 1 5 interrupt ITC_T815_LV 0x30021e 8 bit timer T8 Ch 2 6 interrupt ITC_T826_LV 0x30021f 8 bit timer T8 Ch 3 7 interrupt ITC_T837_LV 0x300220 USI interrupt ITC_USI_LV 0x300221 FSIO Ch 0 interrupt ITC_FSIO0_LV 0x300222 A D conve...

Page 157: ... to the vector table s starting address 28 bytes This interrupt takes precedence over other interrupts and is unconditionally accepted by the C33 PE Core For detailed information on generating NMI by the watchdog timer see the Watchdog Timer WDT chapter Software Exception 12 5 A software exception can be generated by use of int imm2 instruction of the C33 PE Core A software exception number 0 to 3...

Page 158: ...LV FSIO Ch 1 Interrupt Level Register Set FSIO Ch 1 interrupt level 0x300227 ITC_USIL_LV USIL Interrupt Level Register Set USIL interrupt level 0x300228 ITC_REMC_LV REMC Interrupt Level Register Set REMC interrupt level 0x300229 ITC_I2S_LV I2S Interrupt Level Register Set I2S interrupt level 0x30022a ITC_GECOM_LV GE Complete Interrupt Level Register Set GE complete interrupt level 0x30022b ITC_GEE...

Page 159: ... including IVRAM relocated to Area 0 cannot be specified as the transfer source and destination Transfer data size 8 bits 16 bits or 32 bits Transfer mode 1 Single transfer one unit of data is transferred by one trigger 2 Successive transfer specified number of data are transferred by one trigger with 12 bit transfer counter Transfer address control The source and or destination addresses can be f...

Page 160: ...Base 0xa0 Base 0x90 Base 0x80 Base 0x70 Base 0x60 Base 0x50 Base 0x40 Base 0x30 Base 0x20 Base 0x10 Base Ch 0 control table Ch 0 auto reload data area Ch 1 control table Ch 1 auto reload data area Ch 2 control table Ch 2 auto reload data area Ch 3 control table Ch 3 auto reload data area Ch 4 control table Ch 4 auto reload data area Ch 5 control table Ch 5 auto reload data area Ch 6 control table ...

Page 161: ...x68 Ch 4 Base 0x88 Ch 5 Base 0xa8 Ch 6 Base 0xc8 Ch 7 Base 0xe8 D31 0 DSADR 31 0 Destination address 0x0 to 0xffffffff 4th word 32 bits Ch 0 Base 0xc Ch 1 Base 0x2c Ch 2 Base 0x4c Ch 3 Base 0x6c Ch 4 Base 0x8c Ch 5 Base 0xac Ch 6 Base 0xcc Ch 7 Base 0xec D31 16 PTBASE 31 16 Pointer base address high order 16 bits 0x0 to 0xffff PTBASE 31 0 0x0 to 0xffff0000 D15 0 PTBASE 15 0 Fix at 0 Pointer base a...

Page 162: ...the transfer unit 3 2 2 Transfer Data Unit Table 13 UNIT 2 0 Transfer data unit 0x7 0x3 Reserved 0x2 32 bits 0x1 16 bits 0x0 8 bits SRINC 1 0 Source address control D 7 6 1st word Sets the control method for the source address after a unit data transfer 3 2 3 Source Address Control Table 13 SRINC 1 0 Source address control 0x3 0x2 Reserved 0x1 Increment 0x0 Fixed SRINC 1 0 0x0 Address fixed The so...

Page 163: ...re required TM 1 Successive transfer mode In this mode one trigger performs data transfer a number of times as set by the transfer counter The transfer counter is decremented each time a unit data is transferred and successive transfers end when the counter reaches 0 RELOAD Auto reload enable D1 1st word Enables or disables the auto reload function The auto reload function resets the initial value...

Page 164: ...conditions to the auto reloading area The control information written to the auto reloading area is loaded to the control table upon completion of the first data transfer and it will control the second data transfer If the auto reload function is not used the control table must be reset to the subsequent transfer condi tions in the DMAC interrupt handler routine The address of the auto reload data...

Page 165: ...he T16A5 channel for invoking the DMAC using DMASEL 1 0 T16A_CTLx register Default 0x0 At initial reset TRG_SELx 1 0 in all channels are set to 0x0 hardware trigger disabled Note that software triggers are enabled regardless of the trigger source selected These trigger sources causes of interrupt are used in common for interrupt requests and DMAC invocation re quests When interrupts due to the cau...

Page 166: ...6 bits or 32 bits Increment address Transfer counter 1 Store control information DMAC interrupt request Read source data pointer 8 bits or 16 bits ST 1 No data Yes pointer SRINC DSINC 1 0 0x0 address fixed 0x1 address increment Transfer counter 0 No Yes CHEN 1 No channel disabled Yes channel enabled 5 1 1 Figure 13 Operation Flow in Single Transfer Mode 1 When the DMAC accepts a trigger it loads t...

Page 167: ...quest to the ITC This completes the single transfer process Successive Transfer Mode 13 5 2 The channels for which TM D2 1st word in control information is set to 1 operate in the successive transfer mode In this mode a data transfer is performed by one trigger a number of times as set by the transfer counter The operation in the successive transfer mode is shown by the flow chart in Figure 13 5 2...

Page 168: ...o it writes the modified control information back to the control table If DMAIEx DMAC_IE register is set to 1 end of transfer interrupt enabled the DMAC outputs an interrupt request to the ITC This completes the successive transfer process Suspending successive transfers due to other high priority DMA request Successive transfers can be temporarily suspended due to occurrence of a high priority DM...

Page 169: ...n as 0 and not 1 DMAC Channel Enable Register DMAC_CH_EN Register name Address Bit Name Function Setting Init R W Remarks DMAC Channel Enable Register DMAC_CH_EN 0x302100 32 bits D31 8 reserved 0 when being read D7 DMAON7 DMAC Ch 7 enable 1 Enable 0 Disable 0 R W D6 DMAON6 DMAC Ch 6 enable 1 Enable 0 Disable 0 R W D5 DMAON5 DMAC Ch 5 enable 1 Enable 0 Disable 0 R W D4 DMAON4 DMAC Ch 4 enable 1 Ena...

Page 170: ...1 Control Table Map Figure 13 Note The control table must be placed on DSTRAM IVRAM Area 3 or an external RAM IRAM and BBRAM cannot be used to store control information DMAC Interrupt Enable Register DMAC_IE Register name Address Bit Name Function Setting Init R W Remarks DMAC Interrupt Enable Register DMAC_IE 0x302108 32 bits D31 8 reserved 0 when being read D7 DMAIE7 DMAC Ch 7 interrupt enable 1...

Page 171: ...I Rx No hard trigger D3 2 TRG_SEL1 1 0 Ch 1 trigger select TRG_SEL1 1 0 Trigger source 0x0 R W 0x3 0x2 0x1 0x0 USB Port I2S R No hard trigger D1 0 TRG_SEL0 1 0 Ch 0 trigger select TRG_SEL0 1 0 Trigger source 0x0 R W 0x3 0x2 0x1 0x0 ADC complete T16P I2S L No hard trigger D 31 16 Reserved D 15 0 TRG_SELx 1 0 Ch x Trigger Select Bits Selects a trigger source for each DMAC channel 7 2 DMAC Table 13 T...

Page 172: ... W D2 TRG2 Ch 2 software trigger trigger status 0 R W D1 TRG1 Ch 1 software trigger trigger status 0 R W D0 TRG0 Ch 0 software trigger trigger status 0 R W D 31 8 Reserved D 7 0 TRGx Ch x Software Trigger Trigger Status Bit Invokes a DMA of the specified channel by software trigger Also indicates trigger status in respective channels including hardware trigger 1 W Software trigger 0 W Ignored 1 R ...

Page 173: ...ister in the DMAC interrupt handler routine and check which channel has finished trans fers Also in preparation for next interrupts write 1 to ENDFx for resetting it In a channel with DMAIEx is set to 0 interrupt disabled an interrupt is not generated even if ENDFx is set DMAC Running Status Register DMAC_RUN_STAT Register name Address Bit Name Function Setting Init R W Remarks DMAC Running Status...

Page 174: ... the successive transfer operation is suspended due to a high priority DMA transfer or not 1 R Suspended 0 R Status other than suspension default When a DMA request is generated that has higher priority than that of the channel in operation the channel performing a transfer saves control information required for resuming transfers such as the current transfer count and the transfer source and dest...

Page 175: ...Ch 3 To ADC10 from T8 Ch 2 From PSC Ch 0 to T8 Ch 0 2 4 6 From PSC Ch 1 to T8 Ch 1 3 5 7 Timer reset Serial transfer clock Down counter T8_TCx Control circuit PRESER TFMD 3 0 8 bit Timer Ch x Count clock select 1 1 T8 Configuration one channel Figure 14 T8 consists of an 8 bit presettable down counter and an 8 bit reload data register holding the preset value The timer counts down from the initial...

Page 176: ...r presets the reload data register value into the counter and continues the count Thus the timer periodically outputs an underflow pulse T8 should be set to this mode to generate periodic in terrupts or A D triggers at desired intervals or to generate a serial transfer clock One shot mode TRMD 1 Setting TRMD to 1 sets T8 to one shot mode In this mode the timer stops automatically as soon as the co...

Page 177: ...d set it to the reload data register See Section 14 4 4 Reset the timer to preset the counter to the initial value See Section 14 5 5 When using timer interrupts set the interrupt level and enable interrupts for the relevant timer channel See Section 14 9 To start T8 write 1 to PRUN T8_CTLx register The timer starts counting down from the initial value or from the current counter value if no initi...

Page 178: ...3 output clock USIL T8 Ch 2 output clock A D converter Underflow signal Timer output serial transfer clock A D trigger signal Interrupt request to the ITC 7 1 Timer Output Clock Figure 14 Fine Mode Ch 0 to Ch 3 14 8 Ch 0 to Ch 3 support fine mode to minimize transfer rate errors T8 can output a programmable clock signal for use as the USI serial transfer clock The timer output clock can be set to ...

Page 179: ...preventing insertion of delay cycles T8 Interrupts 14 9 T8 outputs an interrupt request to the interrupt controller ITC when the counter underflows Timer underflow interrupt When the counter underflows the interrupt flag T8IF T8_INTx register which is provided for each channel in the T8 module is set to 1 At the same time an interrupt request is sent to the ITC if T8IE T8_INTx register has been se...

Page 180: ...Register Set reload data 0x301124 T8_TC2 T8 Ch 2 Counter Data Register Counter data 0x301126 T8_CTL2 T8 Ch 2 Control Register Set timer mode and start stop timer 0x301128 T8_INT2 T8 Ch 2 Interrupt Control Register Control interrupt 0x301130 T8_CLK3 T8 Ch 3 Input Clock Select Register Select prescaler output clock 0x301132 T8_TR3 T8 Ch 3 Reload Data Register Set reload data 0x301134 T8_TC3 T8 Ch 3 ...

Page 181: ...he T8 count clock 10 2 Count Clock PCLK Division Ratio Selection Table 14 DF 3 0 Division ratio DF 3 0 Division ratio 0xf Reserved 0x7 1 128 0xe 1 16384 0x6 1 64 0xd 1 8192 0x5 1 32 0xc 1 4096 0x4 1 16 0xb 1 2048 0x3 1 8 0xa 1 1024 0x2 1 4 0x9 1 512 0x1 1 2 0x8 1 256 0x0 1 1 Source clock PCLK1 for T8 Ch 0 2 4 6 or PCLK2 for T8 Ch 1 3 5 7 Default 0x0 Note Make sure the counter is halted before sett...

Page 182: ... W D3 2 reserved 0 when being read D1 PRESER Timer reset 1 Reset 0 Ignored 0 W D0 PRUN Timer run stop control 1 Run 0 Stop 0 R W D 15 12 Reserved D 11 8 TFMD 3 0 Fine Mode Setup Bits Ch 0 to Ch 3 Corrects the transfer rate error Default 0x0 TFMD 3 0 specifies the delay pattern to be inserted into a 16 underflow period Inserting one delay extends the output clock cycle by one count clock cycle This...

Page 183: ...e Note Make sure the counter is halted before setting the count mode D 3 2 Reserved D1 PRESER Timer Reset Bit Resets the timer 1 W Reset 0 W Ignored 0 R Always 0 when read default Writing 1 to this bit presets the counter to the reload data value D0 PRUN Timer Run Stop Control Bit Controls the timer RUN STOP 1 R W Run 0 R W Stop default The timer starts counting when PRUN is written as 1 and stops...

Page 184: ...ag Bit Indicates whether the cause of counter underflow interrupt has occurred or not 1 R Cause of interrupt has occurred 0 R No cause of interrupt has occurred default 1 W Flag is reset 0 W Ignored T8IF is the T8 interrupt flag that is set to 1 when the counter underflows T8IF is reset by writing 1 ...

Page 185: ...s of a counter block and a comparator capture block Counter block The counter block includes a 16 bit up counter that operates with a prescaler output clock or the external count clock input from outside the IC The 16 bit PWM timer T16A5 allows software to run and stop the counter and to reset the counter value cleared to 0 as well as selection of the count clock The counter can also be reset by t...

Page 186: ...register T16A5 Input Output Pins 15 2 Table 15 2 1 lists the input output pins for the T16A5 module 2 1 List of T16A5 Pins Table 15 Pin name I O Qty Function T16A_EXCL_0 Ch 0 T16A_EXCL_1 Ch 1 I 2 T16A5 external clock input pin Inputs an external clock for the event counter function The T16A_EXCL_0 pin can also be used as the WDT external clock input pin T16A_ATMA_0 Ch 0 T16A_ATMA_1 Ch 1 I O 2 T16A...

Page 187: ...parator asserts the compare B signal At the same time the compare B interrupt flag is set and an interrupt signal is output to the ITC if the interrupt is enabled Furthermore the counter is reset to 0 Note The intervals of the compare A and compare B interrupts must be longer than three count clock cycles Otherwise the second interrupt will be omitted by T16A5 The compare A and compare B signals a...

Page 188: ...register Notes The correct captured data may not be obtained if the captured data is read at the same time the next value is being captured Read the capture register twice to check if the read data is correct as necessary To capture counter data properly both the High and Low period of the T16A_ATMA_x T16A_ ATMB_x trigger signal must be longer than three count clock cycles The setting of CAPATRG 1...

Page 189: ...ops the count This control does not affect the counter data The counter data is retained even when the count is halted allowing resumption of the count from that data If PRUN and PRESET are written as 1 simultaneously the counter starts counting after reset Notes Always make sure that BUSY T16A_CTLx register is set to 0 idle before writing to the T16A_ CTLx register Setting PRUN to 1 may not start...

Page 190: ...UTBINV T16A_ATMB_x pin Comparator capture block 6 1 TOUT Output Circuit Figure 15 T16A5 includes two TOUT output circuits and their signal generation and output can be controlled individually Al though the output circuit and register names use letters A and B to distinguish two systems it does not mean that they correspond to compare A and B signals Note The compare A and compare B signals can be ...

Page 191: ... PRUN Counter value Compare A signal Compare B signal TOUT T16A_ATMA_x output TOUTAMD 1 0 0x0 TOUTAINV 0 TOUTAMD 1 0 0x0 TOUTAINV 1 TOUTAMD 1 0 0x1 TOUTAINV 0 TOUTAMD 1 0 0x1 TOUTAINV 1 TOUTAMD 1 0 0x2 TOUTAINV 0 TOUTAMD 1 0 0x2 TOUTAINV 1 TOUTAMD 1 0 0x3 TOUTAINV 0 TOUTAMD 1 0 0x3 TOUTAINV 1 1 2 3 4 5 0 0 1 2 3 4 5 0 1 2 3 4 5 0 1 When T16A_CCAx 3 T16A_CCBx 5 6 2 TOUT Output Waveform Figure 15 T1...

Page 192: ...C Capture B interrupt This interrupt request is generated when the counter value is captured in the capture B register by an exter nal trigger during counting in capture mode It sets the interrupt flag CAPBIF T16A_IFLGx register in the T16A5 module to 1 To use this interrupt set CAPBIE T16A_IENx register to 1 If CAPBIE is set to 0 default interrupt re quests for this cause is not sent to the ITC C...

Page 193: ... PWM Timer T16A5 Register Table 15 Address Register name Function 0x301180 T16A_CTL0 T16A5 Ch 0 Counter Control Register Control counter 0x301182 T16A_TC0 T16A5 Ch 0 Counter Data Register Counter data 0x301184 T16A_CCCTL0 T16A5 Ch 0 Comparator Capture Control Register Control comparator capture block and TOUT 0x301186 T16A_CCA0 T16A5 Ch 0 Comparator Capture A Data Register Compare A capture A data...

Page 194: ...ESET Counter reset 1 Reset 0 Ignored 0 W 0 when being read D0 PRUN Counter run stop control 1 Run 0 Stop 0 R W T16A5 Ch 1 Counter Control Register T16A_CTL1 0x301190 16 bits D15 14 reserved 0 when being read D13 12 DMASEL 1 0 DMAC channel select DMASEL 1 0 DMAC channel 0x1 R W 0x3 0x2 0x1 0x0 Ch 4 5 Ch 2 3 Ch 4 5 Ch 2 3 D11 8 CLKS 3 0 Counter clock division ratio select CLKS 3 0 Division ratio 0x0...

Page 195: ...USY Register Writing Status Bit Indicates the T16A5 register writing status 1 R Busy 0 R Idle default BUSY goes 1 when data is written to the T16A_CTLx T16A_CCAx or T16A_CCBx register and it reverts to 0 upon completion of the writing operation Note Make sure that BUSY is set to 0 before writing to these registers D6 Reserved D 5 4 T16SEL 1 0 Counter Select Bits Selects the counter channel 8 4 Cou...

Page 196: ...it resets the counter to 0 D0 PRUN Counter Run Stop Control Bit Starts stops the count 1 W Run 0 W Stop 1 R Counting 0 R Stopped default The counter starts counting when PRUN is written as 1 and stops when written as 0 The counter data is retained even if the counter is stopped T16A5 Ch x Counter Data Registers T16A_TCx Register name Address Bit Name Function Setting Init R W Remarks T16A5 Ch x Co...

Page 197: ...Selects the trigger edge s of the external signal T16A_ATMB_x input at which the counter value is captured in the capture B register 8 5 Capture B Trigger Edge Selection Table 15 CAPBTRG 1 0 Trigger edge 0x3 Falling edge and rising edge 0x2 Falling edge 0x1 Rising edge 0x0 Not triggered Default 0x0 CAPBTRG 1 0 are control bits for capture mode and are ineffective in comparator mode D 13 12 TOUTBMD...

Page 198: ...form T16A_ATMA_x output is changed by the compare A and compare B signals These bits are also used to turn the TOUT A output on and off 8 8 TOUT A Generation Mode Table 15 TOUTAMD 1 0 When compare A occurs When compare B occurs 0x3 No change Toggle 0x2 Toggle No change 0x1 Rise Fall 0x0 Disable output Default 0x0 TOUTAMD 1 0 are control bits for comparator mode and are ineffective in capture mode ...

Page 199: ...ured value is loaded to this register At the same time a capture A interrupt can be generated thus the captured counter value can be read out in the interrupt handler T16A5 Ch x Comparator Capture B Data Registers T16A_CCBx Register name Address Bit Name Function Setting Init R W Remarks T16A5 Ch x Comparator Capture B Data Register T16A_CCBx 0x301188 0x301198 16 bits D15 0 CCB 15 0 Compare captur...

Page 200: ...nable Bit Enables or disables capture B interrupts 1 R W Interrupt enabled 0 R W Interrupt disabled default Setting CAPBIE to 1 enables capture B interrupt requests to the ITC Setting it to 0 disables interrupts D2 CAPAIE Capture A Interrupt Enable Bit Enables or disables capture A interrupts 1 R W Interrupt enabled 0 R W Interrupt disabled default Setting CAPAIE to 1 enables capture A interrupt r...

Page 201: ...terrupt Flag Bit Indicates whether the cause of capture B interrupt has occurred or not 1 R Cause of interrupt has occurred 0 R No cause of interrupt has occurred default 1 W Flag is reset 0 W Ignored CAPBIF is a T16A5 interrupt flag that is set to 1 when the counter value is captured in the capture B register CAPBIF is reset by writing 1 D2 CAPAIF Capture A Interrupt Flag Bit Indicates whether th...

Page 202: ...ndicates whether the cause of compare A interrupt has occurred or not 1 R Cause of interrupt has occurred 0 R No cause of interrupt has occurred default 1 W Flag is reset 0 W Ignored CAIF is a T16A5 interrupt flag that is set to 1 when the counter reaches the value set in the compare A register CAIF is reset by writing 1 ...

Page 203: ...Supports 8 bit and 16 bit PCM data with varied sample rates 8 16 22 05 32 44 1 and 48 kHz Supports both signed and unsigned PCM data Supports split mode 16 bit audio data can be split into 10 bits 6 bits 9 bits 7 bits or 8 bits 8 bits Supports fine mode to improve the precision of the pulse width Includes a digital volume control unit Programmable count clocks using the prescaler or an external cl...

Page 204: ... PWM signal output pin In a split mode Outputs the PWM signal generated from the low order PCM data bits In normal mode Fixed at the initial output level or not used The T16P input output pins PWM_EXCL PWM_H PWM_L are shared with I O ports and are initially set as general purpose I O port pins The pin functions must be switched using the port function select bits to use the gen eral purpose I O po...

Page 205: ... the PWM_L pin is fixed at the level set by INITOL In this case the PWM_L pin can be used for a GPIO or other function Data format T16P supports signed and unsigned PCM data Use SGNSEL T16P_CTL register to select the data format When SGNSEL is set to 1 default signed data format is selected when set to 0 unsigned data format is se lected Note When signed audio data is selected CMPA15 T16P_A regist...

Page 206: ...when compared Count clock PCLK1 Counter PWM_H output in normal comparison mode PWM_H output in fine mode Compare A data 3 Compare B data 5 1 2 3 4 5 0 0 1 2 3 4 5 0 1 3 3 2 Fine Mode Figure 16 The fine mode improves the precision of the pulse width Note however that the PCLK1 1 clock can only be used as the count clock in this mode CLKSEL and CLKDIV 3 0 settings are ineffective Set SELFM T16P_CTL ...

Page 207: ...6P being run write 0 to PRUN The compare data buffers registers and counter retain the value at stop The PWM output is fixed at the level set by INITOL Note that T16P may not stop counting until B match condi tions occur BCNT 3 0 1 times Setting Compare Data 16 4 3 Compare A buffer The compare A buffer CMPA 15 0 T16P_A register is used to specify output pulse widths duty cycles Set output audio da...

Page 208: ...L to 0 The volume control unit multiplies the PCM data stored in the compare A buffer by the specified volume level set using VOL SEL 6 0 T16P_VOL_CTL register before loading to the compare A register This makes it possible to adjust the volume level to 1 64 through 127 64 as well as muting 4 4 1 Volume Level Settings Table 16 VOLSEL 6 0 Volume level 0x7f 127 64 0x7e 126 64 0x40 64 64 0x2 2 64 0x1...

Page 209: ... INITOL 0 PWM_L output INITOL 0 PWM_H output INITOL 1 PWM_L output INITOL 1 Buffer empty interrupt A match interrupt B match interrupt 1 2 3 4 5 0 0 0 3 4 1 2 3 4 5 0 1 2 3 4 5 0 1 0 5 5 2 3 4 5 0 1 When BCNT 3 0 1 4 6 1 PWM Output Timing Chart 1 normal mode Figure 16 Normal fine mode Count clock PCLK1 PRESET PRUN Compare data load Compare A register Compare B register Counter A match signal B mat...

Page 210: ...AH 2 AL 4 1 2 3 4 5 0 1 2 3 4 5 0 1 0 5 5 2 3 4 5 0 1 When BCNT 3 0 1 not occurred 4 6 3 PWM Output Timing Chart 3 split mode Figure 16 Split fine mode Count clock PCLK1 PRESET PRUN Compare data load Compare A register Compare B register Counter AH match signal AL match signal B match signal PWM_H output INITOL 0 PWM_L output INITOL 0 PWM_H output INITOL 1 PWM_L output INITOL 1 Buffer empty interr...

Page 211: ... enabled Writing 1 to PRUN enables T16P to issue buffer empty interrupts and DMA requests so that the first audio data can be sent to the buffer in the interrupt handler routine or DMA A match interrupt This interrupt request is generated when the counter reaches the compare A register value during counting It sets the interrupt flag INTAF T16P_INT register in the T16P module to 1 To use this inte...

Page 212: ...fer Register T16P_A 0x301200 16 bits D15 0 CMPA 15 0 Compare A data CMPA15 MSB CMPA0 LSB 0x0 to 0xffff X R W D 15 0 CMPA 15 0 Compare A Data Bits Sets compare A data PCM data to be converted to a pulse width Default undefined The buffer data is loaded to the compare A register when the timer starts counting or when a B match occurs specified number of times and is compared with the counter value T...

Page 213: ... cycle BCNT 3 0 1 T16P Counter Data Register T16P_CNT_DATA Register name Address Bit Name Function Setting Init R W Remarks T16P Counter Data Register T16P_CNT_ DATA 0x301204 16 bits D15 0 CNT_DATA 15 0 Counter data CNT_DATA15 MSB CNT_DATA0 LSB 0x0 to 0xffff X R W D 15 0 CNT_DATA 15 0 Counter Data Bits The counter data can be read from this register Default undefined Furthermore data can be set to...

Page 214: ...W D2 reserved 0 when being read D1 PRESET T16P reset 1 Reset 0 Ignored 0 W D0 reserved D 15 12 BCNT 3 0 B Match Count Bits Sets the B match counter Default 0x0 When a B match occurs BCNT 3 0 1 times the compare A and B buffer data are loaded into the compare A and B registers D11 RESSEL PCM Data Resolution Select Bit Selects the PCM data resolution 1 R W 16 bits default 0 R W 8 bits Notes When 8 b...

Page 215: ...s time the compare A data is halved when compared Count clock PCLK1 Counter PWM_H output in normal comparison mode PWM_H output in fine mode Compare A data 3 Compare B data 5 1 2 3 4 5 0 0 1 2 3 4 5 0 1 6 1 Fine Mode Figure 16 The fine mode improves the precision of the pulse width Note however that the PCLK1 1 clock can only be used as the count clock in this mode CLKSEL and CLKDIV 3 0 settings a...

Page 216: ...celed DMA request is canceled if it has been issued The PWM outputs go to the initial output level set by INITOL Note Be sure to reset T16P before the GPIO pins are switched to the PWM_H and PWM_L pins and before setting PRUN T16P_RUN register to 1 to start T16P D0 Reserved T16P Running Control Register T16P_RUN Register name Address Bit Name Function Setting Init R W Remarks T16P Running Control ...

Page 217: ...lock When T16P is set to fine mode CLKDIV 3 0 is ineffective and PCLK1 is directly used as the count clock T16P Interrupt Control Register T16P_INT Register name Address Bit Name Function Setting Init R W Remarks T16P Interrupt Control Register T16P_INT 0x30120e 16 bits D15 11 reserved 0 when being read D10 BUFEF Buffer empty interrupt flag 1 Cause of interrupt occurred 0 Cause of interrupt not oc...

Page 218: ...ot 1 R Cause of interrupt has occurred 0 R No cause of interrupt has occurred default 1 W Flag is reset 0 W Ignored INTAF is a T16P interrupt flag that is set to 1 when the counter reaches the value set in the compare A register INTAF is reset by writing 1 D 7 3 Reserved D2 INTBEEN Buffer Empty Interrupt Enable Bit Enables or disables buffer empty interrupts 1 R W Interrupt enabled 0 R W Interrupt...

Page 219: ...ftware so as not to generate NMI or internal reset signals it is possible to detect a program running uncontrollably that does not ex ecute that processing routine The PCLK2 clock system clock or external clock input for the 16 bit PWM timer T16A5 T16A_EXCL_0 can be selected as the count clock for the watchdog timer Moreover a clock can be generated synchronously with NMI reset generation cycles s...

Page 220: ...erating cycle s fWDTIN where CMPDT value set to CMPDT 29 0 fWDTIN Input clock PCLK2 or T16A_EXCL_0 frequency Hz Note Do not set a value equal to or less than 0x1f in the comparison data register Selecting the NMI reset generation function To output an NMI signal when the watchdog timer is not reset within a specified cycle set NMIEN WD_EN register to 1 To output a reset signal instead set RESEN WD...

Page 221: ...rite 0 to RUNSTP WD_EN register to stop the watchdog timer before executing the halt instruc tion When NMIEN or RESEN disables NMI or reset generation the watchdog timer continues counting even in HALT mode To reenable NMI or reset generation after exiting HALT mode be sure to reset the watchdog timer beforehand When HALT mode is entered after stopping the watchdog timer be sure to reset the watch...

Page 222: ...es When data is written to the registers the Reserved bits must always be written as 0 and not 1 The WD_PROTECT register 0x301000 allows 16 bit access only Other registers 0x301002 to 0x30100c allow 8 bit access as well as 16 bit access WDT Write Protect Register WD_PROTECT Register name Address Bit Name Function Setting Init R W Remarks WDT Write Protect Register WD_ PROTECT 0x301000 16 bits D15 ...

Page 223: ...CL_0 D5 CLKEN WDT Clock Output Control Bit This bit controls the clock output of the watchdog timer 1 R W On 0 R W Off default Setting this bit to 1 outputs an NMI reset generation cycle synchronous clock from the IC D4 RUNSTP WDT Run Stop Control Bit This bit starts or stops the watchdog timer 1 R W Start 0 R W Stop default When the NMI or reset generation function is enabled be sure to set compa...

Page 224: ...omparison data set in these registers When a clock is output from the watchdog timer these registers also set the output clock cycle Note Do not set a value equal to or less than 0x1f as comparison data WDT Count Data L H Registers WD_CNT_L WD_CNT_H Register name Address Bit Name Function Setting Init R W Remarks WDT Count Data L Register WD_CNT_L 0x301008 16 bits D15 0 CTRDT 15 0 WDT counter data...

Page 225: ...s Supports DMA transfer SPI master slave mode Data length 8 or 9 bits master mode or 8 bits fixed slave mode Supports both fast and normal modes master mode or normal mode only slave mode Data transfer timing clock phase and polarity variations is selectable from among 4 types Can generate receive buffer full transmit buffer empty and receive error interrupts Supports DMA transfer I2C master slave...

Page 226: ...c_sda I O 1 When USI is configured to I2C master or slave mode either the USI_DI pin or the USI_CS pin can be used as the data input output pin Note however that both the USI_DI and USI_CS pins cannot be used as the data input out put pin simultaneously 2 After a software reset all USI pins are set for input if USI has not been configured to any mode Note Use a GPIO port to output the slave select...

Page 227: ...ps DF Division ratio set by DF 3 0 T8_CLK0 register T8 Ch 0 TR Reload data to be set to the T8_TR0 register T8 Ch 0 TFMD Fine mode set value at TFMD 3 0 T8_CTL0 register T8 Ch 0 Example UART mode transfer rate 115 200 bps system clock 33 MHz DF 3 0 T8_CLK0 register setting T8 Ch 0 1 1 TFMD 3 0 T8_CTL0 register setting T8 Ch 0 14 TR 33 000 000 1 115 200 14 8 8 33 05 0x21 For more information on con...

Page 228: ...terface mode selected 5 Set interrupt and DMA transfer conditions if necessary See Section 18 7 6 Select the port functions to be used for USI according to the interface mode See Section 18 2 and the I O Ports GPIO chapter USI Module Software Reset 18 4 1 Writing 0x0 to USIMOD 2 0 USI_GCFG register resets the USI module circuits Be sure to perform software re set before setting the interface mode ...

Page 229: ...Set ting UPMD to 0 default adds a parity bit and checks for odd parity Setting UPMD to 1 adds a parity bit and checks for even parity Sampling clock UCHLN 0 UPREN 0 USTPB 0 UCHLN 0 UPREN 1 USTPB 0 UCHLN 0 UPREN 0 USTPB 1 UCHLN 0 UPREN 1 USTPB 1 UCHLN 1 UPREN 0 USTPB 0 UCHLN 1 UPREN 1 USTPB 0 UCHLN 1 UPREN 0 USTPB 1 UCHLN 1 UPREN 1 USTPB 1 s1 D0 D1 D2 D3 D4 D5 D6 s2 s1 D0 D1 D2 D3 D4 D5 D6 p s2 s1 ...

Page 230: ...t use the T8 The SPI slave mode uses the T8 output clock for generating the sampling clock Data length master mode only In SPI master mode the data length can be selected using SCHLN USI_SCFG register Setting SCHLN to 0 default configures the data length to 8 bits Setting SCHLN to 1 configures the data length to 9 bits In 9 bit mode 8 bit data is prefixed with a command bit 1 bit The command bit i...

Page 231: ...tten to the transmit buffer and reverts to 0 after both the shift register and transmit buffer become empty Sampling clock TD 7 0 Shift register USI_DO pin UTDIF UTBSY Interrupt start stop stop AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 parity parity BD0 Write Write Transmit buffer empty interrupt Reset by writing 1 Reset by writing 1 Transmit buffer empty interrupt MSB first Data A Data B start BD7 BD6 5 1 ...

Page 232: ...en data written to the transmit data buffer is sent to the transmit shift register STDIF is an interrupt flag An interrupt or DMA request can be generated when this flag is set to 1 see Section 18 7 Write subsequent data to the transmit data buffer to start the following transmission using this interrupt or DMA The transmit data buffer size is 1 byte but a shift register is provided separately to ...

Page 233: ...pleted Furthermore SRDIF must be reset by writing 1 While SRDIF is set to 1 the next received data will not be transferred from the shift register to the receive data buffer the first byte data exists in the receive data buffer and the second byte data exists in the shift register An overrun error occurs if the third byte data is received in this condition as the second byte data in the shift regi...

Page 234: ...erating When the specified operation has finished IMBSY is reset to 0 At the same time the interrupt flag IMIF USI_ IMIF register is also set to 1 After an interrupt occurs read the status bits IMSTA 2 0 USI_IMIF register to check the operation finished Then clear IMIF by writing 1 IMSTA 2 0 will be automatically cleared to 0x0 5 3 2 I Table 18 2 C Master Status Bits IMSTA 2 0 Status 0x7 Reserved ...

Page 235: ...ition I2C data transfer starts when the I2C master device generates a start condition The start condition applies when the SCL line is maintained at high and the SDA line is pulled down to low To generate a start condition in this I2C master set IMTGMOD 2 0 to 0x0 default and write 1 to IMTG SDA USI_DI SCL USI_CK Start condition 5 3 3 Start Condition Figure 18 IMBSY is set to 1 while a start condi...

Page 236: ...transmit shift reg ister IMBSY reverts to 0 and IMSTA 2 0 is set to 0x2 Confirm that the slave address each byte has been sent by reading IMBSY or using an interrupt After a slave address has been sent the selected slave device sends back an ACK by pulling down the SCL line to low If the SCL line maintains high it is regarded as a NAK In this case the I2C controller cannot communicate with the sla...

Page 237: ... to 0x1 and write 1 to IMTG Stop condition SDA USI_DI SCL USI_CK 5 3 6 Stop Condition Figure 18 IMBSY is set to 1 while a stop condition is being generated When the stop condition is generated IMBSY is reset to 0 and IMSTA 2 0 is set to 0x1 Read IMBSY or use an interrupt to check that a stop condition has been generated The I2C bus subsequently switches to free state 5 Generating repeated start co...

Page 238: ...he same as that of data transmission in I2C master mode However send the slave address with the transfer direction bit set to 1 Then check that the slave device sends back an ACK 3 Data reception To start data reception set IMTGMOD 2 0 to 0x3 and write 1 to IMTG This trigger starts outputting 8 clocks from the USI_CK pin The USI_DO pin status is sampled in sync with the clock and loaded to the shi...

Page 239: ... I2C slave mode Data transfer in I2C slave mode is controlled using ISTGMOD 2 0 USI_ISTG register and ISTG USI_ISTG register Select an I2C slave operation using ISTGMOD 2 0 and write 1 to ISTG as the trigger The I2C con troller controls the I2C bus to generate the specified operating status 5 3 3 Trigger List in I Table 18 2 C Slave Mode ISTGMOD 2 0 Trigger 0x7 Reserved 0x6 ACK NAK reception 0x5 N...

Page 240: ...on Data transmission NAK 0x6 0x6 0x2 0x3 Transfer data n D7 D6 D5 D4 D3 D2 D1 D0 ACK USI_CK pin output USI_CK pin input USI_DI pin output USI_DI pin input ISTGMOD 2 0 ISTG write ISBSY ISSTA 2 0 TD 7 0 ISIF Stop detection interrupt End of transmission interrupt Receive NAK interrupt Receive ACK interrupt 1 1 1 1 0x2 0x6 0x1 0x5 2 2 2 2 2 Data transmission Stop condition 1 When the USI_CK input is d...

Page 241: ...btain the remaining address bits Check whether the received address is matched to this I2C slave address or not When they are matched send back an ACK to the I2C master by setting ISTGMOD 2 0 to 0x4 and write 1 to ISTG ISBSY is set to 1 while an ACK is being sent and it reverts to 0 when the transmission has completed An interrupt request can be generated at this point When an ACK has been sent IS...

Page 242: ... 0x3 D7 D6 D5 D4 D3 D2 D1 D0 ACK USI_CK pin output USI_CK pin input USI_DI pin output USI_DI pin input ISTGMOD 2 0 ISTG write ISBSY ISSTA 2 0 RD 7 0 ISIF Stop detection interrupt 1 1 1 1 End of reception interrupt Transfer NAK interrupt Transfer ACK interrupt Received data n 1 Received data n 2 2 2 2 0x3 0x4 0x1 0x4 2 Data reception Stop condition 1 When the USI_CK input is detected as low after t...

Page 243: ...the ISSTA 2 0 value read during data reception is 0x1 the I2C master device has generated a stop condi tion see Figure 18 5 3 6 In this case abort data reception Clock stretch function While data is being sent received this I2C slave generates a clock stretch status by pulling down the SCL line to low to make a wait request to the master device after an ACK is sent received until the following dat...

Page 244: ... in the shift register is checked for parity when sent to the receive data buffer The match ing is checked against the UPMD USI_UCFG register setting odd or even parity If the result is a non match a parity error is issued and the parity error flag UPEIF USI_UIF register is set to 1 Even if this error occurs the data received is sent to the receive data buffer and the receiving operation continues...

Page 245: ...SPI Mode 18 7 2 The SPI master slave modes include a function for generating the following three different types of interrupts Transmit buffer empty interrupt Receive buffer full interrupt Receive error interrupt Transmit buffer empty interrupt To use this interrupt set STDIE USI_SIE register to 1 If STDIE is set to 0 default interrupt requests for this cause will not be sent to the ITC When trans...

Page 246: ...mine the I2C operation status that causes the inter rupt 7 3 1 I Table 18 2 C Master Status Bits IMSTA 2 0 Status 0x7 Reserved 0x6 NAK has been received 0x5 ACK has been received 0x4 ACK or NAK has been sent 0x3 End of receive data 0x2 End of transmit data 0x1 Stop condition has been generated 0x0 Start condition has been generated Default 0x0 Receive error interrupt To use this interrupt set IMEI...

Page 247: ...the receive data buffer USI_RD register twice DMA Transfer 18 7 5 The causes of receive buffer full and transmit buffer empty interrupts in UART and SPI master slave modes can invoke a DMA This allows continuous data transmission reception through DMA transfer between memory and transmit receive data buffers These interrupt signals are output to both the ITC and DMAC Therefore DMA trans fer can be...

Page 248: ...ects whether serial data will be transferred from the MSB or LSB 1 R W MSB first 0 R W LSB first default This setting affects all interface modes D 2 0 USIMOD 2 0 Interface Mode Configuration Bits Selects an interface mode 8 2 Interface Mode Selection Table 18 USIMOD 2 0 Interface mode 0x5 I2C slave 0x4 I2C master 0x3 SPI slave 0x2 SPI master 0x1 UART 0x0 Software reset Default 0x0 Perform softwar...

Page 249: ...n being read D3 UCHLN Character length select 1 8 bits 0 7 bits 0 R W D2 USTPB Stop bit select 1 2 bits 0 1 bit 0 R W D1 UPMD Parity mode select 1 Even 0 Odd 0 R W D0 UPREN Parity enable 1 With parity 0 No parity 0 R W Note This register is effective only in UART mode Configure USI to UART mode before setting this reg ister D 7 4 Reserved D3 UCHLN Character Length Select Bit Selects the serial tra...

Page 250: ...n to the transmit data buffer is sent to the shift register i e when data transmission begins 1 R W Enabled 0 R W Disabled default Set this bit to 1 to write data to the transmit data buffer using interrupts USI UART Mode Interrupt Flag Register USI_UIF Register name Address Bit Name Function Setting Init R W Remarks USI UART Mode Interrupt Flag Register USI_UIF 0x300442 8 bits D7 reserved 0 when ...

Page 251: ...t 1 R Error occurred 0 R No error default 1 W Reset to 0 0 W Ignored UOEIF is set to 1 when an overrun error occurs At the same time a receive error interrupt request is sent to the ITC if UEIE USI_UIE register is 1 An overrun error occurs if the next reception is com pleted when URDIF is 1 and the receive data buffer USI_RD register is not read an overrun error occurs at the time stop bit has bee...

Page 252: ...r mode Selects the serial transfer data length 1 R W 9 bits 0 R W 8 bits default In 9 bit mode 8 bit data is prefixed with a command bit 1 bit The command bit is used for control ling the SPI LCD controller connected to the USI The command bit value to be transmitted can be specified using SCMD SCHLN 0 SCMD SCHLN 1 SCMD 0 SCHLN 1 SCMD 1 Command bit D7 D0 D6 D1 D5 D2 D4 D3 D3 D4 D2 D5 D1 D6 D0 D7 D...

Page 253: ...t R W Remarks USI SPI Master Slave Mode Interrupt Enable Register USI_SIE 0x300451 8 bits D7 3 reserved 0 when being read D2 SEIE Receive error interrupt enable 1 Enable 0 Disable 0 R W D1 SRDIE Receive buffer full interrupt enable 1 Enable 0 Disable 0 R W D0 STDIE Transmit buffer empty int enable 1 Enable 0 Disable 0 R W Note This register is effective only in SPI master and slave modes Configure...

Page 254: ...n the master device clears the SPI controller selection by negating the slave select USI_CS signal D2 SEIF Overrun Error Flag Bit Indicates whether an overrun error has occurred or not 1 R Error occurred 0 R No error default 1 W Reset to 0 0 W Ignored SEIF is set to 1 when an overrun error occurs At the same time a receive error interrupt request is sent to the ITC if SEIE USI_SIE register is 1 An...

Page 255: ... D3 reserved 0 when being read D2 0 IMTGMOD 2 0 I2C master trigger mode select IMTGMOD 2 0 Trigger mode 0x0 R W 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 reserved Receive ACK NAK Transmit NAK Transmit ACK Receive data Transmit data Stop condition Start condition Note This register is effective only in I2C master mode Configure USI to I2C master mode before this register can be used D 7 5 Reserved D4 IMTG I2...

Page 256: ...whether the triggered operation has completed or not using interrupts USI I2C Master Mode Interrupt Flag Register USI_IMIF Register name Address Bit Name Function Setting Init R W Remarks USI I2C Master Mode Interrupt Flag Register USI_IMIF 0x300462 8 bits D7 6 reserved 0 when being read D5 IMBSY I2C master busy flag 1 Busy 0 Standby 0 R D4 2 IMSTA 2 0 I2C master status IMSTA 2 0 Status 0x0 R 0x7 ...

Page 257: ...ut the receive data buffer being read IMEIF is reset by writing 1 To reset an overrun error clear IMEIF by writing 1 and then read the receive data buffer USI_RD reg ister twice D0 IMIF Operation Completion Flag Bit Indicates whether the triggered operation has completed or not 1 R Completed 0 R Not completed default 1 W Reset to 0 0 W Ignored IMIF is set to 1 when the operation that is specified ...

Page 258: ...ault 0x0 USI I2C Slave Mode Interrupt Enable Register USI_ISIE Register name Address Bit Name Function Setting Init R W Remarks USI I2C Slave Mode Interrupt Enable Register USI_ISIE 0x300471 8 bits D7 2 reserved 0 when being read D1 ISEIE Receive error interrupt enable 1 Enable 0 Disable 0 R W D0 ISIE Operation completion int enable 1 Enable 0 Disable 0 R W Note This register is effective only in ...

Page 259: ... specified operation has finished ISBSY is reset to 0 D 4 2 ISSTA 2 0 I2C Slave Status Bits Indicates the I2C slave status 8 6 I Table 18 2 C Slave Status Bits ISSTA 2 0 Status 0x7 Reserved 0x6 NAK has been received 0x5 ACK has been received 0x4 ACK or NAK has been sent 0x3 End of receive data 0x2 End of transmit data 0x1 Stop condition has been detected 0x0 Start condition has been detected Defau...

Page 260: ...ave address Access address Control byte 9 1 Control Byte Sent from I Figure 18 2 C Master I2C master write data receiving from master SDA line Start condition Write 16 bit address and data write STA Stop condition Access address STP ACK ACK ACK Slv_Addr Addr 15 8 ACK Addr 7 0 ACK DA0 ACK DA1 0x02 Write data 0 9 2 I Figure 18 2 C Master Write Data Receiving from Master The control byte specifies th...

Page 261: ...ter mode or normal mode only slave mode Data transfer timing clock phase and polarity variations is selectable from among 4 types Can generate receive buffer full transmit buffer empty and receive error interrupts Supports DMA transfer I2C master slave mode 7 bit addressing mode 10 bit addressing is possible by software control Supports single master configuration only master mode Supports clock s...

Page 262: ...evice SPI master spi_do O SPI slave spi_do O I2C master Not used I2C slave LCD SPI lcds_do O Data output pin Outputs serial data sent to the LCD driver panel LCD parallel lcdp_wr O Write signal output pin Outputs the write signal to the LCD driver panel USIL_CK UART Not used SPI master spi_ck O Clock output pin Outputs the SPI clock SPI slave spi_ck I Clock input pin Inputs an external clock I2C m...

Page 263: ...ers For more information on the PCLK2 supply refer to the Clock Management Unit CMU Transfer clock When the USIL is configured to a UART SPI master normal mode I2C master LCD SPI or LCD parallel interface the source clock for transfer is supplied by the 8 bit programmable timer T8 Ch 3 Program T8 Ch 3 according to the transfer rate and enable supplying the source clock to the USIL module The USIL ...

Page 264: ...he T8 output clock frequency fSOURCE should be determined according to the i2c_sck frequency T8 output clock SCL controlled by I2C master SCL controlled by I2C slave USIL_CK pin a b c d e f 3 1 I Figure 19 2 C Clock in I2 C Slave Mode Tbf Ti2c_baud_rate Tbc Ti2c_baud_rate_high Tcf Ti2c_baud_rate_low Tce The I2C master occupies the SCL line by driving it to low Tac The I2C master releases the SCL l...

Page 265: ...configured to one of them using the USILMOD 2 0 USIL_GCFG register 4 2 1 Interface Mode Selection Table 19 USILMOD 2 0 Interface mode 0x7 LCD parallel 0x6 LCD SPI 0x5 I2C slave 0x4 I2C master 0x3 SPI slave 0x2 SPI master 0x1 UART 0x0 Software reset Default 0x0 Notes Be sure to perform software reset and set the interface mode before changing other USIL con figurations The LCD parallel UART I2C mas...

Page 266: ... 1 UPREN 1 USTPB 1 s1 D0 D1 D2 D3 D4 D5 D6 s2 s1 D0 D1 D2 D3 D4 D5 D6 p s2 s1 D0 D1 D2 D3 D4 D5 D6 s2 s3 s1 D0 D1 D2 D3 D4 D5 D6 p s2 s3 s1 D0 D1 D2 D3 D4 D5 D6 D7 s2 s1 D0 D1 D2 D3 D4 D5 D6 D7 p s2 s1 D0 D1 D2 D3 D4 D5 D6 D7 s2 s3 s1 D0 D1 D2 D3 D4 D5 D6 D7 p s2 s3 s1 start bit s2 s3 stop bit p parity bit 4 4 1 Transfer Data Format in UART Mode LSB first Figure 19 Settings for SPI Mode 19 4 5 Whe...

Page 267: ...I 19 4 6 2 C Mode The I2C mode does not need to set data format and other conditions The data length in I2C mode is fixed at 8 bits Settings for LCD SPI Mode 19 4 7 When the USIL is used in LCD SPI mode configure the SPI clock polarity phase and the data format SPI clock polarity and phase settings Use LSCPOL USIL_LSCFG register to select the SPI clock polarity Setting LSCPOL to 1 treats the SPI c...

Page 268: ...DI pin is used as the A0 signal output pin The USIL_DI pin goes high when LSCMD is set to 1 and it goes low when LSCMD is set to 0 LSCMDEN 0 LSCMDEN 1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 CMD TD 7 0 4 7 2 8 bit Data Format Figure 19 LSCMDEN 0 LSCMDEN 1 RGB mode BGR mode D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 TD 7 0 R5 R4 R3 R2 R1 ...

Page 269: ...TD 7 2 TD 7 2 CMD 18 bit Format 3 4 7 4 18 bit Data Format Figure 19 LSCMDEN 0 LSCMDEN 1 RGB mode BGR mode D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 TD 7 0 R5 R4 R3 R2 R1 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B5 R6 B6 R7 B7 B4 B3 B2 B1 R0 B0 G5 G6 G8 G7 G7 G4 G3 G2 G1 G0 R5 R4 B7 B6 R7 R6 R3 R2 R1 B0 R...

Page 270: ...ta in the shift register is then output in sequence Following output of the eighth data bit the parity bit if parity is enabled and the stop bit are output The transmitter circuit includes two status flags UTDIF USIL_UIF register and UTBSY USIL_UIF register The UTDIF flag indicates the transmit data buffer status This flag is set to 1 indicating that the transmit data buffer becomes empty when dat...

Page 271: ... DMA The receive data buffer size is 1 byte therefore the received data must be read before the subsequent data reception has completed Furthermore URDIF must be reset by writing 1 If the next reception is completed when URDIF is 1 and the receive data buffer USIL_RD register is not read an overrun error occurs at the time stop bit has been received The URBSY flag indicates the shift register stat...

Page 272: ...eception This starts the SPI clock output from the USIL_CK pin In SPI slave mode the module waits until the clock is input from the USIL_CK pin There is no need to write to the transmit data buffer if no transmission is required The receiving operation is started by the clock input from the master device If data is transmitted simultaneously write transmit data to the transmit data buffer be fore ...

Page 273: ...hen the slave select signal is inactive high it goes 0 when the slave select signal is active low If a slave select output is required in SPI master mode use a general purpose I O port and control its output with software Data Transfer in I 19 5 3 2 C Mode Control method in I2C master mode Data transfer in I2C master mode is controlled using IMTGMOD 2 0 USIL_IMTG register and IMTG USIL_ IMTG regis...

Page 274: ...he data transmission procedure in I2C master mode START END Generate start condition Generate stop condition Send slave address and transfer direction bit ACK received yes ACK received yes no Finished yes Send data Error handling no no 5 3 1 I Figure 19 2 C Master Data Transmission Flow Chart 0x0 Address 0x6 0x2 0x2 Transfer data 1 A6 A5 D7 D6 D5 D4 D3 D2 D1 D0 A4 A3 A2 A1 A0 R W 0 ACK USIL_CK pin...

Page 275: ...I2C bus is busy from this point on Note Other operations cannot be started before a start condition is generated 2 Sending slave address and transfer direction bit After a start condition has been generated send the address of the slave device to be communicated and a transfer direction bit I2C slave addresses are either 7 bit or 10 bit This module uses an 8 bit transfer data buffer to send the sl...

Page 276: ...eiving a NAK sets it to 0x6 Check IMSTA 2 0 after confirming IMBSY or using an interrupt When an ACK has been received perform data transmission When a NAK has been received perform an error handling 3 Data transmission The data transmission procedure is the same as that of the slave address transmission 1 Write an 8 bit transmit data to the transmit data buffer TD 7 0 2 Set IMTGMOD 2 0 to 0x2 and...

Page 277: ...e described in Step 1 Slave address transmission is subsequently possible with the I2C bus remaining in the busy state SDA USIL_DI SCL USIL_CK Repeated start condition 5 3 7 Repeated Start Condition Figure 19 Data reception in I2C master mode The following describes the data receiving procedure in I2C master mode START END Generate start condition Generate stop condition Send slave address and tra...

Page 278: ...MTGMOD 2 0 to 0x3 and write 1 to IMTG This trigger starts outputting 8 clocks from the USIL_CK pin The USIL_DO pin status is sampled in sync with the clock and loaded to the shift register The received data is loaded to the receive data buffer RD 7 0 USIL_RD register once the 8 bit data has been received in the shift register Writing 1 to IMTG sets IMBSY to 1 When the received data is loaded to th...

Page 279: ...is controlled using ISTGMOD 2 0 USIL_ISTG register and ISTG USIL_ ISTG register Select an I2C slave operation using ISTGMOD 2 0 and write 1 to ISTG as the trigger The I2C controller controls the I2C bus to generate the specified operating status 5 3 3 Trigger List in I Table 19 2 C Slave Mode ISTGMOD 2 0 Trigger 0x7 Reserved 0x6 ACK NAK reception 0x5 NAK transmission 0x4 ACK transmission 0x3 Data ...

Page 280: ...t condition Data transmission NAK 0x6 0x6 0x2 0x3 Transfer data n D7 D6 D5 D4 D3 D2 D1 D0 ACK USIL_CK pin output USIL_CK pin input USIL_DI pin output USIL_DI pin input ISTGMOD 2 0 ISTG write ISBSY ISSTA 2 0 TD 7 0 ISIF Stop detection interrupt End of transmission interrupt Receive NAK interrupt Receive ACK interrupt 1 1 1 1 0x2 0x6 0x1 0x5 2 2 2 2 2 Data transmission Stop condition 1 When the USIL...

Page 281: ... again to obtain the remaining address bits Check whether the received address is matched to this I2C slave address or not When they are matched send back an ACK to the I2C master by setting ISTGMOD 2 0 to 0x4 and write 1 to ISTG ISBSY is set to 1 while an ACK is being sent and it reverts to 0 when the transmission has completed An interrupt request can be generated at this point When an ACK has b...

Page 282: ...4 0x4 0x3 0x3 D7 D6 D5 D4 D3 D2 D1 D0 ACK USIL_CK pin output USIL_CK pin input USIL_DI pin output USIL_DI pin input ISTGMOD 2 0 ISTG write ISBSY ISSTA 2 0 RD 7 0 ISIF Stop detection interrupt 1 1 1 1 End of reception interrupt Transfer NAK interrupt Transfer ACK interrupt Received data n 1 Received data n 2 2 2 2 0x3 0x4 0x1 0x4 2 Data reception Stop condition 1 When the USIL_CK input is detected ...

Page 283: ...k stretch function While data is being sent received this I2C slave generates a clock stretch status by pulling down the SCL line to low to make a wait request to the master device after an ACK is sent received until the following data transfer is started Data Transmission in LCD SPI Mode 19 5 4 The LCD SPI mode supports only data transmission To start data transmission in LCD SPI mode write the t...

Page 284: ... USIL_LPIF register The LPWRIF flag indicates the write buffer status This flag is set to 1 indicating that the write buffer becomes empty when data written to the buffer is output via the LCD_D 7 0 pins LPWRIF is an interrupt flag An in terrupt or DMA request can be generated when this flag is set to 1 see Section 19 7 Write subsequent data to the write buffer to start the following transmission ...

Page 285: ... or at standby Note Once a triggered read cycle is completed data is stored in the read buffer and LPRDIF switches to high After that read data from the read buffer before issuing the next read trigger Otherwise a subsequent read operation will not be started PCLK2 T8 output clock LPRD LPBSY Read trigger LPRDIF USIL_CS lcdp_cs USIL_CK lcdp_rd USIL_DI lcdp_a0 LCD_D 7 0 RD 7 0 Interrupt data 1 data ...

Page 286: ...igure 19 START 1 1 END yes no LPBSY 1 no LPRD 1 yes yes LPRD 1 no Initialize external modules PSC T8 Software reset USILMOD 2 0 0x0 Set LCD parallel mode USILMOD 2 0 0x7 Clear LCD parallel mode flags LPRDIF LPWRIF 1 Clear read buffer full flag LPRDIF 1 Enable successive read LPSRDEN 1 Disable successive read LPSRDEN 0 Trigger reading LPRD 1 Set LCD parallel mode registers Read data from USIL RD re...

Page 287: ...gister twice The procedure that writes 1 to SEIF and reads USIL_RD register twice can be reversed I2C master slave mode An overrun error occurs when a transmit or receive trigger is issued after two byte data has been received the first byte data exists in the receive data buffer and the second byte data exists in the shift register without the receive data buffer being read When an overrun error ...

Page 288: ...DIE USIL_UIE register to 1 If URDIE is set to 0 default interrupt requests for this cause will not be sent to the ITC If a received data is loaded into the receive data buffer the USIL module sets URDIF USIL_UIF register to 1 If receive buffer full interrupts are enabled URDIE 1 an interrupt request is sent simultaneously to the ITC An interrupt occurs if other interrupt conditions are met You can...

Page 289: ...ve error has occurred or not Receive error interrupt To use this interrupt set SEIE USIL_SIE register to 1 If SEIE is set to 0 default interrupt requests for this cause will not be sent to the ITC The USIL module sets SEIF USIL_SIF register to 1 if an overrun error is detected when receiving data If receive error interrupts are enabled SEIE 1 an interrupt request is sent simultaneously to the ITC ...

Page 290: ...that initiated by a software trigger has completed the USIL module sets ISIF USIL_ISIF register to 1 If operation completion interrupts are enabled ISIE 1 an interrupt request is sent simultane ously to the ITC An interrupt occurs if other interrupt conditions are met You can inspect the ISSTA 2 0 USIL_ISIF register in the interrupt handler routine to determine the I2C operation status that causes...

Page 291: ...bled LPWRIE 1 an interrupt request is sent simultaneously to the ITC An interrupt occurs if other inter rupt conditions are met You can inspect the LPWRIF flag in the interrupt handler routine to determine whether the USIL LCD parallel mode interrupt is attributable to a write buffer empty If LPWRIF is 1 the next data can be written to the write buffer by the interrupt handler routine Read buffer ...

Page 292: ...CD SPI Mode Configuration Register Set LCD SPI transfer conditions 0x300681 USIL_LSIE USIL LCD SPI Mode Interrupt Enable Register Enable disable LCD SPI interrupts 0x300682 USIL_LSIF USIL LCD SPI Mode Interrupt Flag Register Indicate LCD SPI interrupt cause status 0x30068f USIL_LSDCFG USIL LCD SPI Mode Data Configuration Register Select display data format 0x300690 USIL_LPCFG USIL LCD Parallel I F...

Page 293: ...mode the data written to this register is output via the LCD_D 7 0 pins A transmit write buffer empty interrupt can be generated when data written to this register has been transferred to the shift register or output from the LCD_D 7 0 pins The subsequent transmit data can then be written even while data is being sent USIL Receive Data Buffer Register USIL_RD Register name Address Bit Name Functio...

Page 294: ...parity checking is performed and whether a parity bit is added to transmit data Setting UPREN to 1 parity checks the received data A parity bit is automati cally added to the transmit data If UPREN is set to 0 no parity bit is checked or added USIL UART Mode Interrupt Enable Register USIL_UIE Register name Address Bit Name Function Setting Init R W Remarks USIL UART Mode Interrupt Enable Register ...

Page 295: ...e default URBSY is set to 1 when the first start bit is detected when data reception begins and is reset to 0 when the data received in the shift register is loaded into the receive data buffer Inspect URBSY to determine whether the receiving circuit is operating or at standby D5 UTBSY Transmit Busy Flag Bit Indicates the USIL status in UART mode 1 R Busy 0 R Idle default UTBSY switches to 1 when ...

Page 296: ...uffer Empty Flag Bit Indicates the transmit data buffer status 1 R Empty 0 R Data exists default 1 W Reset to 0 0 W Ignored UTDIF is set to 1 when the transmit data written to the transmit data buffer is transferred to the shift register when transmission starts indicating that the next transmit data can be written to At the same time a transmit buffer empty interrupt request is sent to the ITC if...

Page 297: ...ividing the T8 output by 2 Setting SFSTMOD to 1 places the USIL into fast mode and the USIL uses PCLK2 supplied from the CMU directly as the transfer clock The fast mode does not use the T8 The SPI slave mode uses the T8 output clock for generating the sampling clock USIL SPI Master Slave Mode Interrupt Enable Register USIL_SIE Register name Address Bit Name Function Setting Init R W Remarks USIL ...

Page 298: ...D3 SSIF Transfer Busy Flag Bit Master Mode ss Signal Low Flag Bit Slave Mode Master mode Indicates the SPI transfer status 1 R Operating 0 R Standby default SSIF is set to 1 when the SPI starts data transfer in master mode and is maintained at 1 while transfer is underway It is cleared to 0 once the transfer is completed Slave mode Indicates the slave select USIL_CS signal status 1 R High level th...

Page 299: ...it data can be written to At the same time a transmit buffer empty interrupt request is sent to the ITC if STDIE USIL_SIE register is 1 STDIF is reset by writing 1 USIL I2C Master Mode Trigger Register USIL_IMTG Register name Address Bit Name Function Setting Init R W Remarks USIL I2C Master Mode Trigger Register USIL_IMTG 0x300660 8 bits D7 5 reserved 0 when being read D4 IMTG I2C master operatio...

Page 300: ...fault Set this bit to 1 to process overrun errors using interrupts D0 IMIE Operation Completion Interrupt Enable Bit Enables interrupt requests to the ITC when the triggered operation has completed 1 R W Enabled 0 R W Disabled default Set this bit to 1 to confirm whether the triggered operation has completed or not using interrupts USIL I2C Master Mode Interrupt Flag Register USIL_IMIF Register na...

Page 301: ...n error occurs when a transmit or receive trigger is issued after two byte data has been re ceived the first byte data exists in the receive data buffer and the second byte data exists in the shift register without the receive data buffer being read IMEIF is reset by writing 1 To reset an overrun error clear IMEIF by writing 1 and then read the receive data buffer USIL_RD register twice D0 IMIF Op...

Page 302: ...etection 0x2 Data transmission 0x1 Reserved 0x0 Wait for start condition Default 0x0 USIL I2C Slave Mode Interrupt Enable Register USIL_ISIE Register name Address Bit Name Function Setting Init R W Remarks USIL I2C Slave Mode Interrupt Enable Register USIL_ISIE 0x300671 8 bits D7 2 reserved 0 when being read D1 ISEIE Receive error interrupt enable 1 Enable 0 Disable 0 R W D0 ISIE Operation complet...

Page 303: ...ing When the specified operation has finished ISBSY is reset to 0 D 4 2 ISSTA 2 0 I2C Slave Status Bits Indicates the I2C slave status 8 6 I Table 19 2 C Slave Status Bits ISSTA 2 0 Status 0x7 Reserved 0x6 NAK has been received 0x5 ACK has been received 0x4 ACK or NAK has been sent 0x3 End of receive data 0x2 End of transmit data 0x1 Stop condition has been detected 0x0 Start condition has been de...

Page 304: ...isable 0 R W Note This register is effective only in LCD SPI mode Configure USIL to LCD SPI mode before setting this register D 7 4 Reserved D3 LSCPHA Clock Phase Select Bit Selects the LCD SPI clock phase 1 R W Phase 1 0 R W Phase 0 default Set the data transfer timing together with LSCPOL See Figure 19 8 2 D2 LSCPOL Clock Polarity Select Bit Selects the LCD SPI clock polarity 1 R W Active low 0 ...

Page 305: ...s USIL LCD SPI Mode Interrupt Flag Register USIL_LSIF Register name Address Bit Name Function Setting Init R W Remarks USIL LCD SPI Mode Interrupt Flag Register USIL_LSIF 0x300682 8 bits D7 2 reserved X when being read D1 LSBSY Transfer busy flag 1 Busy 0 Idle 0 R D0 LSTDIF Transmit buffer empty flag 1 Empty 0 Not empty 0 R W Reset by writing 1 Note This register is effective only in LCD SPI mode ...

Page 306: ...PI mode before setting this register D 7 4 Reserved D 3 2 LS18DFM 1 0 LCD SPI 18 bit Data Format Select bits Selects a data format in 18 bit mode See Figure 19 8 6 8 7 LCD SPI 18 bit Data Format Table 19 LS18DFM 1 0 Data format 0x3 Format 3 0x2 Format 2 0x1 Format 1 0x0 Format 0 Default 0x0 D 1 0 LSDMOD 1 0 LCD SPI Data Mode Select Bit Selects the LCD SPI data mode 8 8 LCD SPI Data Mode Table 19 L...

Page 307: ... 7 2 CMD 18 bit Format 2 LSCMDEN 0 LSCMDEN 1 RGB mode BGR mode D7 D6 D5 D4 D3 D2 D7 D6 D5 D4 D3 D2 D7 D6 D5 D4 D3 D2 D7 D6 D5 D4 D3 D2 D7 D6 D5 D4 D3 D2 D7 D6 D5 D4 D3 D2 TD 7 2 R5 R4 R3 R2 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B5 B4 B3 B2 B1 G5 G4 G3 G2 G1 G0 R5 R4 R3 R2 R1 R1 B0 B0 R0 TD 7 2 TD 7 2 CMD 18 bit Format 3 8 6 18 bit Data Format Figure 19 LSCMDEN 0 LSCMDEN 1 RGB mode BGR mode D7 D6 D5 ...

Page 308: ...ue before writing to LPRD The command bit value set is output from the USIL_DI pin immediately after it is written to the register Then it loads the LCD_ D 7 0 pin status to the read receive data buffer RD 7 0 USIL_RD register LPRD retains 1 until the read data is loaded to the read buffer USIL LCD Parallel I F Mode Interrupt Enable Register USIL_LPIE Register name Address Bit Name Function Settin...

Page 309: ...a received is loaded to the read buffer when receiving is completed indi cating that the data can be read At the same time a read buffer full interrupt request is sent to the ITC if LPRDIE USIL_LPIE register is 1 LPRDIF is reset by writing 1 D0 LPWRIF Write Buffer Empty Flag Bit Indicates the write transmit data buffer status 1 R Empty 0 R Data exists default 1 W Reset to 0 0 W Ignored LPWRIF is s...

Page 310: ...e of the LCD parallel interface 8 10 Setup Cycle Settings Table 19 LPST 1 0 Number of setup cycles 0x3 4 cycles 0x2 3 cycles 0x1 2 cycles 0x0 1 cycle Default 0x0 D 3 0 LPWT 3 0 Wait Cycle Bits Configures the wait cycle of the LCD parallel interface 8 11 Wait Cycle Settings Table 19 LPWT 3 0 Number of wait cycles 0xf 15 cycles 0xe 14 cycles 0x1 1 cycle 0x0 0 cycles Default 0x0 T8 Ch 3 output clock ...

Page 311: ...TA Stop condition Access address STP ACK ACK ACK Slv_Addr Addr 15 8 ACK Addr 7 0 ACK DA0 ACK DA1 0x02 Write data 0 9 2 I Figure 19 2 C Master Write Data Receiving from Master The control byte specifies the access address size and writing operations The received data that follow the control byte should be used as the address and the data to be written according to the access address size I2C master...

Page 312: ...y desired baud rate can be set by selecting the baud rate timer or using external clock in put asynchronous mode only Up to 8 Mbps transfer in clock synchronized mode or up to 1 Mbps transfer in asynchronous mode are possible 4 byte receive buffer FIFO and 2 byte transmit buffer FIFO are built in allowing for successive receive and transmit operations Data transfers using DMAC are possible Three t...

Page 313: ...elect bits to use the general purpose I O port pins as FSIO pins For detailed information on pin function switching see the I O Ports GPIO chapter FSIO Operating Clock 20 3 FSIO Ch 0 and Ch 1 use PCLK1 and PCLK2 as the operating clock respectively Therefore PCLK1 and or PCLK2 must be supplied from the CMU before starting the FSIO including setting the control registers For more informa tion on the...

Page 314: ...andard Mode and Advanced Mode Table 20 Function Standard mode Advanced mode SRDY mask control Disabled Enabled Number of received data in the buffer to generate a receive buffer full interrupt One One to four can be specified To configure the serial interface in advanced mode set SIOADV FSIO_ADVx register to 1 The control bits for the extended functions are enabled to write after this setting At i...

Page 315: ...d data The initial value for the reload data register is determined by the expressions shown below Note that the expres sion depends on the transfer mode Clock synchronized master mode fPCLK BRTRD 1 2 bps BRTRD Reload data register setup value of the baud rate timer fPCLK Baud rate timer operating clock PCLK1 or PCLK2 frequency bps Transfer rate bits second Asynchronous mode fPCLK DIVMD BRTRD 1 2 ...

Page 316: ...mple of how the input output pins are connected in the clock synchronized mode Data input Data output Clock input Ready output SINx SOUTx SCLKx SRDYx SINx SOUTx SCLKx SRDYx External serial device 1 Master mode 2 Slave mode S1C33L26 Data input Data output Clock output Ready input External serial device S1C33L26 6 1 1 Example of Connection in Clock Synchronized Mode Figure 20 Clock synchronized tran...

Page 317: ... data register is not read This serial interface can generate a receive buffer full interrupt when the specified number of data are received in the receive FIFO Use FIFOINT 1 0 FSIO_IRDAx register to set this number of data Writing 0 3 to FIFOINT 1 0 sets the number of data to 1 4 The default setting at initial reset is 0 so that a receive buffer full interrupt will generate when one data is recei...

Page 318: ...ister are shifted out Be aware that there is a half SCLKx cycle interval between setting TEND to 0 and latching the last bit by the receiver When all the data in the transmit data buffer are transferred a cause of the transmit data empty interrupt oc curs Since an interrupt can be generated by setting the interrupt control bits the subsequent transmit data can be written using an interrupt process...

Page 319: ... data register is trans ferred to the shift register synchronously with the first falling edge of the clock At the same time the LSB of the data transferred to the shift register is output from the SOUTx pin If the transmit data buffer becomes empty at this point a transmit buffer empty interrupt request occurs The SRDYx signal is returned to a high level at this point 3 The data in the shift regi...

Page 320: ... When RXDNUM 1 0 is 0 the buffer contains 0 or 1 data When RXDNUM 1 0 is 1 3 the buffer contains 2 4 data Furthermore RDBF FSIO_STATUSx register is provided for indicating whether the receive data buffer is emp ty or not This flag is set to 1 when the receive data buffer contains one or more received data and is reset to 0 when the receive data buffer becomes empty by reading all the received data...

Page 321: ...setting the SRDYx signal to a low level ready to receive the slave waits for clock input from the master 2 The master device outputs each bit of data synchronously with the falling edges of the clock The LSB is output first 3 This serial interface takes the SINx input into the shift register at the rising edges of the clock that is in put from SCLKx The data in the shift register is sequentially s...

Page 322: ... data buffer is full the SRDYx signal is forcibly fixed at high in order to suspend data transfer from the master device until the data in the buffer is read To use this function set SRDYCTL FSIO_IRDAx register to 1 This function is effective in clock synchronized master mode as well In this case the SRDYx signal low from the slave device is ignored when the receive data buffer is full and the ser...

Page 323: ...s are performed simultaneously is also possible Figure 20 7 1 1 shows an example of how input output pins are connected for transfers in the asynchronous mode Data input Data output External clock SINx SOUTx SCLKx SINx SOUTx External serial device 1 When external clock is used 2 When internal clock is used S1C33L26 Data input Data output External serial device S1C33L26 7 1 1 Example of Connection ...

Page 324: ...ust be made before a transfer mode is set Setting the transfer mode Use SMD 1 0 FSIO_CTLx register to set the transfer mode of the serial interface as described earlier When using the serial interface in the 8 bit asynchronous mode set SMD 1 0 to 0x3 when using the serial interface in the 7 bit asynchronous mode set SMD 1 0 to 0x2 Setting the input clock In the asynchronous mode the operating cloc...

Page 325: ...bsequent samplings and returns to the start bit detection phase in this case no error occurs When the SINx input signal is low at the start bit sampling subsequent bit data is sampled in 16 SIO_CLK cycles 8 SIO_CLK cycles when 1 8 division is selected For transmitting SIO_CLK Sampling clock SOUTx Start bit D0 1 8 16 16 SIO_CLK 7 2 2 Sampling Clock for Asynchronous Transmit Operation when 1 16 divi...

Page 326: ...ode bit 7 MSB in each register is ignored The data written to TXD 7 0 enters the transmit data buffer and waits for transmission The transmit data buffer is a 2 byte FIFO and up to two data can be written to it successively if empty Older data will be transmitted first and cleared after transmission The next transmit data can be written to the trans mit data register even during data transmission ...

Page 327: ...e receive enable bit RXEN FSIO_CTLx register for receive control When receiving enabled by writing 1 to this bit clock input to the shift register is enabled ready for input meaning that it is ready to receive data Receive operations are disabled and the receive data buffer FIFO is cleared initialized by writing 0 to RXEN Note Do not set RXEN to 0 during a receive operation 2 Receive procedure Thi...

Page 328: ...t register is transferred to the receive data register enabling the data to be read out The parity is checked when data is transferred to the receive data register if EPR 1 Note The receive operation is terminated when the first stop bit is sampled even if the stop bit is config ured with two bits 3 Receive errors Three types of receive errors can be detected when receiving data in the asynchronou...

Page 329: ...occurs the receive operation is continued OER is reset to 0 by writing 0 4 Terminating receive operation When a data receive operation is completed write 0 to the receive enable bit RXEN to disable receive opera tions This operation clears initializes the receive data buffer FIFO therefore make sure that there is no data that has not been read in the receive data buffer before setting RXEN to 0 Ir...

Page 330: ...ure to set the transfer mode in 3 and the following items after selecting the IrDA interface function in 2 Selecting the IrDA interface function To use the IrDA interface function select it using IRMD 1 0 FSIO_IRDAx register and then set the 8 bit or 7 bit asynchronous mode as the transfer mode 8 2 1 Setting of IrDA Interface Table 20 IRMD 1 0 Interface mode 0x3 Setting prohibited reserved 0x2 IrD...

Page 331: ...face so refer to Sec tion 20 7 3 Control and Operation of Asynchronous Transfer The following describes the data modulation and demodulation performed using the RZI modulator circuit When transmitting During data transmission the pulse width of the serial interface output signal is set to 3 16 before the signal is output from the SOUTx pin SIO_CLK RZI modulator input I F output RZI modulator outpu...

Page 332: ...terrupt request is sent simultaneously to the ITC An interrupt oc curs if other interrupt conditions are met You can inspect the TDBE_IF flag in the interrupt handler routine to determine whether the FSIO interrupt is attributable to a transmit buffer empty If TDBE_IF is 1 the next trans mit data can be written to the transmit data buffer by the interrupt handler routine TDBE_IF is cleared by writ...

Page 333: ...et transfer mode and control data transfer 0x300704 FSIO_IRDA0 FSIO Ch 0 IrDA Register Set IrDA conditions 0x300705 FSIO_BRTRUN0 FSIO Ch 0 Baud rate Timer Control Register Control baud rate timer 0x300706 FSIO_BRTRDL0 FSIO Ch 0 Baud rate Timer Reload Data L Register Baud rate timer initial count data 0x300707 FSIO_BRTRDH0 FSIO Ch 0 Baud rate Timer Reload Data H Register 0x300708 FSIO_BRTCDL0 FSIO ...

Page 334: ...data buffer The receive data buffer is a 4 byte FIFO and can re ceive data until it becomes full unless received data is not read out When the buffer is full and also the shift register contains received data an overrun error will occur if the received data is not read until the next data receiving begins The receive buffer status flag RDBF FSIO_STATUSx register is provided to indicate that it is ...

Page 335: ...ansmit shift register are shifted out Be aware that there is a half SCLKx cycle interval be tween setting TEND to 0 and latching the last bit by the receiver D4 FER Framing Error Flag Bit Indicates whether a framing error has occurred 1 R An error occurred 0 R No error occurred default 1 W Has no effect 0 W Reset to 0 FER is an error flag indicating whether a framing error has occurred or not When...

Page 336: ...etting Init R W Remarks FSIO Ch x Control Register FSIO_CTLx 0x300703 0x300713 8 bits D7 TXEN Transmit enable 1 Enable 0 Disable 0 R W D6 RXEN Receive enable 1 Enable 0 Disable 0 R W D5 EPR Parity enable 1 With parity 0 No parity 0 R W Valid only in asynchronous mode D4 PMD Parity mode select 1 Odd 0 Even 0 R W D3 STPB Stop bit select 1 2 bits 0 1 bit 0 R W D2 SSCK Input clock select 1 SCLK 0 Inte...

Page 337: ...nsfer 1 R W SCLKx external clock 0 R W Internal clock default During operation in asynchronous mode this bit is used to select the clock source between an internal clock output from the baud rate timer and an external clock input from the SCLKx pin An external clock is selected by writing 1 to this bit and an internal clock is selected by writing 0 D 1 0 SMD 1 0 Transfer Mode Select Bits Sets the ...

Page 338: ...eive Buffer Full Interrupt Timing Bits Sets the number of data in the receive data buffer to generate a receive buffer full interrupt 10 4 Number of Receive Data Buffer Table 20 FIFOINT 1 0 Receive level 0x3 4 0x2 3 0x1 2 0x0 1 Default 0x0 Writing 0 3 to FIFOINT 1 0 sets the number of data to 1 4 When the number of data in the receive data buffer reaches the number specified here the receive buffe...

Page 339: ...Address Bit Name Function Setting Init R W Remarks FSIO Ch x Baud rate Timer Control Register FSIO_ BRTRUNx 0x300705 0x300715 8 bits D7 1 reserved 0 when being read D0 BRTRUN Baud rate timer run stop control 1 Run 0 Stop 0 R W D 7 1 Reserved D0 BRTRUN Baud rate Timer Run Stop Control Bit Controls the baud rate timer s RUN STOP states 1 R W Run 0 R W Stop default The baud rate timer loads the reloa...

Page 340: ... FSIO_INTFx Register name Address Bit Name Function Setting Init R W Remarks FSIO Ch x Interrupt Flag Register FSIO_INTFx 0x30070a 0x30071a 8 bits D7 2 reserved 0 when being read D1 TDBE_IF Transmit data buffer empty int flag 1 Cause of interrupt occurred 0 Cause of interrupt not occurred 0 R W Reset by writing 0 D0 RDBF_IF Receive data buffer full int flag 0 R W D 7 2 Reserved D1 TDBE_IF Transmit...

Page 341: ...en received data is loaded to the receive data buffer 1 R W Enabled 0 R W Disabled default Set this bit to 1 to read received data using interrupts FSIO Ch x STD ADV Mode Select Registers FSIO_ADVx Register name Address Bit Name Function Setting Init R W Remarks FSIO Ch x STD ADV Mode Select Register FSIO_ADVx 0x30070f 0x30071f 8 bits D7 1 reserved Writing 1 not al lowed D0 SIOADV Standard advance...

Page 342: ... is software configurable Data shift direction MSB first LSB first is software selectable Supports I2S mode left justified mode and right justified mode Figure 21 1 1 shows the configuration of the I2S module I2S_MCLK I2S_SCLK I2S_WS I2S_SDO PCLK1 from CMU FIFO control Internal bus ITC DMAC I2S Bus I F and control registers Interrupt control Transmit FIFO 16 bits 2 ch 4 Clock control I2S interface...

Page 343: ...MA conditions see Section 21 6 The following describes the settings Note Always make sure the I2S module is not started I2SSTART I2S_START register 0 before these settings are made A change of settings during operation may cause a malfunction Setting the output pins Configure the port function select bits to enable the I2S output functions For details of pin functions and how to switch over see th...

Page 344: ...LK Hz BCLKDIV 1 2 fI2S_SCLK I2S bit clock frequency Hz fPCLK1 PCLK1 clock frequency Hz BCLKDIV BCLKDIV 7 0 set value 0x0 0xff Sample clock I2S_WS period The I2S generates the sample clock word select clock to be output from the I2S_WS pin by counting the bit clock configured with BCLKDIV 7 0 Specify the half cycle a high or low level period of the I2S_ WS clock with the number of bit clock cycles ...

Page 345: ... word clock mode The I2S_WS signal represents the current output channel L or R with its level low or high Use WCLKMD I2S_CTL register to select the relationship between the signal level and the L R channel I2S_WS WCLKMD 0 default L channel R channel I2S_WS WCLKMD 1 L channel R channel 4 3 Word Clock Mode Figure 21 I2S_SCLK bit clock polarity Use BCLKPOL I2S_CTL register to select the bit clock po...

Page 346: ...id data size are set to the sign bit value D15 of the valid data I2S_WS I2S_SCLK I2S_SDO L channel R channel 0 D15 D2 D1 D0 D14 0 D15 D14 MSB first right justified mode number of bit clock cycles 18 DTSIGN 0 default I2S_WS I2S_SCLK I2S_SDO L channel R channel D15 D2 D1 D0 D14 D15 D14 DTSIGN 1 4 6 Unsigned and Signed Format Figure 21 This setting is effective only in right justified mode Set DTSIGN...

Page 347: ...6 18 17 1 2 3 4 5 I2S_WS I2S_SCLK Bit clock cycle count by setting WSCLKCYC 4 0 I2S_SDO L channel R channel MSB first number of bit clock cycles 18 D15 D2 D1 D0 D0 D14 D13 D15 D14 D13 0 or D15 0 or D15 4 9 Data Output Timing 3 Right Justified Mode Figure 21 Note When using right justified mode the number of bit clock cycles sample clock period must be equal to or greater than Data bit size 2 Data ...

Page 348: ...ereo data has been read out from the FIFO In this case write the next four stereo data 16 bits 2 channels L R 4 to the FIFO in the interrupt handler When one empty interrupts are enabled the I2S module generates an interrupt after one stereo data has been read out from the FIFO In this case write the next one stereo data 16 bits 2 channels L R 1 to the FIFO in the interrupt handler This one empty ...

Page 349: ...FO with more than one group of data it may overwrite the remaining data in the FIFO Therefore the FIFO should always be filled with one group of data in the one empty interrupt handler I2SSTART I2SBUSY FIFO I2S_WS pin FIFOSTAT 2 0 I2SFIFOFF I2SFIFOEF Interrupt 1 2 3 4 2 2 4 3 1 3 0 1L 1R 2L 2R 3L 3R 4L 4R 5L 5R 6L 6R Start 2 3 4 3 4 5 6 4 5 6 3 4 5 6 6 Empty Empty Half empty interrupt Write 4 L R ...

Page 350: ...C and DMAC Therefore DMA transfer can be performed without gener ating any I2S interrupt Single channel DMA mode If L channel and R channel audio data are sequentially stored in one memory area use single channel DMA mode Use 32 bit data transfer to write both L low order 16 bits and R high order 16 bits data to the FIFO fixed address 0x301410 for each DMA request Note that 16 bit and 8 bit data t...

Page 351: ... to 0 I2SSTART I2SBUSY I2S_WS pin I2S_SCLK pin I2S_SDO pin In left or right justified mode 18 bit clock cycles Valid data 1st L channel Dummy 1st R channel 2nd L channel Last R channel Last L channel 18 bit clock cycles 18 bit clock cycles 18 bit clock cycles I2SSTART I2SBUSY I2S_WS pin I2S_SCLK pin I2S_SDO pin In I2S mode Valid data 1st L channel Dummy 1st R channel 2nd L channel Last R channel L...

Page 352: ...errupt requests for this cause will not be sent to the ITC When a free space for two stereo data becomes available in the FIFO the I2S module sets HEIF I2S_INT regis ter to 1 If half empty interrupts are enabled HEIE 1 an interrupt request is sent simultaneously to the ITC An interrupt occurs if other interrupt conditions are met If HEIF is 1 the application program should fill the FIFO with two s...

Page 353: ...ations use DMAC Ch 0 and Ch 1 In this case perform 16 bit data transfer to write L channel data to the FIFO fixed address 0x301410 using DMAC Ch 0 and to write R channel data to the FIFO fixed address 0x301412 using DMAC Ch 1 The I2S one empty DMA request is sent to DMAC Ch 0 and Ch 1 simultaneously However DMAC Ch 0 starts a DMA transfer first as it priority over Ch 1 Therefore DMAC Ch 0 must be ...

Page 354: ...S module D 15 9 Reserved D8 DTSIGN I2S Signed Unsigned Data Format Select Bit Selects the data format in right justified mode 1 R W Signed 0 R W Unsigned default Setting DTSIGN to 0 default selects the unsigned format The high order bits that exceed the valid data size are set to 0 Setting 1 selects the signed format The high order bits that exceed the valid data size are set to the sign bit value...

Page 355: ...LSB first 0 R W MSB first default I2S_WS I2S_SCLK I2S_SDO DTFORM 0 default I2S_WS I2S_SCLK I2S_SDO DTFORM 1 D0 D15 D2 D1 D0 D15 D14 D2 D1 D14 D0 D15 D0 D13 D14 D15 D0 D1 D13 D14 D1 D15 7 4 Output Data Format Example in I Figure 21 2 S Mode D4 I2SOUTEN I2S Output Enable Bit Enables disables output of the I2S signals 1 R W Enable on 0 R W Disable off default When I2SOUTEN 0 the I2S_MCLK pin is maint...

Page 356: ...dge 1 2 3 4 5 16 18 17 1 2 3 4 5 I2S_WS I2S_SCLK Bit clock cycle count by setting WSCLKCYC 4 0 I2S_SDO L channel R channel MSB first number of bit clock cycles 18 D15 D2 D1 D0 D0 D14 D13 D15 D14 D13 0 or D15 0 or D15 7 7 Data Output Timing 3 Right Justified Mode Figure 21 Note When using right justified mode the number of bit clock cycles sample clock period must be equal to or greater than Data b...

Page 357: ...o Clock Division Ratio Register I2S_DV_AUDIO_CLK Register name Address Bit Name Function Setting Init R W Remarks I2S Audio Clock Division Ratio Register I2S_DV_AUDIO _CLK 0x301406 16 bits D15 13 reserved 0 when being read D12 8 WSCLKCYC 4 0 I2S WS clock cycle setup WSCLKCYC 4 0 Clock period 0x0 R W Other 0x10 0xf 0xe 0xd 0xc 0xb 0xa 0x9 0x8 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 reserved 32 clocks 31 cl...

Page 358: ... Table 21 7 5 Note The value to be set to the WSCLKCYC 4 0 is not the number of audio data bits but the num ber of bit clock cycles that is used to adjust the sample clock period It must be equal to or greater than the number of audio data bits 16 bits 1 2 3 15 16 17 n 1 2 3 D15 D2 D1 D0 D14 I2S_WS I2S_SCLK Bit clock cycle count by setting WSCLKCYC 4 0 I2S_SDO L channel R channel MSB first I2S mod...

Page 359: ...RT I2S Start Stop Control Bit Starts stops data output of the I2S 1 R W Start 0 R W Stop default Writing 1 to I2SSTART starts serial data transmission through the I2S_SDO pin Writing 0 to I2SSTART stops data transmission Note however that the data currently stored in the FIFO will be continuously transmitted through the I2S_SDO pin until the FIFO becomes empty After I2SSTART is set to 0 new transm...

Page 360: ...lize all four entries of FIFO This means that the I2S module is started and waits for filling the FIFO with the first four stereo data 0x0 STOP FIFO is idle This means that the I2S module is stopped Default 0x0 D1 I2SFIFOFF I2S FIFO Full Flag Bit Indicates whether the transmit FIFO is full or not 1 R Full 0 R Not full default I2SFIFOFF is set to 1 when the FIFO becomes full of the written data 16 ...

Page 361: ...ith two stereo data 16 bits 2 channels L R 2 Then reset HEIF by writing 1 at the end of the interrupt handler D8 OEIF I2S FIFO One Empty Interrupt Flag Bit Indicates whether the cause of I2S FIFO one empty interrupt has occurred or not 1 R Cause of interrupt has occurred 0 R No cause of interrupt has occurred default 1 W Flag is reset 0 W Ignored When a free space for one stereo data becomes avail...

Page 362: ...rite ld w rb rs instruction Note that 8 bit memory write instructions cannot be used When using a 16 bit memory write ld h rb rs instruction first write L channel data to address 0x301410 then R channel data to address 0x301412 Both channel data must be written as a pair even if mono is selected as the output channel mode Write the first to fourth data to the same addresses 0x301410 0x301412 witho...

Page 363: ...le clock I2S_WS frequency 33 MHz fI2S_MCLK eq1 MCLKDIV 5 0 1 33 MHz fI2S_WS eq2 BCLKDIV 7 0 1 2 WSCLKCYC 4 0 16 2 BCLKDIV 7 0 1 2 WSCLKCYC 4 0 16 2 Integer eq3 MCLKDIV 5 0 1 8 1 I2S_MCLK Master Clock Settings Table 21 MCLKDIV 5 0 PCLK1 division ratio 0x3f 1 64 0x3e 1 63 0x3d 1 62 0x2 1 3 0x1 1 2 0x0 1 1 8 2 I2S_SCLK Bit Clock Settings Table 21 BCLKDIV 7 0 PCLK1 division ratio 0xff 1 512 0xfe 1 510...

Page 364: ...8 34 38 32 74 31 25 29 89 28 65 27 50 26 44 25 46 24 55 23 71 22 92 22 18 21 48 15 12 39 66 37 33 35 26 33 40 31 73 30 22 28 85 27 59 26 44 25 38 24 41 23 50 22 66 21 88 21 15 20 47 19 83 16 13 36 83 34 66 32 74 31 02 29 46 28 06 26 79 25 62 24 55 23 57 22 66 21 83 21 05 20 32 19 64 19 01 18 42 17 14 34 38 32 35 30 56 28 95 27 50 26 19 25 00 23 91 22 92 22 00 21 15 20 37 19 64 18 97 18 33 17 74 17...

Page 365: ...cted BCLKDIV 7 0 and WSCLKCYC 4 0 values to Cells U2 and V2 respectively Integer appears in the cell corresponding to the MCLKDIV 5 0 value that can be set MCLKDIV 5 0 0 1 3 10 16 21 33 43 8 6 Master Clock Frequency Table 21 MCLKDIV 5 0 fI2S_MCLK 0 33 MHz 748 fs 1 16 5 MHz 374 fs 3 8 25 MHz 187 fs 10 3 MHz 68 fs 16 1 941 MHz 44 fs 21 1 5 MHz 34 fs 33 970 588 kHz 22 fs 43 750 kHz 17 fs Select an ap...

Page 366: ... registers Data length counter REMC_O REMC_I Edge detector Modulator Interrupt control PCLK2 1 PCLK2 16K Prescaler ITC 1 1 REMC Module Configuration Figure 22 REMC Input Output Pins 22 2 Table 22 2 1 lists the REMC input output pins 2 1 List of REMC Pins Table 22 Pin name I O Qty Function REMC_I I 1 Remote control receive data input pin Inputs receive data REMC_O O 1 Remote control transmit data o...

Page 367: ... 3 0 0x2 PCLK2 4 REMCH 5 0 2 REMCL 5 0 1 PCLK2 PSC Ch 1 output clock Count Carrier 0 1 2 0 1 0 Carrier H section length Carrier L section length 3 1 Carrier Signal Generation Figure 22 Data Length Counter Clock Settings 22 4 The data length counter is an 8 bit counter for setting data lengths when transmitting data When a value corresponding to the data pulse width is written during data transmiss...

Page 368: ...Note Make sure the REMC module is halted REMEN REMC_CFG register 0 before changing the above settings Data transmission control REMDT REMC_O pin output Carrier REMDT REMC_O pin output 5 1 Data Transmission Figure 22 PCLK2 PSC Ch 1 output clock Data length counter clock REMLEN 7 0 Interrupt signal 4 3 2 1 0 5 2 Underflow Interrupt Generation Timing Figure 22 1 Data transmit mode setting Set REMC to...

Page 369: ...ck Data length counter clock REMC_I input REMDT Sampled waveform REMRIF REMFIF Interrupt signal REMLEN 7 0 Write 0xff x 2 x 1 x 0xff 0xfe 0xfd 0xff Write 0xff Write 1 Write 1 5 3 Data Reception Figure 22 1 Data receive mode setting Set REMC to receive mode by writing 1 to REMMD REMC_CFG register 2 Enabling data reception Enable REMC operation by setting REMEN REMC_CFG register to 1 This initiates ...

Page 370: ... occurred To use this interrupt set REMUIE REMC_INT register to 1 If REMUIE is set to 0 default the interrupt re quest attributable to this cause will not be sent to the ITC When REMUIF is set to 1 REMC outputs an interrupt request to the ITC An interrupt will be generated if the ITC and C33 PE Core interrupt conditions are met REMUIF should be inspected in the REMC interrupt handler routine to de...

Page 371: ... 16 bit registers Note When data is written to the registers the Reserved bits must always be written as 0 and not 1 REMC Configuration Register REMC_CFG Register name Address Bit Name Function Setting Init R W Remarks REMC Configuration Register REMC_CFG 0x301500 16 bits D15 12 CGCLK 3 0 Carrier generator clock division ratio select Prescaler output clock CGCLK 3 0 LCCLK 3 0 Division ratio 0x0 R ...

Page 372: ...gth Setup Register REMC_CAR 0x301502 16 bits D15 14 reserved 0 when being read D13 8 REMCL 5 0 Carrier L length setup 0x0 to 0x3f 0x0 R W D7 6 reserved 0 when being read D5 0 REMCH 5 0 Carrier H length setup 0x0 to 0x3f 0x0 R W D 15 14 Reserved D 13 8 REMCL 5 0 Carrier L Length Setup Bits Sets the carrier signal L section length Default 0x0 Specify a value corresponding to the number of carrier ge...

Page 373: ...sequent transmit data using this interrupt For data receiving Interrupts can be generated at the input signal rising or falling edges when receiving data The data pulse length can be obtained from the difference between 0xff set to the data length counter using the interrupt when the input changes and the count value read out when the next interrupt occurs due to an input change D 7 1 Reserved D0 ...

Page 374: ...errupt cause occurrence status 1 R Cause of interrupt has occurred 0 R No cause of interrupt has occurred default 1 W Flag is reset 0 W Ignored REMFIF is set to 1 at the input signal falling edge REMFIF is reset to 0 by writing 1 D9 REMRIF Rising Edge Interrupt Flag Bit Indicates the rising edge interrupt cause occurrence status 1 R Cause of interrupt has occurred 0 R No cause of interrupt has occ...

Page 375: ...ad signal output pin This pin outputs the read signal for NAND Flash and SmartMedia card NAND_WR O 1 SmartMedia write signal output pin This pin outputs the write signal for NAND Flash and SmartMedia card The CARD output pins NAND_RD NAND_WR are shared with I O ports and are initially set as general pur pose I O port pins The pin functions must be switched using the port function select bits to us...

Page 376: ... of GPIO ports depends on the peripheral functions used Can generate input interrupts from the 16 of 64 ports selected via software Interrupt input signal conditions level or edge trigger and polarity can be specified The input interrupt circuit includes chattering filters All port provide a port function select bit to configure the pin function for GPIO or peripheral functions Figure 24 1 1 shows...

Page 377: ...0 TFT_CTL0 T16A_ATMA_0 CFP30 1 0 PMUX_P3_03 register P31 TFT_CTL1 T16A_ATMB_0 CFP31 1 0 PMUX_P3_03 register P32 TFT_CTL2 REMC_O CFP32 1 0 PMUX_P3_03 register P33 TFT_CTL3 REMC_I CFP33 1 0 PMUX_P3_03 register DCLK P34 CFP34 1 0 PMUX_P3_46 register DSIO P35 CFP35 1 0 PMUX_P3_46 register DST2 P36 CFP36 1 0 PMUX_P3_46 register A21 P40 FPDAT18 NAND_RD CFP40 1 0 PMUX_P4_02 register A22 P41 FPDAT17 NAND_...

Page 378: ...al modules The sections below describe port functions with the pins set as general purpose I O ports Note The port function select registers PMUX_Px_ are write protected Before these registers can be rewritten the write protection must be removed by writing data 0x96 to PPROT 7 0 GPIO_ PROTECT register Note that since unnecessary rewrites to the port function select registers could lead to erratic...

Page 379: ...d the ports can be selected for generat ing each cause of interrupt The interrupt trigger conditions can also be selected from between input signal edge rising edge or falling edge and input signal level high level or low level Figure 24 5 1 shows the configuration of the port interrupt circuit SIET0 SEPT0 SFGP0 P30 P10 P50 P00 SPPT0 SCTP0 2 0 SPT0 1 0 Chattering filter Trigger mode polarity contr...

Page 380: ...SPT7 1 0 Chattering filter Trigger mode polarity control FPT7 ANFEN Noise filter ANFEN Noise filter ANFEN Noise filter ANFEN Noise filter SIET8 SEPT8 SFGP8 P90 P80 PB0 P40 SPPT8 SCTP8 2 0 SPT8 1 0 Chattering filter Trigger mode polarity control Port input interrupt 2 request to ITC Port input interrupt 2 FPT8 SIET9 SEPT9 SFGP9 P91 P81 PB1 P41 SPPT9 SCTP9 2 0 SPT9 1 0 Chattering filter Trigger mode...

Page 381: ...our ports to generate interrupts Select the ports using SPTn 1 0 GPIO_ FPTnn_SEL register n 0 to F nn 03 47 8B or CF 5 1 Selecting Ports Used For Port Interrupt 0 Table 24 SPTn 1 0 setting FPT0 SPT0 1 0 FPT1 SPT1 1 0 FPT2 SPT2 1 0 FPT3 SPT3 1 0 0x3 P30 P31 P32 P33 0x2 P10 P11 P12 P13 0x1 P50 P51 P52 P53 0x0 default P00 P01 P02 P03 5 2 Selecting Ports Used For Port Interrupt 1 Table 24 SPTn 1 0 set...

Page 382: ...o the FPT interrupt ports In level trigger mode the interrupt flag is set according to the input signal level In edge trigger mode the interrupt flag is set at the active edge of the input signal The interrupt flag must be reset by writing 1 after an interrupt occurs Interrupt enable bits Each FPT interrupt port can be enabled or disabled to generate interrupts using the corresponding interrupt en...

Page 383: ...LK2 2 32 fPCLK2 4 0x5 16 fPCLK2 16 fPCLK2 2 16 fPCLK2 4 0x4 8 fPCLK2 8 fPCLK2 2 8 fPCLK2 4 0x3 4 fPCLK2 4 fPCLK2 2 4 fPCLK2 4 0x2 2 fPCLK2 2 fPCLK2 2 2 fPCLK2 4 0x1 1 fPCLK2 1 fPCLK2 2 1 fPCLK2 4 0x0 Not filtered Default 0x0 Notes The prescaler PSC Ch 1 output is used as the filter clock Make sure the prescaler PSC Ch 1 is turned on before using the chattering filter Do not enable the chattering f...

Page 384: ...running by the instructions fetched from an external memory the CPU will not be able to run after that point To drive the signals low the CPU must be running with the program stored in the internal RAM Control Register Details 24 8 8 1 List of GPIO and Port MUX Registers Table 24 Address Register name Function 0x300300 GPIO_P0_DAT P0 Port Data Register P0 port input output data 0x300301 GPIO_P0_IO...

Page 385: ...terrupt Mask Register Enable disable FPT4 7 interrupts 0x30033e GPIO_FPT8B_MSK FPT8 B Interrupt Mask Register Enable disable FPT8 B interrupts 0x30033f GPIO_FPTCF_MSK FPTC F Interrupt Mask Register Enable disable FPTC F interrupts 0x300340 GPIO_FPT03_FLG FPT0 3 Interrupt Flag Register Indicate FPT0 3 interrupt cause status 0x300341 GPIO_FPT47_FLG FPT4 7 Interrupt Flag Register Indicate FPT4 7 inte...

Page 386: ...om which 0 is always read out D 7 0 Px 7 0 D Px 7 0 I O Port Data Bits These bits are used to read data from I O port pins or to set output data Default external pin status 1 R W High level 0 R W Low level PxyD corresponds directly to the Pxy pin The pin voltage level can be read out even if the port is set to output mode IOCxy GPIO_Px_IOC reg ister 1 The value read out will be 1 when the pin volt...

Page 387: ...ontrol Registers GPIO_Px_PUP Register name Address Bit Name Function Setting Init R W Remarks Px Port Pull up Control Register GPIO_Px_PUP 0x300321 0x30032c 8 bits D7 0 PUPx 7 0 Px 7 0 port pull up enable 1 Enable 0 Disable R W Write protected Note The PUPxy bits for unavailable pins are read only bits from which 0 is always read out D 7 0 PUPx 7 0 Px 7 0 Port Pull Up Enable Bits Enables or disabl...

Page 388: ...r generating port interrupt 0 D 1 0 SPT0 1 0 FPT0 Interrupt input Port Select Bits Selects an FPT0 port used for generating port interrupt 0 8 3 Selecting Ports Used For Port Interrupt 0 Table 24 SPTn 1 0 setting FPT0 SPT0 1 0 FPT1 SPT1 1 0 FPT2 SPT2 1 0 FPT3 SPT3 1 0 0x3 P30 P31 P32 P33 0x2 P10 P11 P12 P13 0x1 P50 P51 P52 P53 0x0 default P00 P01 P02 P03 FPT4 7 Interrupt Port Select Register GPIO_...

Page 389: ...0x0 P93 P83 PB3 P71 D5 4 SPTA 1 0 FPTA interrupt input port select SPTA 1 0 Port 0x0 R W 0x3 0x2 0x1 0x0 P92 P82 PB2 P42 D3 2 SPT9 1 0 FPT9 interrupt input port select SPT9 1 0 Port 0x0 R W 0x3 0x2 0x1 0x0 P91 P81 PB1 P41 D1 0 SPT8 1 0 FPT8 interrupt input port select SPT8 1 0 Port 0x0 R W 0x3 0x2 0x1 0x0 P90 P80 PB0 P40 D 7 6 SPTB 1 0 FPTB Interrupt input Port Select Bits Selects an FPTB port use...

Page 390: ...t Port Select Bits Selects an FPTC port used for generating port interrupt 3 8 6 Selecting Ports Used For Port Interrupt 3 Table 24 SPTn 1 0 setting FPTC SPTC 1 0 FPTD SPTD 1 0 FPTE SPTE 1 0 FPTF SPTF 1 0 0x3 P94 P95 P96 P97 0x2 PA4 PA5 PA6 P60 0x1 PB4 PB5 PB6 PB7 0x0 default P72 P73 P74 P75 FPT0 3 Interrupt Polarity Select Register GPIO_FPT03_POL Register name Address Bit Name Function Setting In...

Page 391: ...rved D 3 0 SPPT B 8 FPT B 8 Input Polarity Select Bits Selects the interrupt trigger level or edge for the ports used for port interrupt 2 FPT8 FPTB 1 R W High level Rising edge default 0 R W Low level Falling edge See the descriptions of SPPT 3 0 GPIO_FPT03_POL register FPTC F Interrupt Polarity Select Register GPIO_FPTCF_POL Register name Address Bit Name Function Setting Init R W Remarks FPTC F...

Page 392: ...ct 1 Edge 0 Level 1 R W D 7 4 Reserved D 3 0 SEPT 7 4 FPT 7 4 Interrupt Mode Select Bits Selects trigger modes of the ports used for port interrupt 1 FPT4 FPT7 1 R W Edge trigger mode default 0 R W Level trigger mode See the descriptions of SEPT 3 0 GPIO_FPT03_MOD register FPT8 B Interrupt Mode Select Register GPIO_FPT8B_MOD Register name Address Bit Name Function Setting Init R W Remarks FPT8 B I...

Page 393: ... interrupt enable 1 Enable 0 Disable 0 R W D1 SIET5 FPT5 interrupt enable 1 Enable 0 Disable 0 R W D0 SIET4 FPT4 interrupt enable 1 Enable 0 Disable 0 R W D 7 4 Reserved D 3 0 SIET 7 4 FPT 7 4 Interrupt Enable Bits Enables or disables the ports to generate port interrupt 1 FPT4 FPT7 1 R W Interrupt enabled 0 R W Interrupt disabled default FPT8 B Interrupt Mask Register GPIO_FPT8B_MSK Register name...

Page 394: ... a port interrupt request signal is also output to the ITC at the same time An interrupt is generated if the ITC and C33 PE Core interrupt conditions are satisfied SFGPn is reset by writing 1 FPT4 7 Interrupt Flag Register GPIO_FPT47_FLG Register name Address Bit Name Function Setting Init R W Remarks FPT4 7 Interrupt Flag Register GPIO_FPT47_ FLG 0x300341 8 bits D7 4 reserved 0 when being read D3...

Page 395: ...t cause occurred 1 W Reset flag 0 W Ignored See the descriptions of SFGP 3 0 GPIO_FPT03_FLG register FPT0 1 Interrupt Chattering Filter Control Register GPIO_FPT01_CHAT Register name Address Bit Name Function Setting Init R W Remarks FPT0 1 Interrupt Chattering Filter Control Register GPIO_FPT01_ CHAT 0x300344 8 bits D7 reserved 0 when being read D6 4 SCTP1 2 0 FPT1 chattering filter time select S...

Page 396: ...herefore the port input interrupt must be disabled before setting the GPIO_FPTnn_CHAT register Furthermore be sure to clear the port input inter rupt flag before enabling the interrupt again after setting the GPIO_FPTnn_CHAT register In this case clear the interrupt flag after the wait time shown below has elapsed from the GPIO_FPTnn_CHAT register setting Wait time µs Filter sampling time µs 4 Exa...

Page 397: ...PCLK2 None D7 Reserved D 6 4 SCTP5 2 0 FPT5 Chattering Filter Time Select Bits Configures the chattering filter circuit for the FPT5 port D3 Reserved D 2 0 SCTP4 2 0 FPT4 Chattering Filter Time Select Bits Configures the chattering filter circuit for the FPT4 port See the descriptions of SCTP0 2 0 GPIO_FPT01_CHAT register FPT6 7 Interrupt Chattering Filter Control Register GPIO_FPT67_CHAT Register...

Page 398: ...PCLK2 None D7 Reserved D 6 4 SCTP9 2 0 FPT9 Chattering Filter Time Select Bits Configures the chattering filter circuit for the FPT9 port D3 Reserved D 2 0 SCTP8 2 0 FPT8 Chattering Filter Time Select Bits Configures the chattering filter circuit for the FPT8 port See the descriptions of SCTP0 2 0 GPIO_FPT01_CHAT register FPTA B Interrupt Chattering Filter Control Register GPIO_FPTAB_CHAT Register...

Page 399: ...PCLK2 None D7 Reserved D 6 4 SCTPD 2 0 FPTD Chattering Filter Time Select Bits Configures the chattering filter circuit for the FPTD port D3 Reserved D 2 0 SCTPC 2 0 FPTC Chattering Filter Time Select Bits Configures the chattering filter circuit for the FPTC port See the descriptions of SCTP0 2 0 GPIO_FPT01_CHAT register FPTE F Interrupt Chattering Filter Control Register GPIO_FPTEF_CHAT Register...

Page 400: ... DMA transfer 8 8 DMA Trigger Source Selection Table 24 SPTRG 3 0 Trigger source SPTRG 3 0 Trigger source 0xf FPTF 0x7 FPT7 0xe FPTE 0x6 FPT6 0xd FPTD 0x5 FPT5 0xc FPTC 0x4 FPT4 0xb FPTB 0x3 FPT3 0xa FPTA 0x2 FPT2 0x9 FPT9 0x1 FPT1 0x8 FPT8 0x0 FPT0 Default 0x0 The interrupt signal of the selected FPT line which is generated according to the interrupt mode and polarity settings regardless of the S...

Page 401: ... SOUT1 USI_DO P01 D1 0 CFP00 1 0 P00 port function select CFP00 1 0 Function 0x0 R W 0x3 0x2 0x1 0x0 NAND_WR SIN1 USI_DI P00 The GPIO pins are shared with the peripheral module pins This register is used to select how the pins are used D 7 6 CFP03 1 0 P03 Port Function Select Bits 0x3 R W REMC_I REMC 0x2 R W SRDY1 FSIO Ch 1 0x1 R W USI_CK USI 0x0 R W P03 GPIO default D 5 4 CFP02 1 0 P02 Port Funct...

Page 402: ...T0 P05 D1 0 CFP04 1 0 P04 port function select CFP04 1 0 Function 0x0 R W 0x3 0x2 0x1 0x0 T16A_ATMA_0 I2S_SDO SIN0 P04 The GPIO pins are shared with the peripheral module pins This register is used to select how the pins are used D 7 6 CFP07 1 0 P07 Port Function Select Bits 0x3 R W PWM_L T16P 0x2 R W I2S_MCLK I2S 0x1 R W SRDY0 FSIO Ch 0 0x0 R W P07 GPIO default D 5 4 CFP06 1 0 P06 Port Function S...

Page 403: ...d FPDAT9 USIL_DO P11 D1 0 CFP10 1 0 P10 port function select CFP10 1 0 Function 0x0 R W 0x3 0x2 0x1 0x0 reserved FPDAT8 USIL_DI P10 The GPIO pins are shared with the peripheral module pins This register is used to select how the pins are used D 7 6 CFP13 1 0 P13 Port Function Select Bits 0x3 R W T16A_ATMB_1 T16A5 Ch 1 0x2 R W FPDAT11 LCDC 0x1 R W USIL_CK USIL 0x0 R W P13 GPIO default D 5 4 CFP12 1...

Page 404: ... Select Bits 0x3 R W Reserved 0x2 R W FPDAT15 LCDC 0x1 R W P17 GPIO 0x0 R W DPCO DBG default D 5 4 CFP16 1 0 P16 Port Function Select Bits 0x3 R W Reserved 0x2 R W FPDAT14 LCDC 0x1 R W P16 GPIO 0x0 R W DST1 DBG default D 3 2 CFP15 1 0 P15 Port Function Select Bits 0x3 R W Reserved 0x2 R W FPDAT13 LCDC 0x1 R W P15 GPIO 0x0 R W DST0 DBG default D 1 0 CFP14 1 0 P14 Port Function Select Bits 0x3 R W C...

Page 405: ...REMC_O TFT_CTL2 reserved P32 D3 2 CFP31 1 0 P31 port function select CFP31 1 0 Function 0x0 R W 0x3 0x2 0x1 0x0 T16A_ATMB_0 TFT_CTL1 reserved P31 D1 0 CFP30 1 0 P30 port function select CFP30 1 0 Function 0x0 R W 0x3 0x2 0x1 0x0 T16A_ATMA_0 TFT_CTL0 reserved P30 The GPIO pins are shared with the peripheral module pins This register is used to select how the pins are used D 7 6 CFP33 1 0 P33 Port F...

Page 406: ...Bits 0x3 R W Reserved 0x2 R W Reserved 0x1 R W P36 GPIO 0x0 R W DST2 DBG default D 3 2 CFP35 1 0 P35 Port Function Select Bits 0x3 R W Reserved 0x2 R W Reserved 0x1 R W P35 GPIO 0x0 R W DSIO DBG default D 1 0 CFP34 1 0 P34 Port Function Select Bits 0x3 R W Reserved 0x2 R W Reserved 0x1 R W P34 GPIO 0x0 R W DCLK DBG default P4 2 0 Port Function Select Register PMUX_P4_02 Register name Address Bit N...

Page 407: ...CFP53 1 0 Function 0x0 R W Write protected 0x3 0x2 0x1 0x0 reserved reserved P53 CE10 D5 4 CFP52 1 0 P52 port function select CFP52 1 0 Function 0x0 R W 0x3 0x2 0x1 0x0 reserved CE5 P52 CE9 D3 2 CFP51 1 0 P51 port function select CFP51 1 0 Function 0x0 R W 0x3 0x2 0x1 0x0 reserved CE4 P51 CE8 D1 0 CFP50 1 0 P50 port function select CFP50 1 0 Function 0x0 R W 0x3 0x2 0x1 0x0 reserved SDCS P50 CE7 T...

Page 408: ... register is used to select how the pins are used D 7 6 Reserved D 5 4 CFP56 1 0 P56 Port Function Select Bits 0x3 R W Reserved 0x2 R W Reserved 0x1 R W P56 GPIO 0x0 R W WRH BSH SRAMC default D 3 2 CFP55 1 0 P55 Port Function Select Bits 0x3 R W Reserved 0x2 R W Reserved 0x1 R W P55 GPIO 0x0 R W WRL SRAMC default D 1 0 CFP54 1 0 P54 Port Function Select Bits 0x3 R W Reserved 0x2 R W Reserved 0x1 R...

Page 409: ...Select Bits 0x3 R W Reserved 0x2 R W Reserved 0x1 R W AIN3 ADC10 0x0 R W P73 GPIO default D 5 4 CFP72 1 0 P72 Port Function Select Bits 0x3 R W Reserved 0x2 R W PWM_EXCL T16P 0x1 R W AIN2 ADC10 0x0 R W P72 GPIO default D 3 2 CFP71 1 0 P71 Port Function Select Bits 0x3 R W Reserved 0x2 R W T16A_EXCL_1 T16A5 Ch 1 0x1 R W AIN1 ADC10 0x0 R W P71 GPIO default D 1 0 CFP70 1 0 P70 Port Function Select Bi...

Page 410: ...W 0x3 0x2 0x1 0x0 reserved USIL_DI FPSHIFT P82 D3 2 CFP81 1 0 P81 port function select CFP81 1 0 Function 0x0 R W 0x3 0x2 0x1 0x0 reserved USIL_CK FPLINE P81 D1 0 CFP80 1 0 P80 port function select CFP80 1 0 Function 0x0 R W 0x3 0x2 0x1 0x0 reserved USIL_CS FPFRAME P80 The GPIO pins are shared with the peripheral module pins This register is used to select how the pins are used D 7 6 CFP83 1 0 P83...

Page 411: ...CD_D1 FPDAT1 P91 D1 0 CFP90 1 0 P90 port function select CFP90 1 0 Function 0x0 R W 0x3 0x2 0x1 0x0 SIN0 LCD_D0 FPDAT0 P90 The GPIO pins are shared with the peripheral module pins This register is used to select how the pins are used D 7 6 CFP93 1 0 P93 Port Function Select Bits 0x3 R W SRDY0 FSIO Ch 0 0x2 R W LCD_D3 USIL 0x1 R W FPDAT3 LCDC 0x0 R W P93 GPIO default D 5 4 CFP92 1 0 P92 Port Functi...

Page 412: ...1 0x0 reserved LCD_D5 FPDAT5 P95 D1 0 CFP94 1 0 P94 port function select CFP94 1 0 Function 0x0 R W 0x3 0x2 0x1 0x0 reserved LCD_D4 FPDAT4 P94 The GPIO pins are shared with the peripheral module pins This register is used to select how the pins are used D 7 6 CFP97 1 0 P97 Port Function Select Bits 0x3 R W Reserved 0x2 R W LCD_D7 USIL 0x1 R W FPDAT7 LCDC 0x0 R W P97 GPIO default D 5 4 CFP96 1 0 P9...

Page 413: ...s 0x3 R W FPDAT23 LCDC 0x2 R W FPDAT19 LCDC 0x1 R W SRDY1 FSIO Ch 1 0x0 R W PA3 GPIO default D 5 4 CFPA2 1 0 PA2 Port Function Select Bits 0x3 R W FPDAT22 LCDC 0x2 R W FPDAT18 LCDC 0x1 R W SCLK1 FSIO Ch 1 0x0 R W PA2 GPIO default D 3 2 CFPA1 1 0 PA1 Port Function Select Bits 0x3 R W FPDAT21 LCDC 0x2 R W FPDAT17 LCDC 0x1 R W SOUT1 FSIO Ch 1 0x0 R W PA1 GPIO default D 1 0 CFPA0 1 0 PA0 Port Function...

Page 414: ...00816 8 bits D7 6 CFPB3 1 0 PB3 port function select CFPB3 1 0 Function 0x0 R W Write protected 0x3 0x2 0x1 0x0 PWM_L I2S_MCLK FPDAT11 PB3 D5 4 CFPB2 1 0 PB2 port function select CFPB2 1 0 Function 0x0 R W 0x3 0x2 0x1 0x0 PWM_H I2S_SCLK FPDAT10 PB2 D3 2 CFPB1 1 0 PB1 port function select CFPB1 1 0 Function 0x0 R W 0x3 0x2 0x1 0x0 reserved I2S_WS FPDAT9 PB1 D1 0 CFPB0 1 0 PB0 port function select C...

Page 415: ...5 port function select CFPB5 1 0 Function 0x0 R W 0x3 0x2 0x1 0x0 FPDAT21 reserved FPDAT13 PB5 D1 0 CFPB4 1 0 PB4 port function select CFPB4 1 0 Function 0x0 R W 0x3 0x2 0x1 0x0 FPDAT20 reserved FPDAT12 PB4 The GPIO pins are shared with the peripheral module pins This register is used to select how the pins are used D 7 6 CFPB7 1 0 PB7 Port Function Select Bits 0x3 R W FPDAT23 LCDC 0x2 R W Reserve...

Page 416: ...W 0x3 0x2 0x1 0x0 reserved reserved PC1 D9 D1 0 CFPC0 1 0 PC0 port function select CFPC0 1 0 Function 0x0 R W 0x3 0x2 0x1 0x0 reserved reserved PC0 D8 The GPIO pins are shared with the peripheral module pins This register is used to select how the pins are used D 7 6 CFPC3 1 0 PC3 Port Function Select Bits 0x3 R W Reserved 0x2 R W Reserved 0x1 R W PC3 GPIO 0x0 R W D11 SRAMC default D 5 4 CFPC2 1 0...

Page 417: ...C7 Port Function Select Bits 0x3 R W Reserved 0x2 R W Reserved 0x1 R W PC7 GPIO 0x0 R W D15 SRAMC default D 5 4 CFPC6 1 0 PC6 Port Function Select Bits 0x3 R W Reserved 0x2 R W Reserved 0x1 R W PC6 GPIO 0x0 R W D14 SRAMC default D 3 2 CFPC5 1 0 PC5 Port Function Select Bits 0x3 R W Reserved 0x2 R W Reserved 0x1 R W PC5 GPIO 0x0 R W D13 SRAMC default D 1 0 CFPC4 1 0 PC4 Port Function Select Bits 0x...

Page 418: ...write protection of the GPIO registers 0x300320 0x30032c and 0x30083e and PMUX registers 0x300800 0x300819 Writing another value set the write protection 0x0 R W D 7 0 PPROT 7 0 GPIO PMUX Register Protect Flag Bits Enables or disables write protection of the GPIO registers 0x300320 0x30032c and 0x30083e and PMUX registers 0x300800 0x300819 0x96 R W Disable write protection Other than 0x96 R W Writ...

Page 419: ...single channel or multi channels terminated with software Supports three conversion triggers Software trigger External trigger input from the ADTRIG pin T8 Ch 2 underflow trigger The conversion results can be read as 16 bit data with the 10 bit converted data aligned to left or right Two types of interrupts can be generated Conversion completion interrupt Conversion data overwrite error interrupt ...

Page 420: ...put pins See Section 25 2 2 Set the A D conversion clock 3 Select the A D conversion start and end channels 4 Select the A D conversion mode 5 Select the A D conversion trigger source 6 Set the sampling time 7 Select the conversion result storing mode 8 When using A D converter interrupts set interrupt conditions See Section 25 5 Note Make sure the A D converter is disabled ADEN ADC10_CTL register...

Page 421: ...C10_TRG register and ADCE 2 0 ADC10_TRG register respectively 3 2 1 Relationship between ADCS ADCE and Input Channels Table 25 ADCS 2 0 ADCE 2 0 Channel selected 0x7 0x6 Reserved 0x5 AIN5 0x4 AIN4 0x3 AIN3 0x2 AIN2 0x1 AIN1 0x0 AIN0 Default 0x0 Example Operation of one A D conversion ADCS 2 0 0 ADCE 2 0 0 Converted only in AIN0 ADCS 2 0 0 ADCE 2 0 3 Converted in the following order AIN0 AIN1 AIN2 ...

Page 422: ...DTS 1 0 Trigger source 0x3 External trigger ADTRIG 0x2 Reserved 0x1 T8 Ch 2 0x0 Software trigger Default 0x0 1 External trigger ADTRIG The signal input to the ADTRIG pin is used as a trigger To use this trigger source the I O port pin must be configured for the ADTRIG input using the port function select bit see the I O Ports GPIO chapter An A D conversion starts when a Low level of the ADTRIG sig...

Page 423: ... 25 3 have been completed write 1 to ADEN ADC10_CTL register to enable the A D converter The A D converter is thereby ready to accept a trigger to start A D conversion To set up the A D converter again or when the A D converter is not used ADEN must be set to 0 Starting A D Conversion 25 4 2 The A D converter starts A D conversion when a trigger is input while ADEN is 1 When software trigger is se...

Page 424: ...e interrupt Once ADOWE is set it will not be reset until software writes 1 Since ADCF is also set simultaneously with ADOWE read out the converted data to reset ADCF Note Occurrence of an overwrite error does not stop continuous conversion Terminating A D Conversion 25 4 4 One time conversion mode ADMS 0 In one time mode the A D converter performs A D conversion within the channel range successive...

Page 425: ...ad ADOWE Interrupt request AIN0 Ch 0 Ch 0 Ch 0 AIN0 Sampling Conversion AIN0 AIN0 Sampling Clear Clear Conversion AIN0 converted data AIN0 converted data 0 is written to ADCTL to stop conversion Sampling Conversion AIN0 invalid 3 Single channel AIN0 continuous conversion mode ADCS 0 ADCE 0 ADMS 1 ADEN Trigger ADIBS A D operation ADD 15 0 ADCF Conversion result read ADOWE Interrupt request AIN0 Ch ...

Page 426: ... for this cause will not be sent to the ITC If the following A D conversion has completed when ADD 15 0 has not been read ADCF 1 the A D con verter sets ADOWE ADC10_CTL register to 1 indicating that ADD 15 0 is overwritten If conversion data overwrite error interrupts are enabled ADOIE 1 an interrupt request is sent simultaneously to the ITC An interrupt occurs if other interrupt conditions are me...

Page 427: ...10 8 ADCS 2 0 Start channel select 0x0 to 0x5 0x0 R W D7 STMD Conversion result storing mode 1 ADD 15 6 0 ADD 9 0 0 R W D6 ADMS Conversion mode select 1 Continuous 0 Single 0 R W D5 4 ADTS 1 0 Conversion trigger select ADTS 1 0 Trigger 0x0 R W 0x3 0x2 0x1 0x0 ADTRIG pin reserved T8 Ch 2 Software D3 reserved 0 when being read D2 0 ADST 2 0 Sampling time setting ADST 2 0 Sampling time 0x7 R W Always...

Page 428: ...DCS 2 0 and ADCE 2 0 have been converted once D 5 4 ADTS 1 0 Conversion Trigger Select Bits Selects a trigger source to start A D conversion 6 3 Trigger Selection Table 25 ADTS 1 0 Trigger source 0x3 External trigger ADTRIG 0x2 Reserved 0x1 T8 Ch 2 0x0 Software trigger Default 0x0 When an external trigger is used the ADTRIG pin must be configured in advance using the port func tion select bit see ...

Page 429: ...DD register have been overwritten before reading 1 R Overwrite error cause of interrupt has occurred 0 R Normal cause of interrupt has not occurred default 1 W Flag is reset 0 W Ignored When a single channel or multiple channels are being converted continuously ADD 15 0 is overwritten and ADOWE is set to 1 if the A D conversion currently underway is completed while ADCF is set to 1 before reading ...

Page 430: ...o 1 by the hardware ADCTL remains set while A D conversion is underway In one time conversion mode upon completion of A D conversion in the specified channels ADCTL is reset to 0 and the A D conversion circuit stops operating To stop A D conversion during operation in continuous conversion mode reset ADCTL by writing 0 When ADEN is 0 A D conversion disabled ADCTL is fixed to 0 with no trigger acce...

Page 431: ... 0x4 0x3 0x2 0x1 0x0 reserved 1 32768 1 16384 1 8192 1 4096 1 2048 1 1024 1 512 1 256 1 128 1 64 1 32 1 16 1 8 1 4 1 2 D 15 4 Reserved D 3 0 ADDF 3 0 A D Converter Clock Division Ratio Select Bits Selects the A D converter clock PCLK1 division ratio 6 5 A D Conversion Clock PCLK1 Division Ratio Selections Table 25 ADDF 3 0 Division Ratio 0xf Reserved 0xe 1 32768 0xd 1 16384 0xc 1 8192 0xb 1 4096 0...

Page 432: ...circuit The LCDC registers are mapped into area 6 and 32 bit accesses are possible The 20K byte internal VRAM IVRAM is mapped at addresses 0x90000 to 0x94fff The external VRAM map is configurable The frame interrupt signal is output to the ITC Display support 4 or 8 bit monochrome LCD interface 4 or 8 bit color LCD interface Single panel single drive passive displays 12 16 or 24 bit Generic HR TFT...

Page 433: ...rface Look up table LCDC cache Sequence controller Registers Power save circuit SAPB bridge GE CMU AHB bus interface SDRAM SRAM LCD interface FPDAT 23 0 FPFRAME FPLINE FPSHIFT FPDRDY TFT_CTL 3 0 To LCD panel LCDC clocks LCD Controller S1C33L26 AHB 1 AHB 2 2 1 LCD Controller Block Diagram Figure 26 SAPB bus interface The C33 PE Core accesses the LCDC registers and monochrome look up table through t...

Page 434: ... O 4 TFT interface control signal outputs The LCDC output pins are shared with I O ports and are initially set as general purpose I O port pins The pin func tions must be switched using the port function select bits to use the general purpose I O port pins as LCDC output pins For detailed information on pin function switching see the I O Ports GPIO chapter 3 2 Pin Configurations by LCD Panel Type ...

Page 435: ...it data width 1 8 bit data width 3 8 bit data width 0 1 bpp 1 2 bpp 2 4 bpp Color passive panel 0 STN 1 Color 0 4 bit data width 1 8 bit data width format 1 3 8 bit data width format 2 0 1 bpp 1 2 bpp 2 4 bpp 3 8 bpp 4 12 bpp 5 16 bpp TFT panel 1 TFT 1 Color 0 1 bpp 1 2 bpp 2 4 bpp 3 8 bpp 4 12 bpp 5 16 bpp 6 24 bpp The PANELSEL COLOR DWD 1 0 and BPP 2 0 control bits are assigned in the LCDC_DISPM...

Page 436: ...Plus Also the LCDC can switch the display by selecting a screen from two or more display data prepared in the VRAM Since the display start memory address is specified using a register display data can be stored in any location but it must be a word boundary address in the memory Figure 26 4 1 1 shows memory usage examples IVRAM SDRAM Window Main Sub When using Picture in Picture Plus IVRAM SDRAM W...

Page 437: ...2 1 LCDC Clock OSC3 Division Ratio Selections Table 26 LCLKDIV 4 0 Division ratio OSC3 n LCLKDIV 4 0 Division ratio OSC3 n 0x1f 1 32 0xf 1 16 0x1e 1 31 0xe 1 15 0x1d 1 30 0xd 1 14 0x1c 1 29 0xc 1 13 0x1b 1 28 0xb 1 12 0x1a 1 27 0xa 1 11 0x19 1 26 0x9 1 10 0x18 1 25 0x8 1 9 0x17 1 24 0x7 1 8 0x16 1 23 0x6 1 7 0x15 1 22 0x5 1 6 0x14 1 21 0x4 1 5 0x13 1 20 0x3 1 4 0x12 1 19 0x2 1 3 0x11 1 18 0x1 1 2 ...

Page 438: ...e type of LCD panel either color or monochrome COLOR 1 Color panel selected COLOR 0 Monochrome panel selected default Selecting the STN panel data width Use DWD 1 0 LCDC_DISPMOD register to select the data width and format for STN panels 5 1 1 Data Width Selection of STN Panels Table 26 COLOR DWD 1 0 LCD panel 1 0x3 Color single 8 bit passive LCD panel format 2 0x2 Reserved 0x1 Color single 8 bit ...

Page 439: ...diagram FPSMASK is set to 1 5 2 2 4 bit Single Monochrome Panel Timing Chart Example Figure 26 FPFRAME FPLINE FPDRDY MOD FPDAT 7 0 FPLINE FPDRDY MOD FPSHIFT FPDAT7 FPDAT6 FPDAT5 FPDAT4 FPDAT3 FPDAT2 FPDAT1 FPDAT0 Line 1 1 1 1 9 1 313 1 2 1 10 1 314 1 3 1 11 1 315 1 4 1 12 1 316 1 5 1 13 1 317 1 6 1 14 1 318 1 7 1 15 1 319 1 8 1 16 1 320 Line 2 Line 3 Line 1 Line 2 Line 4 Line 239 Line 240 VDP VNDP...

Page 440: ...ple Figure 26 FPFRAME FPLINE FPDAT 7 0 FPLINE FPSHIFT FPSHIFT2 FPDAT7 FPDAT6 FPDAT5 FPDAT4 FPDAT3 FPDAT2 FPDAT1 FPDAT0 Line 1 1 R1 1 G1 1 R236 1 B1 1 R2 1 B236 1 G2 1 B2 1 G237 1 R3 1 G3 1 R238 1 B3 1 R4 1 B238 1 G4 1 B4 1 G239 1 R5 1 G5 1 R240 1 B5 1 R6 1 B240 1 G6 1 R7 1 B7 1 G8 1 R9 1 B9 1 G10 1 R11 1 B6 1 G7 1 R8 1 B8 1 G9 1 R10 1 B10 1 G11 1 B11 1 G12 1 R13 1 B13 1 G14 1 R15 1 B15 1 G16 1 R12...

Page 441: ...al period HT HTCNT 6 0 1 8 Ts Ts Pixel clock LCLK period HTCNT 6 0 must be programmed such that the following condition is met HTCNT 6 0 HDPCNT 6 0 3 Note HT should be determined so that the horizontal non display period HNDP HT HDP will be longer than the time required when the LCDC accesses eight words in the VRAM HDP Horizontal display period Use HDPCNT 6 0 LCDC_HDISP register to set the horizo...

Page 442: ...IFT_MSK LCDC_DISPMOD register to 1 Note When using an STN panel the registers for setting the HR TFT timing parameters must be set to 0x0 HR TFT Panel Timing Parameters 26 5 3 The HR TFT panel timing parameters shown in Figures below can be set using the LCDC control registers FPLINE LP HPW HPS HDPS HT FPFRAME SPS VT VDPS VDP HDP VPS VPW Non display period Display period 5 3 1 HR TFT Panel Timing ...

Page 443: ...ing condition is met HDP 16 HDPCNT 6 0 1 HDPS Horizontal display period start position Use HDPSCNT 9 0 LCDC_HDPS register to set the horizontal display period start position for the HR TFT panel HDPS HDPCNT 9 0 1 Ts HDPSCNT 9 0 must be programmed such that the following condition is met HT HDP HDPS HPS Horizontal sync pulse start position Use FPLINE_ST 9 0 LCDC_FPLINE register to set the horizonta...

Page 444: ...y Use FPFRAME_POL LCDC_FPFR register to set the vertical sync pulse polarity for the HR TFT panel FPFRAME_POL 1 Active High FPFRAME_POL 0 Active low default Vertical sync pulse offset The vertical sync pulse position and width that are basically set in line units can be adjusted in pixel clock units FPLINE LP FPFRAME SPS without offset FPFRAME SPS with offset VPS VPW VPS FPLINE FPFRAME pulse polar...

Page 445: ... offset The TFT_CTL0 PS pulse position and width can be specified in pixel clock cycles Use CTL0ST 9 0 LCDC_TFT_CTL0 register to set the pulse start position and CTL0STP 9 0 LCDC_TFT_CTL0 register to set the pulse stop position These values should be specified an offset from the FPLINE pulse start position By setting this register the TFT_CTL0 pulse width is set to CTL0STP 9 0 CTL0ST 9 0 1 Ts To p...

Page 446: ...16 777 216 colors 2 R 8 bits G 8 bits B 8 bits 1 Limited to 4 096 colors in CSTN panels 2 Cannot be used in CSTN panels 3 The bit configuration of LUTRAM is R 5 bits G 6 bits and B 5 bits The bpp mode is set using BPP 2 0 LCDC_DISPMOD register 5 4 3 Bpp Mode Settings Table 26 BPP 2 0 bpp mode 0x7 Reserved 0x6 24 bpp 0x5 16 bpp 0x4 12 bpp 0x3 8 bpp 0x2 4 bpp 0x1 2 bpp 0x0 1 bpp Default 0x0 To displ...

Page 447: ...idth 320 pixels LUT Bypassed LCD characteristics Data 0 Low LCD brightness Display image Coordinates 0 0 320 pixels VRAM data Address 0x1000 0000 0x1000 0028 0x1000 0050 0xdf 0x83 0xdf 40 bytes line Note Display may be inverted depending on the LCD panel used 5 5 2 Example of VRAM Data in 1 bpp Mode Figure 26 2 bpp mode 4 colors or 4 gray levels In 2 bpp mode each 2 bit data in the VRAM correspond...

Page 448: ...d or an LUT entry number 0 to 15 when the look up table is used 1 0 0 0 D3 D2 D1 D0 LCD I F LCD I F LUT entries 0 to 15 3 0 2 0 VRAM Display start address Byte address offset 4 bit 1 pixel When LUT is bypassed When LUT is used FPDAT signals FPDAT signals LUT entry number x y MSB LSB Brightness data in the specified entry 0 1 5 0 4 0 2 7 0 6 0 3 9 0 8 0 4 11 0 10 0 5 13 0 12 0 6 15 0 14 0 7 b 7 4 b...

Page 449: ...ls LUT Bypassed LCD characteristics Data 0 Low LCD brightness Display image Coordinates 0 0 320 pixels VRAM data Address 0x1000 0000 0x1000 0140 0x1000 0280 0x00 0xe0 0x1c 0x07 0xff 0x1f 0xe7 0xfc 0x00 0x49 0xb6 0xff 320 bytes line Note Display may be inverted depending on the LCD panel used 5 5 8 Example of VRAM Data in 8 bpp Mode Figure 26 12 bpp mode 4K colors In 12 bpp mode each 12 bit data in...

Page 450: ...ely of the pixel This mode does not support the look up table 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 R4 R3 R2 R1 R0 G5 G4 G3 G5 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0 G2 G1 G0 B4 B3 B2 B1 B0 LCD I F VRAM Display start address Byte address offset 16 bit 1 pixel LUT bypassed FPDAT signals Byte 1 Byte 0 R4 R3 R2 R1 R0 Short x y MSB LSB MSB LSB 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Figure 26 5 5 11 VRAM Data Format i...

Page 451: ...xff 0x00 0xff 0xff 0x00 0x00 0x00 0x80 0x80 0x80 0xff 0xff 0xff 960 bytes line Note Display may be inverted depending on the LCD panel used 5 5 14 Example of VRAM Data in 24 bpp Mode Figure 26 Note When using the GE 24 bpp mode cannot be set as the GE does not support 24 bpp data LUT Bypass Mode 26 5 6 In LUT bypass mode LUTPASS LCDC_DISPMOD register 1 VRAM data are converted directly into the FP ...

Page 452: ...T21 FPDAT20 FPDAT19 FPDAT18 FPDAT17 FPDAT16 FPDAT15 FPDAT14 FPDAT13 FPDAT12 FPDAT11 FPDAT10 FPDAT9 FPDAT8 FPDAT7 FPDAT6 FPDAT5 FPDAT4 FPDAT3 FPDAT2 FPDAT1 FPDAT0 TFT panel G signals TFT panel B signals D1 5 6 2 FPDAT Signals in LUT Bypass Mode TFT panel 2 bpp mode Figure 26 5 6 2 Relationship between 2 bpp Pixel Data and FPDAT Signals Table 26 Pixel data FPDAT0 2 4 6 8 10 11 13 15 signals FPDAT1 3...

Page 453: ...w 0 Low 0 High 1 Low 0 Low 0 0x1 Low 0 Low 0 Low 0 High 1 Low 0 0x0 Low 0 Low 0 Low 0 Low 0 Low 0 8 bpp mode TFT panel LUT bypassed To ensure a uniform brightness R2 R0 G2 G0 and B1 B0 are connected to the TFT panel RGB signals repeatedly B0 LCDC signals 0 8 bpp pixel data TFT panel R signals FPDAT23 FPDAT22 FPDAT21 FPDAT20 FPDAT19 FPDAT18 FPDAT17 FPDAT16 FPDAT15 FPDAT14 FPDAT13 FPDAT12 FPDAT11 FP...

Page 454: ...ow 0 FPDAT2 Low 0 FPDAT12 Low 0 FPDAT7 High 1 FPDAT1 High 1 FPDAT11 Low 0 FPDAT6 Low 0 FPDAT0 Low 0 FPDAT5 Low 0 FPDAT 23 16 Low 0 16 bpp mode TFT panel LUT bypassed B0 LCDC signals 0 16 bpp pixel data TFT panel R signals FPDAT23 FPDAT22 FPDAT21 FPDAT20 FPDAT19 FPDAT18 FPDAT17 FPDAT16 FPDAT15 FPDAT14 FPDAT13 FPDAT12 FPDAT11 FPDAT10 FPDAT9 FPDAT8 FPDAT7 FPDAT6 FPDAT5 FPDAT4 FPDAT3 FPDAT2 FPDAT1 FPD...

Page 455: ... FPDAT19 Low 0 FPDAT16 Low 0 LUT bypass mode for CSTN panel When a CSTN panel is used LUT bypass mode is effective if the conditions shown below are all met The LUT bypass function is enabled LUTPASS LCDC_DISPMOD register 1 Color mode is selected COLOR LCDC_DISPMOD register 1 1 2 4 8 12 or 16 bpp mode is selected BPP 2 0 LCDC_DISPMOD register 0x0 to 0x5 In LUT bypass mode pixel data in the VRAM sp...

Page 456: ...s of the FPDAT signal B0 16 bpp pixel data B1 G0 G1 G2 R0 R1 R2 B2 B3 B4 G3 G4 G5 R3 R4 FPDAT 7 4 4 bit passive panel FPDAT 7 0 8 bit passive panel 5 6 13 FPDAT Signals in LUT Bypass Mode CSTN panel 16 bpp mode Figure 26 LUT bypass mode for MSTN panel When an MSTN panel is used LUT bypass mode is effective if the conditions shown below are all met The LUT bypass function is enabled LUTPASS LCDC_DI...

Page 457: ... below Each entry consists of 5 bit Red data D 15 11 6 bit Green data D 10 5 and 5 bit Blue data D 4 0 This allows the software to set a color out of 65 536 colors in each entry The entries to be used depend on the bpp mode selected VRAM data selects an entry Color look up table 16 bit color data LSB MSB Entry No 0 1 2 3 4 14 15 16 154 255 B0 LCDC signals TFT CSTN 0 TFT panel R signals FPDAT23 FPD...

Page 458: ...ay scale data if the conditions shown below are all met The LUT bypass function is disabled LUTPASS LCDC_DISPMOD register 0 Monochrome mode is selected COLOR LCDC_DISPMOD register 0 1 2 or 4 bpp mode is selected BPP 2 0 LCDC_DISPMOD register 0x0 to 0x2 The monochrome look up table consists of 4 bits 16 entries as shown in the figure below The software can set a gray level out of 16 levels in each ...

Page 459: ...tes 26 5 8 The frame rate is calculated from the LCD panel s horizontal and vertical total periods and pixel clock frequency as shown below fLCLK Frame rate HT VT fLCLK Pixel clock frequency fLCLK OSC3 1 to OSC3 32 Hz see Section 26 4 2 Setting the LCDC Clock HT Horizontal total period HT HTCNT 6 0 1 8 Ts where Ts pixel clock period VT Vertical total period VT VTCNT 9 0 1 lines Other Settings 26 5...

Page 460: ...e effective enable the LCD power supply using the port The procedure for initializing the LCD at power on is summarized below 1 Configure the clocks pins and display memory area refer to 26 4 System Settings 2 Set the LCD panel parameters display mode and look up tables refer to 26 5 Setting the LCD Panel 3 Enable the LCDC interrupt 4 Write display data to the display memory 5 Set the display star...

Page 461: ...layed in the main window the main window start address is 0x10012ca0 X1 8 32 word MW_OFS 11 0 word Y1 0x4b28 words 0x12ca0 bytes Main window start address 0x10000000 0x12ca0 0x10012ca0 The LCDC determines the addresses of the first and end pixels in each line as follows First pixel address in Nth line Display start address N 1 MW_OFS 11 0 word End pixel address in Nth line Display start address N ...

Page 462: ...e within the vertical non display period VNDPF 1 Picture in Picture Plus and Sub Window 26 6 5 Picture in Picture Plus enables a sub window to be overlaid on the main window The sub window may be posi tioned anywhere within the main window and is controlled through the sub window control registers The sub window retains the same color depth as the main window The sub window also supports the virtu...

Page 463: ...ne units For ex ample to specify the sub window vertical start position as 60 lines set PIP_YSTART 9 0 to 60 Sub screen address offset for virtual screen The virtual screen feature can also be used for the sub window Specify the screen address offset using SW_ OFS 11 0 LCDC_SUBOFS register Sub screen address offset Virtual screen width in pixels bpp 32 words See Main screen address offset for virt...

Page 464: ...screen address offset MW_OFS 11 0 800 pixels 4 bpp 32 bits 100 words LCDC_MAINOFS register 100 0x64 3 Sub window start address LCDC_SUBADR register 0x10100000 to 0x101257fc for 640 480 pixels word boundary address LCDC_SUBADR register 0x10100000 to 0x1015fffc for 1024 768 pixels word boundary address This register is used to change the sub window location in the virtual sub screen VRAM If LCDC_SUB...

Page 465: ...F LCDC_PSAVE register is set to 1 At the same time FRINTF LCDC_PSAVE register is set to 1 and the LCDC outputs an interrupt signal to the interrupt controller ITC if frame interrupts are enabled FRINTEN 1 An interrupt occurs if other interrupt conditions are met FPFRAME FPLINE FRINTF VNDPF VDP VNDP e g 3 lines Interrupt is generated Reset by writing 1 7 1 Frame Interrupt Timing Figure 26 For more ...

Page 466: ...nts of the reload table used in the control table reload function 9 1 Reload Table Contents LCDC Registers Table 26 Address Control register Base 0x00 LCDC Display Mode Register LCDC_DISPMOD 0x302060 Base 0x04 Main Window Display Start Address Register LCDC_MAINADR 0x302070 Base 0x08 Main Screen Address Offset Register LCDC_MAINOFS 0x302074 Base 0x0c Sub window Display Start Address Register LCDC_...

Page 467: ...icate LCDC status and set power save mode 0x302010 LCDC_HDISP Horizontal Display Register Set horizontal display period 0x302014 LCDC_VDISP Vertical Display Register Set vertical display period 0x302018 LCDC_MODR MOD Rate Register Set MOD rate 0x302020 LCDC_HDPS Horizontal Display Start Position Register Set horizontal display start position for TFT 0x302024 LCDC_VDPS Vertical Display Start Positi...

Page 468: ...D7 VNDPF Vertical display status flag 1 VNDP 0 VDP 1 R D6 2 reserved 0 when being read D1 0 PSAVE 1 0 Power save mode select PSAVE 1 0 Mode 0x0 R W 0x3 0x2 0x1 0x0 Normal reserved reserved Power save D31 FRINTF Frame Interrupt Flag Bit Indicates the frame interrupt cause occurrence status 1 R Cause of interrupt has occurred 0 R No cause of interrupt has occurred default 1 W Flag is reset 0 W Ignor...

Page 469: ...pixel period The following conditions must be satisfied when setting HTCNT 6 0 HTCNT 6 0 HDPCNT 6 0 3 HT HDP HDPS Note HT should be determined so that the horizontal non display period HNDP HT HDP will be longer than the time required when the LCDC accesses eight words in the VRAM D 15 7 Reserved D 6 0 HDPCNT 6 0 Horizontal Display Period HDP Setup Bits Sets the horizontal display period HDP panel...

Page 470: ...me Address Bit Name Function Setting Init R W Remarks Horizontal Display Start Position Register LCDC_HDPS 0x302020 32 bits D31 10 reserved 0 when being read D9 0 HDPSCNT 9 0 Horizontal display period start position for TFT HT HDP HDPS 1 HR TFT HT HDP HDPS other TFT HDPS HDPSCNT Ts 0x0 R W 0x0 must be set for STN panels Note This register is used only for setting HR TFT panel parameters When using...

Page 471: ...ls in pixel clock units Default 0x0 HPS FPLINE_ST 9 0 1 Ts Ts pixel clock period D 15 8 Reserved D7 FPLINE_POL FPLINE Pulse Polarity Setup Bit Sets the horizontal sync pulse polarity for HR TFT panels 1 R W Active high 0 R W Active low default D 6 0 FPLINE_WD 6 0 FPLINE Pulse Width Setup Bits Sets the horizontal sync pulse width HPW for HR TFT panels in pixel clock units Default 0x0 HPW FPLINE_WD ...

Page 472: ...ault 0x0 VPW FPFRAME_WD 6 0 1 HT FPFRAME_STOFS 9 0 FPFRAME_STPOFS 9 0 Ts Ts pixel clock period D 15 10 Reserved D 9 0 FPFRAME_STOFS 9 0 FPFRAME Pulse Start Offset Bits Adjusts the vertical sync pulse start position which has been set in line units in pixel clock units Default 0x0 VPS FPFRAME_ST 9 0 HT FPFRAME_STOFS 9 0 Ts Ts pixel clock period TFT Special Output Register LCDC_TFTSO Register name A...

Page 473: ...en TFT_CTL1 and TFT_CTL0 1 R W Swapped TFT_CTL0 CLS TFT_CTL1 PS 0 R W Not swapped TFT_CTL0 PS TFT_CTL1 CLS default TFT_CTL1 Pulse Register LCDC_TFT_CTL1 Register name Address Bit Name Function Setting Init R W Remarks TFT_CTL1 Pulse Register LCDC_TFT_ CTL1 0x302044 32 bits D31 26 reserved 0 when being read D25 16 CTL1STP 9 0 TFT_CTL1 pulse stop offset TFT_CTL1 pulse width CTL1STP CTL1ST 1 Ts Stop ...

Page 474: ...0 pulse width to CTL0STP 9 0 CTL0ST 9 0 1 Ts To enable this register set CTLCNT_RUN LCDC_TFTSO register to 1 TFT_CTL2 Register LCDC_TFT_CTL2 Register name Address Bit Name Function Setting Init R W Remarks TFT_CTL2 Register LCDC_TFT_ CTL2 0x30204c 32 bits D31 10 reserved 0 when being read D9 0 CTL2DLY 9 0 TFT_CTL2 delay setup Delay CTL2DLY Ts 0x0 R W 2 For TFT This register is enabled when CTLCNT_...

Page 475: ...red 1 R Reloading 0 R Reloading has finished default Writing 1 to CTABRLD resets the control registers with the reload table data This reload operation should be performed during a vertical non display period CTABRLD retains 1 during reloading and it reverts to 0 when the reloading is completed See Section 26 9 for the reload table contents LCDC Reload Table Base Address Register LCDC_RLDADR Regis...

Page 476: ...TFT 1 R W TFT panel 0 R W STN panel default When TFT panel is selected COLOR and DWD 1 0 settings are disabled D30 COLOR Color Mono Select Bit Selects the type of connected LCD panel color or monochrome 1 R W Color panel 0 R W Monochrome panel default D29 FPSHIFT_MSK FPSHIFT Mask Enable Bit Enables the FPSHIFT mask effective only for STN monochrome LCD panels and HR TFT panels 1 R W Enabled 0 R W ...

Page 477: ...anels 1 R W Repeated 0 R W Not repeated default When FRMRPT is set to 1 the internal 19 bit frame counter is enabled and starts counting the number of frames Each time this counter overflows 0x40000 0 the frame rate modulation pattern is re peated When FRMRPT is set to 0 the counter is disabled and the frame rate modulation pattern is not repeated D 6 5 Reserved D4 LUTPASS LUT Bypass Mode Select B...

Page 478: ...pixels bpp 32 See Main screen address offset for virtual screen in Section 26 6 2 for more information on the virtual screen and the configurations Sub window Display Start Address Register LCDC_SUBADR Register name Address Bit Name Function Setting Init R W Remarks Sub window Display Start Address Register LCDC_ SUBADR 0x302080 32 bits D31 0 SW_START 31 0 Sub window start address SW_START31 MSB S...

Page 479: ...ndow vertical start position as 60 lines set PIP_YSTART 9 0 to 60 D 15 10 Reserved D 9 0 PIP_XSTART 9 0 Sub Window Horizontal X Start Position Bits Sets the sub window horizontal display start position Default 0x0 Convert the number of pixels from the LCD panel origin point to the upper left corner of the sub win dow into the number of data words according to the bpp mode and set it to these bits ...

Page 480: ...R W D19 16 MLUT4 3 0 Monochrome LUT entry 4 data 0x0 to 0xf 0x0 R W D15 12 MLUT3 3 0 Monochrome LUT entry 3 data 0x0 to 0xf 0x0 R W D11 8 MLUT2 3 0 Monochrome LUT entry 2 data 0x0 to 0xf 0x0 R W D7 4 MLUT1 3 0 Monochrome LUT entry 1 data 0x0 to 0xf 0x0 R W D3 0 MLUT0 3 0 Monochrome LUT entry 0 data 0x0 to 0xf 0x0 R W Monochrome Look up Table Register 1 LCDC_MLUT1 0x302094 32 bits D31 28 MLUT15 3 0...

Page 481: ... Clipping Line width setting Drawing color setting Octant selection for circle drawing Block copy XOR mesh transparency Color replacement color inversion with palettes Resize tiling rotation in 90 degree angle texts compressed image Command set Drawing functions can be specified by a 32 bit command one to six 32 bits arguments Number of commands 18 commands in all The image to be displayed can be ...

Page 482: ...the VRAM capacity Effective range of the coordinate system X Y 0 0 to 4095 4095 A work area to which objects images can actually be drawn VRAM is used normally must be configured within this range in advance A work area over error occurs if the whole of an object image is drawn outside the work area No error occurs if a part of an object image is beyond the work area Maximum work area range Maximu...

Page 483: ...st to the specified value The data size depends on the bpp mode Furthermore when the work area is rotated its width and height must be reset according to the rotation angle Therefore VWIN_W 11 0 and VWIN_ H 11 0 should be set after setting the bpp mode and the angle of work area rotation See Table 27 3 1 4 for VWIN_W 11 0 and VWIN_H 11 0 settings for different bpp modes and rotation angles Setting...

Page 484: ...ress 270 Work area EPSON Work area start address 0 0 0 0 180 Work area Work area start address EPSON 3 1 2 VRAM Rotation Figure 27 The rotation angle is selected using VWIN_ROT 1 0 GE_ROTATE register 3 1 3 Angle of VRAM Rotation Table 27 VWIN_ROT 1 0 Rotation angle 0x3 270 0x2 180 0x1 90 0x0 0 Default 0x0 Changing this setting does not affect the contents of the work area To rotate the image accor...

Page 485: ...nable it in the drawing commands to perform clipping If the whole of an object image drawn by a command is located outside the clipping area when the clipping function is enabled a clipping area over error occurs an interrupt can be generated If only a part of an object image is beyond the clipping area the drawing within the clipping area is performed without an error Notes When configuring a cli...

Page 486: ...a Clipping area X1 Y1 0 0 Width X2 Y2 Y2 X2 X1 Y1 3 2 2 Straight Line Drawing Figure 27 Oblique lines with two pixels or more line width are drawn as follows 1 When 315 slope 45 135 slope 225 Both ends are drawn vertically 2 When 45 slope 135 225 slope 315 Both ends are drawn horizontally Width Width 45 slope 135 225 slope 315 315 slope 45 135 slope 225 3 2 3 Drawing Oblique Line Figure 27 When an...

Page 487: ...e line width can also be specified in number of pixels Work area Clipping area X1 Y1 0 0 Width X2 Y2 Y2 X2 X1 Y1 3 2 5 Drawing Rectangular Line Figure 27 The line drawing method for an even number of line width is the same as that of straight line drawing Solid filled rectangle drawing RECT_FILL command 0x17 Draws a solid filled rectangle specified with the X and Y coordinates of the upper left an...

Page 488: ...hree vertices and a color Work area Clipping area X1 Y1 0 0 X2 Y2 X3 Y3 Y2 Y3 X3 X2 X1 Y1 3 2 8 Drawing Solid Filled Triangle Figure 27 The X and Y coordinates of three vertices must be specified in a clockwise direction Circle Circle drawing CIRCLE command 0x1b Draws the circumference of a circle specified with the center coordinates radius and a line color The line width can be specified in numb...

Page 489: ...bytes 3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 2 bytes 3 0 or X bytes 1 optional n bytes 2 1 2 3 X index code size in bytes must be specified as the Font Index Offset parameter in the font configuration command Width 7 n int Height bytes 24 bytes in this example 8 Font base address is the start address of the first character data The font header is not started from the font...

Page 490: ...wing effects Work area Clipping area X1 Y1 0 0 X2 Y2 Y2 X2 Memory X1 Y1 Font set Index n Font data X2 Y2 X1 Y1 X2 Y2 X1 Y1 Normal X2 Y2 X1 Y1 Rotation Resizing X2 Y2 X1 Y1 Tiling 3 3 2 Character Drawing Figure 27 Decompression Copy Functions 27 3 4 The GE module supports functions to decompress compressed image data copy and transfer image data Decompression DECOMP command 0x22 Decompresses the co...

Page 491: ... and 2 to 4 bpp conversion data 1 bpp image data 6 byte 1 to 8 bpp 1 to 4 bpp and 1 to 2 bpp conversion data CCT 0 6 8 16 bytes Color depth size Byte 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 4 bpp 16 bytes 4 to 8 bpp table 2 bpp 8 bytes Image data 2 to 4 bpp table 2 to 8 bpp table 1 bpp 6 bytes Image data 1 to 2 bpp table 1 to 4 bpp table 1 to 8 bpp table None Image data 3 4 2 Image Data Format Figur...

Page 492: ... 0x302923 8 or 4 bit color data 3 0x302924 8 4 or 2 bit color data 0 0x302925 8 4 or 2 bit color data 1 CCT1 is located at 22 byte from address 0x302910 This table is used for converting color depth when the color conversion table in the header of the image data to be decompressed drawn is disabled bcTable 0 Conversion data must be written to the addresses shown above in advance Converting into 16...

Page 493: ...destination can also be specified Work area Clipping area X1 Y1 0 0 X2 Y2 X3 Y3 Y2 Y3 X3 X2 X1 Y1 Copy 3 4 5 Image Copy Figure 27 This copy function can guarantee that the source image will be copied to the destination properly even if the source and destination areas overlap one another Block transfer BLKCOPY command 0x2a Transfers image data block between a specified area within the work area an...

Page 494: ...d quadrilateral Circle Solid filled circle Character Decompression Copy Block transfer Can be specified Cannot be specified The block transfer command supports these effects only when data is transferred from a memory to VRAM These effect cannot be used when data is transferred from VRAM to a memory The following describes the drawing effects individually Clipping The clipping function can be enab...

Page 495: ...equired Writing effects When the GE writes object image data to the work area a writing effect can be applied to the data to be written The GE provides four effects listed in the table below and one of them can be selected 3 5 2 Writing Effect Selections Table 27 Write Effect Setting 2 0 bits Writing effect 0x7 0x4 Reserved 0x3 Rewrite 0x2 Mesh 0x1 XOR 0x0 Normal Fill The writing effect is applied...

Page 496: ... logi cal coordinates after VRAM rotation Work area 3 5 2 Mesh Effect Applied to Multiple Objects Figure 27 Rewrite Write Effect Setting 2 0 bits 0x3 Reads the work area data to be rewritten with the drawing command and performs color conversion via the palette selected by the Palette Select 1 0 bits Then writes the converted data back to the work area The palette only affects the color in the are...

Page 497: ...ch entry 16 bpp mode does not use Palette 1 even if it is specified Original color data 0 255 Converted color data 2 4 or 8 bit color conversion data 0 1 2 3 4 5 15 16 2 4 or 8 bit color conversion data 2 4 or 8 bit color conversion data 2 4 or 8 bit color conversion data 4 or 8 bit color conversion data 4 or 8 bit color conversion data 4 or 8 bit color conversion data 8 bit color conversion data ...

Page 498: ...d decompression commands allow specification of drawing areas different from the original size The Resize Tile Select 1 0 bits are used to select how the character image is drawn in this area 3 5 5 Resizing Tiling Selections Table 27 Resize Tile Select 1 0 bits Drawing effect 0x3 Reserved 0x2 Tiling 0x1 Resizing 0x0 Normal Normal The character image is drawn from origin in the original size Work a...

Page 499: ... image X1 Y1 X2 Y2 180 90 270 X1 Y1 X1 Y1 X1 Y1 X2 Y2 X2 Y2 X2 Y2 3 5 9 Character Image Rotation Figure 27 Transfer source destination The block transfer command allows selection of the source and destination for image data transfer using the Memory Select 1 0 bits This command performs drawing data block transfer between the specified area in the work area and memory or a built in RAM LCD driver ...

Page 500: ...GE_CCT1_1BIT registers 9 Set the command start address GE_CMD_ADDR register 10 Enable GE interrupts GE_IE register It is not necessary to set these registers if the functions are not used 3 Programming drawing commands Write the commands to be executed to the memory beginning with the command start address IVRAM Area 3 or an external memory located in Areas 13 to 22 can be used for executing drawi...

Page 501: ...tes the next command address that follows the command that has stopped execution except when stopped due to an unexpected operation Therefore writing 1 to GE_RUN resumes execution from that command However when an undefined command termination has occurred due to too many or less arguments the GE_ CMD_ADDR register may not point to the following command address Therefore be sure of the command sta...

Page 502: ..._UPDT_END registers will be cleared by writing any value Notes The coordinates of the updated area can be obtained in the following cases 1 At least one opaque dot of the specified object is located in the drawing area 2 As for a transparent object in the drawing area a copy command or a block transfer com mand is executed or the writing effect of rewrite or mesh specifies the transparent color Th...

Page 503: ...alculation error interrupts are enabled GE_ERR_IE1 1 Other calculation errors can always be detected regardless of the GE_ERR_IE1 setting 3 The image data in which an error occurs will be drawn with the last valid color Note Occurrence of a calculation error does not terminate command execution if calculation error inter rupts are disabled GE_ERR_IE1 0 Although the command in which an error has oc...

Page 504: ... reset via software The GE supports two reset meth ods hot reset and cold reset Hot reset Hot reset initializes the GE with the command and work area address information maintained The bus is relin quished Perform hot reset if a command execution is terminated due to an unexpected operation To perform hot reset write 1 to GE_HRST GE_CTL register GE_HRST retains 1 while the GE is placed into reset ...

Page 505: ...rupts are enabled GE_ERR_IE0 1 an interrupt request is sent simultaneously to the ITC An interrupt occurs if other interrupt conditions are met You can inspect DRAW_ERR 3 0 in the GE error interrupt handler routine to determine which drawing error occurred Calculation error interrupt To use this interrupt set GE_ERR_IE1 GE_IE register to 1 If GE_ERR_IE1 is set to 0 default interrupt re quests for ...

Page 506: ... CALC_ERR 3 0 0x3 has occurred while calculation error interrupts are enabled GE_ ERR_IE1 GE_IE register 1 b When a Decompress error CALC_ERR 3 0 0x8 has occurred and the data placed at the front of the invalid decompress flag 0x80 has not been written to the VRAM drawing on outside the work area clip area or draw ing with the transparent color No drawing error will occur when another calculation ...

Page 507: ...t configuration 0x20 0xffff Index Offset Font Size Text Color BG Color Font Set Base Address CHAR Character 0x21 0xffff Effect Setting Font Index Y1 X1 Y2 X2 DECOMP Decompression 0x22 0xffff Effect Setting reserved Start Address Y1 X1 Y2 X2 COPY Copy 0x29 0xffff Effect Setting reserved SRC Y1 SRC X1 SRC Y2 SRC X2 DST Y DST X BLKCOPY Block transfer 0x2a 0xffff Effect Setting reserved Address Y1 X1 ...

Page 508: ...e work area a calcula tion error will occur Clip area size must be equal to or less than that of the work area DOT Command Dot Drawing 27 5 5 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CMD 0x10 0xffff ARG1 Effect Setting Color reserved Clip Enable Transparent Enable Palette Select Sync Enable Write Effect Setting ARG2 Y Coordinate X Coordinate The DOT...

Page 509: ...effective bits depend on the GE bpp mode set using DISP_BPP 2 0 GE_DISP_CFG register 16 bpp mode Color 15 0 D 15 0 bits are effective 8 bpp mode Color 7 0 D 7 0 bits are effective 4 bpp mode Color 3 0 D 3 0 bits are effective 2 bpp mode Color 1 0 D 1 0 bits are effective 1 bpp mode Color0 D0 bit is effective The color data may be modified before being written to the work area according to the pale...

Page 510: ...le Bit Enables or disables the clipping function See Section 27 3 5 1 Clipping enabled 0 Clipping disabled D22 Transparent Enable Bit Enables or disables transparency See Section 27 3 5 1 Transparency enabled 0 Transparency disabled D 21 20 Palette Select 1 0 Bits Selects the palette to be used when converting colors with a palette See Section 27 3 5 5 6 1 Palette Selection Table 27 Palette Select...

Page 511: ... starting point D 31 16 Y1 Coordinate 15 0 Bits Specifies the Y coordinate of the starting point D 15 0 X1 Coordinate 15 0 Bits Specifies the X coordinate of the starting point Argument 4 Coordinates of endpoint D 31 16 Y2 Coordinate 15 0 Bits Specifies the Y coordinate of the endpoint D 15 0 X2 Coordinate 15 0 Bits Specifies the X coordinate of the endpoint Work area Clipping area X1 Y1 0 0 Width...

Page 512: ...ed D19 Sync Enable Bit Enables or disables the LCDC synchronization function See Section 27 3 5 1 Enabled Synchronized 0 Disabled Not synchronized D 18 16 Write Effect Setting 2 0 Bits Selects a writing effect See Section 27 3 5 5 7 2 Writing Effect Selections Table 27 Write Effect Setting 2 0 bits Writing effect 0x7 0x4 Reserved 0x3 Rewrite 0x2 Mesh 0x1 XOR 0x0 Normal Fill D 15 0 Color 15 0 Bits ...

Page 513: ...TRI_FILL Command Solid Filled Triangle Drawing 27 5 8 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CMD 0x16 0xffff ARG1 Effect Setting Color reserved Clip Enable Transparent Enable Palette Select Sync Enable Write Effect Setting ARG2 Y1 Coordinate X1 Coordinate ARG3 Y2 Coordinate X2 Coordinate ARG4 Y3 Coordinate X3 Coordinate The TRI_FILL command draws ...

Page 514: ...ode set using DISP_BPP 2 0 GE_DISP_CFG register 16 bpp mode Color 15 0 D 15 0 bits are effective 8 bpp mode Color 7 0 D 7 0 bits are effective 4 bpp mode Color 3 0 D 3 0 bits are effective 2 bpp mode Color 1 0 D 1 0 bits are effective 1 bpp mode Color0 D0 bit is effective The color data may be modified before being written to the work area according to the palette and or writing effect settings Se...

Page 515: ...0 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CMD 0x17 0xffff ARG1 Effect Setting Color reserved Clip Enable Transparent Enable Palette Select Sync Enable Write Effect Setting ARG2 Y1 Coordinate X1 Coordinate ARG3 Y2 Coordinate X2 Coordinate The RECT_FILL command draws a solid filled rectangle specified with the X and Y coordinates of the upper left and lower right corners and a color Argume...

Page 516: ...8 bpp mode Color 7 0 D 7 0 bits are effective 4 bpp mode Color 3 0 D 3 0 bits are effective 2 bpp mode Color 1 0 D 1 0 bits are effective 1 bpp mode Color0 D0 bit is effective The color data may be modified before being written to the work area according to the palette and or writing effect settings See Section 27 3 5 Argument 2 Coordinates of upper left corner D 31 16 Y1 Coordinate 15 0 Bits Spec...

Page 517: ...ee Section 27 3 5 1 Clipping enabled 0 Clipping disabled D22 Transparent Enable Bit Enables or disables transparency See Section 27 3 5 1 Transparency enabled 0 Transparency disabled D 21 20 Palette Select 1 0 Bits Selects the palette to be used when converting colors with a palette See Section 27 3 5 5 10 1 Palette Selection Table 27 Palette Select 1 0 bits Palette 0x3 Palette 3 0x2 Palette 2 0x1...

Page 518: ...15 0 Bits Specifies the X coordinate of the 3rd vertex Argument 5 Coordinates of 4th vertex D 31 16 Y4 Coordinate 15 0 Bits Specifies the Y coordinate of the 4th vertex D 15 0 X4 Coordinate 15 0 Bits Specifies the X coordinate of the 4th vertex Notes This command supports convex quadrilaterals only and does not draw concave quadrilaterals An error results and nothing will be drawn if a concave qua...

Page 519: ...all the 1 8 Position Select 7 0 bits to 1 b0 0x1 0x1 0x3 0x2 0xf 0x4 0x3f 0x8 0x11 0x10 0x33 0x20 0x55 0x40 0x6f 0x80 0xff b3 0x8 b7 0x80 b4 0x10 b1 0x2 b2 0x4 b6 0x40 b5 0x20 1 8 Position Select 7 0 Examples b7b6b5b4b3b2b1b0 5 11 1 Arc Selections Figure 27 Note When two or more arcs are drawn with separate commands the pixels at the boundary are overwritten This must be taken into consideration w...

Page 520: ...ective 4 bpp mode Color 3 0 D 3 0 bits are effective 2 bpp mode Color 1 0 D 1 0 bits are effective 1 bpp mode Color0 D0 bit is effective The color data may be modified before being written to the work area according to the palette and or writing effect settings See Section 27 3 5 Argument 2 Line width and radius D 31 28 Reserved D 27 16 Line Width 11 0 Bits Specifies the line width in number of pi...

Page 521: ... bits to 1 0x1 0x3 0x2 0xf 0x4 0x3f 0x8 0x11 0x10 0x33 0x20 0x55 0x40 0x6f 0x80 0xff b0 0x1 b3 0x8 b7 0x80 b4 0x10 b1 0x2 b2 0x4 b6 0x40 b5 0x20 1 8 Position Select 7 0 Examples b7b6b5b4b3b2b1b0 5 12 1 Circular Section Selections Figure 27 Note When two or more circular sections are drawn with separate commands the pixels at the boundary are overwritten This must be taken into consideration when u...

Page 522: ...effective 1 bpp mode Color0 D0 bit is effective The color data may be modified before being written to the work area according to the palette and or writing effect settings See Section 27 3 5 Argument 2 Radius D 31 12 Reserved D 11 0 Radius 11 0 Bits Specifies the radius in number of pixels Argument 3 Coordinates of center D 31 16 Y Coordinate 15 0 Bits Specifies the Y coordinate of the center D 1...

Page 523: ...PP 2 0 GE_DISP_CFG register 16 bpp mode Character Background Color 15 0 D 31 16 D 15 0 bits are effective 8 bpp mode Character Background Color 7 0 D 23 16 D 7 0 bits are effective 4 bpp mode Character Background Color 3 0 D 19 16 D 3 0 bits are effective 2 bpp mode Character Background Color 1 0 D 17 16 D 1 0 bits are effective 1 bpp mode Character Background Color0 D16 D0 bit is effective The co...

Page 524: ...ransparent Enable Bit Enables or disables transparency See Section 27 3 5 1 Transparency enabled 0 Transparency disabled D 21 20 Palette Select 1 0 Bits Selects the palette to be used when converting colors with a palette See Section 27 3 5 5 14 3 Palette Selection Table 27 Palette Select 1 0 bits Palette 0x3 Palette 3 0x2 Palette 2 0x1 Palette 1 0x0 Not used D19 Sync Enable Bit Enables or disable...

Page 525: ...14 1 Character Drawing Figure 27 DECOMP Command Decompression and Drawing 27 5 15 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CMD 0x22 0xffff ARG1 Effect Setting reserved reserved Resize Tile Select reserved Rotation Select Clip Enable Transparent Enable Palette Select Sync Enable Write Effect Setting ARG2 Start Address ARG3 Y1 Coordinate X1 Coordinate...

Page 526: ...180 0x1 90 0x0 0 D23 Clip Enable Bit Enables or disables the clipping function See Section 27 3 5 1 Clipping enabled 0 Clipping disabled D22 Transparent Enable Bit Enables or disables transparency See Section 27 3 5 1 Transparency enabled 0 Transparency disabled D 21 20 Palette Select 1 0 Bits Selects the palette to be used when converting colors with a palette See Section 27 3 5 5 15 3 Palette Se...

Page 527: ...gnored Work area Clipping area X1 Y1 0 0 X2 Y2 Y2 X2 Memory X1 Y1 Image data X2 Y2 X1 Y1 X2 Y2 X1 Y1 Normal X2 Y2 X1 Y1 Rotation Resizing X1 Y1 Tiling X2 Y2 5 15 1 Decompression and Drawing Figure 27 COPY Command Copy 27 5 16 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CMD 0x29 0xffff ARG1 Effect Setting reserved reserved Clip Enable Transparent Enable...

Page 528: ...ing 2 0 Bits Selects a writing effect See Section 27 3 5 5 16 2 Writing Effect Selections Table 27 Write Effect Setting 2 0 bits Writing effect 0x7 0x3 Reserved 0x2 Mesh 0x1 XOR 0x0 Normal Fill D 15 0 Reserved Argument 2 Coordinates of transfer source area upper left corner D 31 16 Source Y1 Coordinate 15 0 Bits Specifies the Y coordinate of the transfer source area upper left corner D 15 0 Source...

Page 529: ...and transfers image data block between a specified area within the work area and memory or a built in RAM LCD driver via USIL The source and destination can be selected from four combinations in a command argument Drawing effects such as palette conversion can be specified when sending data to the work area Argument 1 Drawing effects D 31 28 Reserved D 27 26 Memory Select 1 0 Bits Selects the tran...

Page 530: ... work area See Section 27 3 5 5 17 3 Writing Effect Selections Table 27 Write Effect Setting 2 0 bits Writing effect 0x7 0x3 Reserved 0x2 Mesh 0x1 XOR 0x0 Normal Fill Note The Writing effects are effective only when data is transferred to the work area D 15 0 Reserved Argument 2 Memory address D 31 0 Address 31 0 Bits Specifies the transfer source destination memory address or the USIL transmit da...

Page 531: ..._MESH Mesh Configuration Register Configure mesh size and color 0x30246c GE_MAGIC Transparent Color Register Specify transparent color 0x302470 GE_UPDT_ST Updated Area Start Position Register Indicate upper left corner of updated area 0x302474 GE_UPDT_END Updated Area End Position Register Indicate lower right corner of updated area 0x302800 0x3028ff GE_PALETTE1 Palette 1 Palette 1 0x302910 0x3029...

Page 532: ...GE_STS is the result of OR between BUS_STS CALC_STS and DRAW_STS GE_RUN GE_STS End of execution interrupt 3 GCLK cycles Possible to restart running 6 1 GE_STS Set Timing Figure 27 D 15 11 Reserved D10 BUS_STS Bus Operation Status Bit Indicates the GE bus operation status 1 R Running 0 R Stopped default BUS_STS indicates the GE bus operation status It is set to 1 while the GE is fetching a command ...

Page 533: ...after a hot reset Font font configuration command Clipping area GE_CLIP_ST and GE_CLIP_END registers D0 GE_CRST GE Cold Reset Control Bit Cold resets the GE 1 R W Cold reset default 0 R W Normal mode Cold reset initializes the GE completely To perform cold reset write 1 to GE_CRST The reset state must be canceled by writing 0 to GE_ CRST If the initialization has not finished yet at this time GE_C...

Page 534: ...0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 reserved Decompress Picture header Font size Radius Circle location Concave Coordinates Trace width No error D 7 4 Reserved D 3 0 CALC_ERR 3 0 Calculation Error Status Bits Indicates whether an error has occurred in the calculation stage or not 6 2 List of Calculation Errors Table 27 CALC_ERR 3 0 Error 0xf to 0x9 Reserved 0x8 Decompress A Decompress flag 0x80 exists...

Page 535: ..._IE1 1 occurrence of an error ter minates command execution In this case no end of execution interrupt will occur GE Interrupt Flag Register 2 GE_IF2 Register name Address Bit Name Function Setting Init R W Remarks GE Interrupt Flag Register 2 GE_IF2 0x302449 8 bits D7 4 reserved 0 when being read D3 DRAW_ ERR3 No VRAM write error flag 1 Occurred 0 Not occurred 0 R W Reset by writing 1 D2 DRAW_ ER...

Page 536: ... object image drawn by a command with clipping area en abled is located outside the clipping area If a part of an object image is beyond the clipping area the drawing within the clipping area is performed without an error When DRAW_ERR1 is set to 1 a drawing error interrupt request is output to the ITC if GE_ERR_IE0 has been set to 1 interrupt enabled An interrupt is generated if the ITC and C33 P...

Page 537: ...t terminated Default 0x0 When a bit in EXE_END 2 0 is set an end of execution interrupt request is output to the ITC if GE_ END_IE GE_IE register has been set to 1 interrupt enabled An interrupt is generated if the ITC and C33 PE Core interrupt conditions are satisfied EXE_END 2 0 is cleared to 0x0 by writing 0x0 or 0xff to address 0x30244a VRAM Work Area Width Register GE_REAL_W Register name Add...

Page 538: ...rmore when the work area is rotated its width and height must be reset according to the rotation angle Therefore VWIN_W 11 0 and VWIN_H 11 0 should be set after setting the bpp mode and the angle of work area rotation 6 4 Work Area Size Specifications Table 27 bpp mode VWIN_W 11 0 VWIN_H 11 0 1 bpp int Width 31 32 32 1 Height 1 2 bpp int Width 15 16 16 1 Height 1 4 bpp int Width 7 8 8 1 Height 1 8...

Page 539: ...D1 D0 16 bpp R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0 R4 R3 R2 G5 G4 G3 B4 B3 In this mode GE cannot draw anything as RGB data is regarded as 3 pixel data not for 1 pixel However the BLKCOPY command can be executed normally A 5 bpp LCD panel with SPI parallel I F can be used via USIL by setting TF_TYPE to 1 Pixel to Byte and the color depth to 1 to 8 bpp D 15 5 Reserved D4 SYNC_TYPE LCDC Ho...

Page 540: ...302460 32 bits D31 28 reserved 0 when being read D27 16 CLIP_UPL_ Y 11 0 Clipping area upper left corner Y coordinate 0 to 4 095 0x0 R W D15 12 reserved 0 when being read D11 0 CLIP_UPL_ X 11 0 Clipping area upper left corner X coordinate 0 to 4 095 0x0 R W D 31 28 Reserved D 27 16 CLIP_UPL_Y 11 0 Clipping Area Upper Left Corner Y Coordinate Bits Specifies the Y coordinate value of the clipping ar...

Page 541: ... 16 CLIP_LWR_Y 11 0 Clipping Area Lower Right Corner Y Coordinate Bits Specifies the Y coordinate value of the clipping area lower right corner Default 0x0 D 15 12 Reserved D 11 0 CLIP_LWR_X 11 0 Clipping Area Lower Right Corner X Coordinate Bits Specifies the X coordinate value of the clipping area lower right corner Default 0x0 Mesh Configuration Register GE_MESH Register name Address Bit Name F...

Page 542: ...cifies the transparent color Default 0x0 A color within the effective range for the bpp mode set using DISP_BPP 2 0 GE_DISP_CFG register can only be specified When transparency is enabled in a drawing command the pixels with the transparent color specified in objects images are not drawn on the work area and the current pixel color is left unchanged Updated Area Start Position Register GE_UPDT_ST ...

Page 543: ...ordinate 0 to 4 095 0x0 R W Cleared by writing any data D15 12 reserved 0 when being read D11 0 UPDT_LWR _X 11 0 Updated area lower right corner X coordinate 0 to 4 095 0x0 R W Cleared by writing any data D 31 28 Reserved D 27 16 UPDT_LWR_Y 11 0 Updated Area Lower Right Corner Y Coordinate Bits Indicates the Y coordinate value of the updated area lower right corner Default 0x0 D 15 12 Reserved D 1...

Page 544: ...es GE_CCT1_ 2BIT 0x302920 0x302923 8 bits D7 0 CCT1 data User defined 2 to 4 8 bpp con version data 0x0 to 0xff X R W Write 2 to 4 or 8 bpp conversion data to the 4 bytes of CCT1 from address 0x302920 to address 0x302923 CCT1 1 bit Entries GE_CCT1_1BIT Register name Address Bit Name Function Setting Init R W Remarks CCT1 1 bit Entries GE_CCT1_ 1BIT 0x302924 0x302925 8 bits D7 0 CCT1 data User defi...

Page 545: ... MHz clock Supports snooze mode Figure 28 1 1 shows the block diagram of the USB function controller USBDM USBDP Bridge USB Part To DMAC PDREQ PDACK PDWR PDRD 1 1 1 1 Snooze Reset USBVBUS FIFO 1KB Decoder FIFO Controller SIE Port Interface Controller CPU Interface Controller Test MUX USBIO 1 The PDREQ PDACK PDWR and PDRD signals level must be configured as Active High ADD 5 0 CE6 RD WRL INT_USB IN...

Page 546: ...d Clock management unit CMU Control the clock supply to the USB function controller Misc register MISC Set the number of wait cycles to be inserted when the USB control register is accessed Enable or disable the snooze control by the USB function controller Enable or disable the USB interrupts Interrupt controller ITC Set the USB interrupt level DMA controller DMAC Program the control table for th...

Page 547: ...set in the EP0MaxSize register starting with FIFO address 0 Table 28 5 1 2 lists the basic setting items for the general purpose endpoints EPa EPb EPc and EPd The EPa EPb EPc and EPd endpoints allow optional settings for the transaction directions and the endpoint num bers which allows up to four discrete endpoints to be used Set up and or enable these endpoints as appropriate according to the def...

Page 548: ...or vacancies in the FIFO region STALL response EP0ControlIN ForceSTALL EP0ControlOUT ForceSTALL Returns a STALL response to IN or OUT transactions Set automatic ForceNAK EP0ControlOUT AutoForceNAK Sets the EP0ControlOUT ForceNAK bit whenever an OUT transaction is completed SETUP reception status MainIntStat RcvEP0SETUP Indicates that a SETUP transaction is executed Transaction status EP0IntStat IN...

Page 549: ... size since it can read the FIFO data via the Port interface for example and receive data while creat ing an available space concurrently After all data are successfully received in an OUT transaction the transaction is closed and an ACK re sponse is returned In addition the firmware receives an OUT_TranACK status of the relevant endpoint EPx x 0 a b c d IntStat OUT_TranACK bit Furthermore the FIF...

Page 550: ... d IntStat IN_TranErr bit Accordingly the FIFO is not updated or no space is freed In on an IN endpoint if no maximum packet size data exist in the FIFO and no permission is granted for short packet transmission the IN transaction receives a NAK response and an IN_TranNAK status EPx x 0 a b c d IntStat IN_TranNAK bit is issued to the firmware Accordingly the FIFO is not updated or no space is free...

Page 551: ...y OUT and IN transactions flow control using NAK responses works effectively The device is allowed to prepare for returning responses within a specified time frame SETUP stage The macro automatically executes a SETUP transaction upon reception of a SETUP token addressed to its own node Have your firmware monitor a RcvEP0SETUP status and analyze the request referring to the EP0Setup_0 through EP0Se...

Page 552: ...The descriptor return function executes IN transactions by returning data packets in response to IN transac tions until it finishes sending all of a specified number of data If a fractional number of data exist against the maximum packet size the descriptor return function sets EP0ControlIN EnShortPkt enabling response to IN transactions until the entire data return is completed After returning al...

Page 553: ...lank Although the Port interface is invoked no transfer is performed since the FIFO is blank The PDREQ signal is negated F2 An OUT transaction is developing and data reception has started in the FIFO At this point the FIFO data is not considered to be valid since the transaction is not closed F3 Although data packet reception is completed from the OUT transaction the FIFO data is not consid ered t...

Page 554: ...rt interface is completed Using this function provides auto matic control to the end that only a non zero length short packet is returned eliminating return of a zero length data packet Figure 28 5 1 7 illustrates the data flow in IN transfer The FIFO region for an IN endpoint is connected to the Port interface Also the FIFO region assigned to this endpoint is assumed to be twice as large as the m...

Page 555: ...unction This function automatically performs Suspend detection Reset detection and Resume detection checking the state of the USB bus for each operation You can check each interruption DetectReset and DetectSuspend to confirm what has been actually performed DISABLE EnAutoNego 1 irq_DetectSuspend InSUSPEND 0 irq_DetectReset irq_NonJ 1 NORMAL state RESET state SUSPEND state RESUME state NORMAL irq_...

Page 556: ...aring the current consumption reducing function At this time in order to detect Resume FS K that indicates the end of Suspend set the SIE_IntEnb En NonJ bit in the firmware when the macro enters this state to give permission to NonJ interruption When NonJ interruption status SIE_IntStat NonJ is set it is interpreted as an indication of return from Suspend and the macro enters the CHK_EVENT state a...

Page 557: ...etect bit to 1 time DetectReset DisBusDetect LineState 1 0 USBDP USBDM T 1 T0 T1 T2 Last Activity J State J State Driven SE0 SE0 5 1 10 Reset Timing FS mode Figure 28 Issuing resume This section describes how to enable automatic resume to be triggered by some cause when remote wakeup is supported and the remote wakeup function is enabled from the host Remote wakeup can only be enabled 5 ms after t...

Page 558: ...USB_Status LineState 1 0 is J If K is ob served on the bus it means the instruction for wakeup Resume is received from the downstream port This section describes the operation when Resume is detected assuming that this macro is in the Snooze state when the USB is suspended Use the firmware that controls this macro to perform steps 4 5 5a and 9 The other steps are handled by the macro hardware auto...

Page 559: ... DisBusDetect OpMode 1 0 LineState 1 0 USBDP USBDM Internal clock time VBUS Upstream Port Actions Device Actions T0 T4 T1 T2 T3 0x0 Normal Mode Fully meet USB2 0 required frequency J State FS Idle J State SE1 SE0 SE0 SE0 CLK Powerup time 5 1 11 Device Attach Timing Figure 28 5 1 5 Device Attach Timing Values Table 28 Timing parameter Description Value T0 VBUS is enabled 0 Reference T1 Set USBCLK_E...

Page 560: ...ess set in the EPbStartAdrs register The EPb area extends from the address set in the EPbStartAdrs register up to the point before the address set in the EPcStartAdrs register The EPd area extends from the address set in the EPdStartAdrs register up to the end of FIFO RAM The addresses available in the area setup registers must be written in the unit of four bytes meaning that the lowest two bits ...

Page 561: ... data to be transmitted to the data stage set the data size specified in the request in the DescSize_H and DescSize_L registers and then set the EP0Control ReplyDescriptor bit to 1 After receiving the IN token from the host the macro start transmitting data to the host automatically split ting them into the maximum packet size set in the EP0MaxSize In addition if the value in the DescSize_ H or De...

Page 562: ... guarantee normal operations if the basic setting registers are modified while the DMA in transferring data 5 3 1 Port Interface s Registers for Basic Setting Items Table 28 Item Register bit Description Endpoint connection DMA_Join JoinEPr r a b c d DMA Connects the Port interface to the endpoint of the bit set to 1 Writing reading is enabled to from the connected endpoint Counter setting DMA_Cou...

Page 563: ... with DMA_Config_1 CountMode 1 the DMA completes data transfer when the DMA_Count_HH HL LH and LL registers reach 0x00000000 To cancel negate the DMA request PDREQ provide 1 to the DMA_Control DMA_Stop bit Note that writing 1 to the DMA_ Control DMA_Stop bit does not stop the DMAC So to terminate data transfer first terminate the DMAC master and then terminate the macro s DMA transfer Note The S1C...

Page 564: ...ritten on the DMA_Control DMA_Go bit After data transfer starts on the DMA the USB macro requests data transfer by asserting PDREQ if any data exist at the connected endpoint Turning PDACK to active starts outputting transferred data to the data bus Have the DMAC master load the data while PDRD is rising when the DMA_Config_0 PDRDWR_ Level bit is set to 1 When no data remains at the endpoint the i...

Page 565: ...sserted and data transfer is rejected If any data is set to the DMA_Latency DMA_Latency 3 0 bit other than 0x0 this mode negates PDREQ once after completing transfer of 4 byte data and does not assert PDREQ as long as 130 ns N N DMA_Latency DMA_Latency 3 0 If the DMA is set to the Countdown mode with DMA_Config_1 CountMode 1 the DMA completes data transfer when the DMA_Count_HH HL LH and LL regist...

Page 566: ...each 0x00000000 To cancel negate the DMA request PDREQ provide 1 to the DMA_Control DMA_Stop bit Note that writing 1 to the DMA_ Control DMA_Stop bit does not stop the DMAC So to terminate data transfer first terminate the DMAC master and then terminate the macro s DMA transfer Note The S1C33L26 DMAC can only be triggered to start data transfer by the Rising Edge of PDREQ The subsequent DMAC trigg...

Page 567: ...tection for the Misc registers 5 Set USBSNZ in the MISC_USB register to disable the snooze control 6 Write a value other than 0x96 to the MISC_PROTECT register to enable write protection for the Misc reg isters Registers 28 6 List of Registers 28 6 1 Italic bold represents readable writable registers in SNOOZE SLEEP mode Address Register name R W Init D7 D6 D5 D4 D3 D2 D1 D0 0x300c00 MainIntStat R...

Page 568: ...Test Test_SE0_NAK Test_J Test_K Test_Packet 0x300c25 EPnControl W 0x00 AllForceNAK EPrForceSTALL AllFIFO_Clr EP0FIFO_Clr 0x300c26 EPrFIFO_Clr W 0x00 EPdFIFO_Clr EPcFIFO_Clr EPbFIFO_Clr EPaFIFO_Clr 0x300c27 0x300c28 0x300c29 0x300c2a 0x300c2b 0x300c2c 0x300c2d 0x300c2e FrameNumber_H R 0x80 FnInvalid FrameNumber 10 8 0x300c2f FrameNumber_L R 0x00 FrameNumber 7 0 Address Register name R W Init D7 D6 ...

Page 569: ...8 0x300c77 EPdStartAdrs_L R W 0x00 EPdStartAdrs 7 2 0x300c78 0x300c79 0x300c7a 0x300c7b 0x300c7c 0x300c7d 0x300c7e 0x300c7f Address Register name R W Init D7 D6 D5 D4 D3 D2 D1 D0 0x300c80 CPU_JoinRd R W 0x00 JoinEPdRd JoinEPcRd JoinEPbRd JoinEPaRd 0x300c81 CPU_JoinWr R W 0x00 JoinEPdWr JoinEPcWr JoinEPbWr JoinEPaWr 0x300c82 EnEPnFIFO_Access R W 0x00 EnEPnFIFO_Wr EnEPnFIFO_Rd 0x300c83 EPnFIFOforCPU...

Page 570: ...ption of the CPU Clearing all relevant causes of interrupt negates the INT signal D7 SIE_IntStat Shows a cause of interrupt indirectly When the SIE_IntStat register has a cause of interrupt and the SIE_IntEnb register bit corresponding to the cause of interrupt is enabled this bit is set to 1 Reading this bit is valid during snooze as well D6 EPrIntStat Shows a cause of interrupt indirectly When t...

Page 571: ...etectReset Shows a cause of interrupt directly Set to 1 when the reset state of the USB is detected This reset detection is valid when the ActiveUSB bit of the USB_Control register is set to 1 When the AutoNegotiation function is not used if this bit is set to 1 set to the DisBusDetect bit of the USB_Control register to 1 not to detect the succeeding reset wrongly by disabling detection of the re ...

Page 572: ...cause of interrupt indirectly When the EPaIntStat register has a cause of interrupt and the EPaIntEnb register bit corresponding to the cause of interrupt is enabled this bit is set to 1 DMA_IntStat DMA Interrupt Status Register name Address Bit Name Setting Init R W Remarks DMA_IntStat DMA interrupt status 0x300c03 8 bits D7 2 0 when being read D1 DMA_CountUp 1 DMA counter overflow 0 None 0 R W D...

Page 573: ...it Name Setting Init R W Remarks EP0IntStat EP0 interrupt status 0x300c07 8 bits D7 6 0 when being read D5 IN_TranACK 1 In transaction ACK 0 None 0 R W D4 OUT_TranACK 1 Out transaction ACK 0 None 0 R W D3 IN_TranNAK 1 In transaction NAK 0 None 0 R W D2 OUT_TranNAK 1 Out transaction NAK 0 None 0 R W D1 IN_TranErr 1 In transaction error 0 None 0 R W D0 OUT_TranErr 1 Out transaction error 0 None 0 R ...

Page 574: ... a cause of interrupt directly Set to 1 when NAK is replied in the IN transaction D2 OUT_TranNAK Shows a cause of interrupt directly Set to 1 when NAK is replied in the OUT transaction D1 IN_TranErr Shows a cause of interrupt directly Set to 1 when STALL is replied in the IN transaction when an error occurred in the packet or when the handshake is failed in Time Out D0 OUT_TranErr Shows a cause of...

Page 575: ...interrupt status 0x300c0a 8 bits D7 0 when being read D6 OUT_ShortACK 1 Out short packet ACK 0 None 0 R W D5 IN_TranACK 1 In transaction ACK 0 None 0 R W D4 OUT_TranACK 1 Out transaction ACK 0 None 0 R W D3 IN_TranNAK 1 In transaction NAK 0 None 0 R W D2 OUT_TranNAK 1 Out transaction NAK 0 None 0 R W D1 IN_TranErr 1 In transaction error 0 None 0 R W D0 OUT_TranErr 1 Out transaction error 0 None 0 ...

Page 576: ...o 1 at the same time D5 IN_TranACK Shows a cause of interrupt directly Set to 1 when ACK is received in the IN transaction D4 OUT_TranACK Shows a cause of interrupt directly Set to 1 when ACK is replied in the OUT transaction D3 IN_TranNAK Shows a cause of interrupt directly Set to 1 when NAK is replied in the IN transaction D2 OUT_TranNAK Shows a cause of interrupt directly Set to 1 when NAK is r...

Page 577: ...er DMA_IntEnb DMA Interrupt Enable Register name Address Bit Name Setting Init R W Remarks DMA_IntEnb DMA interrupt enable 0x300c13 8 bits D7 2 0 when being read D1 EnDMA_CountUp 1 Enable 0 Disable 0 R W D0 EnDMA_Cmp 0 R W This register enables disables assertion of the DMA_IntStat bit of the MainIntStat register with the cause of inter rupt of the DMA_IntStat register FIFO_IntEnb FIFO Interrupt E...

Page 578: ...cIntEnb EPc Interrupt Enable Register name Address Bit Name Setting Init R W Remarks EPcIntEnb EPc interrupt enable 0x300c1a 8 bits D7 0 when being read D6 EnOUT_ShortACK 1 Enable 0 Disable 0 R W D5 EnIN_TranACK 0 R W D4 EnOUT_TranACK 0 R W D3 EnIN_TranNAK 0 R W D2 EnOUT_TranNAK 0 R W D1 EnIN_TranErr 0 R W D0 EnOUT_TranErr 0 R W This register enables disables assertion of the EPcIntStat bit of the...

Page 579: ...ork se quence to be done after detecting the reset from the end of the speed negotiation to determination of the speed mode Refer to the section describing operations for details of the Auto Negotiation D5 InSUSPEND This bit enables the detection of the NonJ state If the USB suspend state is detected and f w is pre pared set this bit to 1 To return from the suspended state set this bit to 0 to be ...

Page 580: ...erved D 1 0 OpMode This bit sets the operation mode of the Transceiver macro This bit needs not be set up normally excluding when the USB cable is pulled off and during the test mode OpMode OpMode 1 0 Operation mode 0x3 Reserved 0x2 Disable bitstuffing and NRZI encoding 0x1 Non driving 0x0 Normal operation When the USB cable is pulled off it is recommended to set this register to 0x1 USB_Test USB ...

Page 581: ...ake the endpoint be ready to use And allocate the FIFO of the end point EPc for 64 bytes or more 2 Do not overlap the above setting with the settings of the endpoints EPa and EPb Or clear the EPaConfig_0 EnEndPoint bit and EPbConfig_0 EnEndPoint bit 3 Clear the FIFO of the EPc and write data for the following test packet into this FIFO 4 Set the EnIN_TranErr of the EPcIntEnb register to 0 clear th...

Page 582: ...int EPd is connected to the general port the JoinEPdDMA bit of the DMA_Join register is set to 1 and the start operation of the general port is being done when the DMA_Running bit of the DMA_Control register is 1 Otherwise a malfunction may occur D2 EPcFIFO_Clr Clears the FIFO of the endpoint EPc This bit is automatically set 0 to be cleared after completing the FIFO clear operation Do not set thi...

Page 583: ... LOW Register name Address Bit Name Setting Init R W Remarks FrameNumber _L Frame number low 0x300c2f 8 bits D7 0 FrameNumber 7 0 Frame number low 0x0 R D 7 0 FrameNumber 7 0 The lower order 8 bits in the FrameNumber field of the received SOF packet are stored in these bits EP0Setup_0 EP0 Setup 0 EP0Setup_7 EP0 Setup 7 Register name Address Bit Name Setting Init R W Remarks EP0Setup_0 EP0 setup 0 ...

Page 584: ...thing 0 W This register sets up the endpoint EP0 D7 INxOUT Sets the transfer direction of the endpoint EP0 Judging from the request received at the setup stage set a value in this bit If the data stage exists set the transfer direction at the data stage into this bit As the setup of the ForceNAK bits of the EP0ControlIN and EP0ControlOUT registers completes when the setup stage completes clear the...

Page 585: ... is transmitted this bit is not cleared If this bit is set to 1 when the FIFO has no data a zero length packet can be transmitted for the IN token from the host If the data is written into the FIFO that is in the transmission process with the packet to which this bit is set that data may be included in transmission Therefore do not write into the FIFO until the packet transmission completes and th...

Page 586: ...nse is done for the OUT transaction of the endpoint EP0 regardless of the FIFO space capacity When the RcvEP0SETUP bit of the MainIntStat register is set to 1 after completion of the setup stage this bit is set to 1 and this bit cannot be set to 0 to be cleared as long as the RcvEP0SETUP bit is 1 When a transaction has been being done for a certain period of time the setting of this bit will be en...

Page 587: ...gth packet can be transmitted for the IN token from the host If the data is written into the FIFO that is in the transmission process with the packet to which this bit is set that data may be included in transmission Therefore do not write into the FIFO until the packet transmission completes and this bit is cleared D5 DisAF_NAK_Short When this bit is set to 0 default setting and the packet that w...

Page 588: ...ssion completes and this bit is cleared D5 DisAF_NAK_Short When this bit is set to 0 default setting and the packet that was received at normal completion time of the OUT transaction is a short packet the ForceNAK bit is automatically set to 1 When this bit is set to 1 this function is disabled When the AutoForceNAK bit is set to 1 the AutoForceNAK bit has a priority D4 ToggleStat Shows the status...

Page 589: ...riority D4 ToggleStat Shows the status of the toggle sequence bit of the endpoint EPc D3 ToggleSet Sets the toggle sequence bit of the endpoint EPc to 1 D2 ToggleClr Sets the toggle sequence bit of the endpoint EPc to 0 to be cleared D1 ForceNAK If this bit is set to 1 the NAK response is done for the transaction of the endpoint EPc regardless of the FIFO data quantity and space capacity When a tr...

Page 590: ...dpoint EPd D3 ToggleSet Sets the toggle sequence bit of the endpoint EPd to 1 D2 ToggleClr Sets the toggle sequence bit of the endpoint EPd to 0 to be cleared D1 ForceNAK If this bit is set to 1 the NAK response is done for the transaction of the endpoint EPd regardless of the FIFO data quantity and space capacity When a transaction has been being done for a certain period of time the setting of t...

Page 591: ...ted Perform the setup according to the SetConfiguration request from the host D4 Reserved D 3 0 EndPointNumber 3 0 Sets an endpoint number between 0x1 and 0xf EPaConfig_1 EPa Configuration 1 Register name Address Bit Name Setting Init R W Remarks EPaConfig_1 EPa configuration 1 0x300c53 8 bits D7 ISO 1 ISO 0 Non ISO 0 R W D6 ISO_CRCmode 1 CRC mode 0 Normal ISO 0 R W D5 0 0 when being read This reg...

Page 592: ... of the endpoint D6 ToggleMode Sets the operation mode of the toggle sequence bit Only for the IN transaction Normal toggle Perform the toggle only when the transaction ends normally Always toggle Always perform the toggle for every transaction D5 EnEndPoint Setting this bit to 1 enables this endpoint When this bit is 0 access to an endpoint is neglected Perform the setup according to the SetConfi...

Page 593: ...0 Disable endpoint 0 R W D4 0 when being read D3 0 EndPointNumber 3 0 Endpoint number 0x1 to 0xf 0x0 R W This register sets up the endpoint EPc Perform the setup so that combination of the EndpointNumber and the INxOUT does not overlap with those of other endpoints D7 INxOUT Sets the transfer direction of the endpoint D6 ToggleMode Sets the operation mode of the toggle sequence bit Only for the IN...

Page 594: ...Bit Name Setting Init R W Remarks EPdConfig_0 EPd configuration 0 0x300c5e 8 bits D7 INxOUT 1 In 0 Out 0 R W D6 ToggleMode 1 Always toggle 0 Normal toggle 0 R W D5 EnEndPoint 1 Enable endpoint 0 Disable endpoint 0 R W D4 0 when being read D3 0 EndPointNumber 3 0 Endpoint number 0x1 to 0xf 0x0 R W This register sets up the endpoint EPd Perform the setup so that combination of the EndpointNumber and...

Page 595: ...acro does not op erate normally Set the total of the FIFO area secured for all endpoints does not exceed the total capacity of the built in RAM Allocate the FIFO area to the endpoints in the order from the lower order address to higher order ad dress like EP0 EPa EPb EPc EPd The FIFO of the endpoint EP0 is allocated from the address 0 to up to the size specified as the Max PacketSize of the endpoi...

Page 596: ...PnControl regis ter to 1 to clear all FIFOs If the EPcMaxSize of the endpoint EPc is larger than the area specified in here the macro does not op erate normally Set the total of the FIFO area secured for all endpoints does not exceed the total capacity of the built in RAM Allocate the FIFO area to the endpoints in the order from the lower order address to higher order ad dress like EP0 EPa EPb EPc...

Page 597: ... CPU I F through the endpoint used by USB I F or DMA I F is not allowed If CPU I F needs to read from the IN direction endpoint use the ForceNAK bit to avoid reading data from USB I F If CPU I F needs to read from the OUT direction endpoint check the DMA_Running bit of the DMA_Control reg ister to avoid reading data from DMA I F at the same time This register is valid when EnEPnFIFO_Access EnEPnFI...

Page 598: ... addition reference to the space capacity in the FIFO of the endpoint EPc by the EPnWrRemain_H L register is enabled D1 JoinEPbWr If this bit is set to 1 the FIFO data of the endpoint EPb can be written into the EPnFIFOforCPU regis ter In addition reference to the space capacity in the FIFO of the endpoint EPb by the EPnWrRemain_H L register is enabled D0 JoinEPaWr If this bit is set to 1 the FIFO...

Page 599: ...main 0x0 R EPnRdRemain 11 0 This register shows the remained data quantity in the FIFO of the endpoint connected to the CPU Interface by the CPU_JoinRd register When the remained data quantity in the FIFO is acquired the EPnRdRemain_H and the EPnRdRemain_L registers must be accessed as a pair When accessing them access the EPnRdRemain_H register first EPnWrRemain_H EPn FIFO Write Remain HIGH EPnWr...

Page 600: ...00c8b 8 bits D7 0 DescSize 7 0 Descriptor size 0x0 R W DescSize 9 0 Specifies the total number of the data to reply in Descriptor reply function for the Descriptor Size Re fer to the item on the ReplyDescriptor bit of the EP0Control register for the Descriptor reply function The area ranging from 0x0000 to 0x03ff can be specified for the Descriptor Size regardless of the FIFO area setting In the D...

Page 601: ...oin EPd to DMA 0 Do nothing 0 R W D2 JoinEPcDMA 1 Join EPc to DMA 0 Do nothing 0 R W D1 JoinEPbDMA 1 Join EPb to DMA 0 Do nothing 0 R W D0 JoinEPaDMA 1 Join EPa to DMA 0 Do nothing 0 R W The endpoint to perform the DMA transfer can be specified by setting the JoinEPd aDMA bits After setting these bits the remained data quantity for the endpoint of the OUT direction or the space capacity for endpoi...

Page 602: ...name Address Bit Name Setting Init R W Remarks DMA_Config_0 DMA configuration 0 0x300c94 8 bits D7 ActivePort 1 Activate DMA port 0 Deactivate DMA port 0 R W D6 4 0 when being read D3 PDREQ_Level 1 Active low 0 Active high 0 R W D2 PDACK_Level 1 Active low 0 Active high 0 R W D1 PDRDWR_Level 1 Active low 0 Active high 0 R W D0 0 when being read This register sets fields on the bus of the DMA inter...

Page 603: ...properly D 6 4 Reserved D3 SingleWord Sets the handshake mode in the Asynchronous handshake mode In the Single Word mode the PDREQ signal is negated every time when one word is transferred In the Multi Word mode the PDREQ signal is not negated if the next data communication is possible when one word is transferred Notes In multi word DMA transfer mode the DMAC can only be triggered to start data t...

Page 604: ...egister is the OUT direc tion this register shows the remained data quantity in the FIFO of the endpoint When the direction of the endpoint connected to the DMA by the DMA_Join register is the IN direc tion this register shows the space capacity in the FIFO of the endpoint The DMA_Remain_H register and the DMA_Remain_L register must be accessed as a pair When ac cessing them access the DMA_Remain_...

Page 605: ...et to be in the countdown mode by the setting of the CountMode bit of the DMA_ Config_1 register CountMode 1 specify the total number of transmissions in the DMA Transfer Byte Counter set the DMA_Go bit of the DMA_Control register to 1 and then start the DMA transfer In this mode the DMA Transfer Byte Counter is decreased as much as the data quantity transferred by the DMA When it reaches 0x000000...

Page 606: ...ding to the MCLK clock frequency 1 1 RTCWT 2 0 RTC Wait Cycle Settings Table 29 RTCWT 2 0 Number of wait cycles MCLK frequency 0x7 7 cycles fMCLK 60 MHz 0x6 6 cycles 0x5 5 cycles 0x4 4 cycles 0x3 3 cycles 0x2 2 cycles 0x1 1 cycle 0x0 0 cycles Cannot be set Note Default 0x7 Note The S1C33L26 RTC cannot operate if RTCWT 2 0 is set to 0x0 0 wait cycles Internal RAM Wait Control 29 2 The MISC_RAMWT re...

Page 607: ...nables USB interrupts setting to 0 disables USB interrupts RAM Location 29 4 The MISC_RAM_LOC register contains IVRAM_LOC to select the IVRAM location and DSTRAM_CFG to se lect the DSTRAM location IVRAM is located in Area 3 by default IVRAM_LOC 1 and is used as the internal VRAM Setting IVRAM_ LOC to 0 relocates IVRAM in Area 0 and it can be used as a general purpose RAM DSTRAM is located in Area ...

Page 608: ...unction Setting Init R W Remarks RTC Wait Control Register MISC_RTCWT 0x300010 8 bits D7 3 reserved 0 when being read D2 0 RTCWT 2 0 RTC register access wait control 0 to 7 cycles 0x7 R W Write protected D 7 3 Reserved D 2 0 RTCWT 2 0 RTC Register Access Wait Control Bits Sets the number of wait cycles to be inserted when accessing the RTC control register 6 2 RTCWT 2 0 RTC Wait Cycle Settings Tab...

Page 609: ...Default 0x7 The number of wait cycles should be set according to the MCLK clock frequency Internal RAM Wait Control Register MISC_RAMWT Register name Address Bit Name Function Setting Init R W Remarks Internal RAM Wait Control Register MISC_RAMWT 0x300014 8 bits D7 2 reserved 0 when being read D1 COREWT IRAM 12KB access wait control 1 1 cycle 0 0 cycles 1 R W Write protected D0 BUSWT IVRAM 20KB ac...

Page 610: ... When programming a Flash memory using ICD33 BOOT_ENA must be set to 0 D0 Reserved RAM Location Select Register MISC_RAM_LOC Register name Address Bit Name Function Setting Init R W Remarks RAM Location Select Register MISC_RAM_ LOC 0x300018 8 bits D7 5 reserved 0 when being read D4 DSTRAM_ CFG DSTRAM configuration 1 LUTRAM 0 DSTRAM 0 R W Write protected D3 1 reserved 0 when being read D0 IVRAM_LO...

Page 611: ...0x300010 0x300018 Writing another value set the write protection 0x0 R W D 7 0 PROT 7 0 Misc Register Write Protect Flag Bits Enables or disables write protection of the Misc registers 0x300010 0x300018 0x96 R W Disable write protection Other than 0x96 R W Write protect the register default 0x0 Before altering any Misc register from 0x300010 to 0x300018 write data 0x96 to PROT 7 0 to disable write...

Page 612: ...r Reserved Division The division function performs A 16 bits B 16 bits C 16 bits D 16 bits remainder To perform a division set the operation mode to 0x8 unsigned division or 0x9 signed division Then send the 16 bit dividend B and 16 bit divisor C to the divider using a ld c imm4 rs instruction The quo tient A and the remainder D will be stored in the low order 16 bits and the high order 16 bits of...

Page 613: ...ure Tstg 65 to 150 C 1 HVDD AVDD LVDD RTCVDD PLLVDD LVDD RTCVDD PLLVDD 2 The maximum input voltage range of the STBY pin is VSS 0 3 V to 4 0 V Recommended Operating Conditions 31 2 Item Symbol Condition Min Typ Max Unit Power supply voltage High 1 HVDD AVDD When USB is not used 2 70 3 30 3 60 V When USB is used 3 00 3 30 3 60 V Power supply voltage Low 1 LVDD RTCVDD PLLVDD Crystal oscillator or ex...

Page 614: ...ent Bus hold latch HIBHH0 HVDD 3 6V VI 0 8V 350 µA Low level inverting current Bus hold latch HIBHL0 HVDD 3 6V VI 2 0V 300 µA LVDD RTCVDD system I O High level output voltage TYPE1 VOH1L LVDD 1 65V IOH 1mA LVDD 0 4 V Low level output voltage TYPE1 VOL1L LVDD 1 65V IOL 1mA 0 4 V High level input voltage LVCMOS VIH1L LVDD 1 95V 1 27 LVDD 0 3 V Low level input voltage LVCMOS VIL1L LVDD 1 65V 0 3 0 57...

Page 615: ...VCMOS VIL1L LVDD 1 65V 0 3 0 57 V Positive trigger input voltage LVCMOS Schmitt VT2 HVDD 3 6V LVDD 1 95V 0 6 1 4 V Negative trigger input voltage LVCMOS Schmitt VT2 HVDD 2 7V LVDD 1 65V 0 3 1 1 V Hysteresis voltage LVCMOS Schmitt DV2 HVDD 2 7V LVDD 1 65V 0 02 V Pull down resistor TYPE2 RPLD2L VI LVDD 48 120 300 kW Input pin capacitance CI f 1MHz HVDD 0V 8 pF Output pin capacitance CO f 1MHz HVDD 0...

Page 616: ...BY Low 1 3 µA RTCVDD RTC Run RTCCLK 32kHz PCLK2 10MHz STBY High 70 µA RTC Run RTCCLK 32kHz PCLK2 33MHz STBY High 210 µA RTC Run RTCCLK 32kHz PCLK2 48MHz STBY High 300 µA RTC Run RTCCLK 32kHz PCLK2 60MHz STBY High 410 µA USB current consumption during idle IUSB USB Snooze mode USBCLK 48MHz 3 7 mA LVDD LCDC current consumption during idle ILCDC LCDC Power save mode LCLK 48MHz 0 1 mA LVDD LCDC Normal...

Page 617: ... A D Converter Characteristics 31 5 Unless otherwise specified LVDD 1 65 to 1 95V HVDD AVDD 2 7 to 3 6V VSS 0V Ta 40 to 85 C ADST 2 0 0x7 Item Symbol Condition Min Typ Max Unit Resolution 10 bits Conversion time 1 10 1250 µs Zero scale error EZS 2 2 LSB Full scale error EFS 2 2 LSB Integral linearity error EL 3 3 LSB Differential linearity error ED 3 3 LSB Permissible signal source impedance 5 kW ...

Page 618: ...articular when a ceramic or crystal resona tor is used evaluate the components adequately under real operating conditions by mounting them on the board before the external register Rf Rd and capacitor CG CD values are finally decided OSC1 crystal oscillation Unless otherwise specified LVDD RTCVDD 1 65 to 1 95V VSS 0V Ta 25 C Item Symbol Condition Min Typ Max Unit Oscillation start time tSTA1 1 3 s...

Page 619: ...tC3H tC3 tIF tIR OSC1 external clock Unless otherwise specified LVDD RTCVDD 1 65 to 1 95V VSS 0V Ta 40 to 85 C Item Symbol Min Typ Max Unit OSC1 external clock cycle time tC1 30 51 µs OSC1 external clock input duty tC1ED 45 55 OSC1 external clock input rise time tIF 5 ns OSC1 external clock input fall time tIR 5 ns OSC3 external clock Unless otherwise specified LVDD RTCVDD 1 65 to 1 95V VSS 0V Ta ...

Page 620: ...te data hold time tWRDH 0 ns Read delay time tRDD 13 ns Read data setup time tRDS 13 ns Read data hold time tRDDH 0 ns Write signal pulse width tWRW tCYC 1 WC 13 ns Read signal pulse width tRDW tCYC 1 WC 13 ns WAIT setup time tWTS 12 ns WAIT hold time tWTH 0 ns WC Number of wait cycles SDRAMC AC Characteristics 31 8 3 SDRAM access cycle write read Column Bank Row Bank active Column tWEH tCASH SDCL...

Page 621: ...A10 SDCS SDRAS SDCAS SDWE D 15 0 DQMH DQML tAD tAH H valid tA10D tA10H tCSD tCSH tWED tWEH valid tRASD tRASH tCASD SDRAM auto refresh cycle SDCLK SDCKE SDBA 1 0 SDA 12 11 SDA 9 0 SDA10 SDCS SDRAS SDCAS SDWE D 15 0 DQMH DQML tCASH Auto refresh Nop Nop H tCSD tCSH tWED tWEH Nop tRASD tRASH tCASD A precharge cycle is necessary before entering the auto refresh mode ...

Page 622: ...time 1ns Access time 6 5ns max Item Symbol Min Typ Max Unit Address delay time tAD 12 1 ns Address hold time tAH 1 3 ns SDA10 signal delay time tA10D 12 1 ns SDA10 signal hold time tA10H 1 3 ns SDCS signal delay time tCSD 12 1 ns SDCS signal hold time tCSH 1 3 ns SDRAS signal delay time tRASD 12 1 ns SDRAS signal hold time tRASH 1 3 ns SDCAS signal delay time tCASD 12 1 ns SDCAS signal hold time t...

Page 623: ...signal delay time tCKED 10 3 ns SDCKE signal hold time tCKEH 1 3 ns SDWE signal delay time tWED 10 3 ns SDWE signal hold time tWEH 1 3 ns Read data setup time tRDS 6 3 ns Read data hold time tRDH 0 ns Write data delay time tWDD 10 3 ns Write data hold time tWDH 1 3 ns Note All the signals change at the rising edge of the SDRAM clock USI USIL AC Characteristics 31 8 4 SPI master slave mode USI USIL...

Page 624: ...SI_DI USI_CS USIL_DI USIL_CS input i2c_sda USI_DI USI_CS USIL_DI USIL_CS output Input data sampling point for master and slave I2C master mode Unless otherwise specified LVDD 1 65 to 1 95V HVDD 2 7 to 3 6V VSS 0V Ta 40 to 85 C Item Symbol Min Typ Max Unit i2c_scl cycle time tSCL 2500 ns i2c_sda output delay time tSDO 2 tT8 ns Start condition hold time tSTH 4 tT8 ns Stop condition hold time tSPH 3 ...

Page 625: ...rdata setup time tlcdprd_su 17 5 ns lcdp_rdata hold time tlcdprd_hd 0 ns lcdp_wr output delay time tlcdpwr 19 ns lcdp_wdata output delay time tlcdpwd 19 ns LCDC AC Characteristics 31 8 5 4 bit single monochrome panel timing FPFRAME FPLINE FPDRDY MOD FPDAT 7 4 VDP VNDP FPLINE FPDRDY MOD FPSHIFT FPDAT7 FPDAT6 FPDAT5 FPDAT4 Line 1 1 1 1 5 1 317 1 2 1 6 1 318 1 3 1 7 1 319 1 4 1 8 1 320 Line 2 Line 3 ...

Page 626: ...e Pulse width 9 Ts t5 MOD delay from Line Pulse rising edge 1 Ts t6 Shift Pulse falling edge to Line Pulse rising edge note 4 t7 Shift Pulse falling edge to Line Pulse falling edge note 5 t8 Line Pulse falling edge to Shift Pulse falling edge t14 2 Ts t9 Shift Pulse period 4 Ts t10 Shift Pulse width low 2 Ts t11 Shift Pulse width high 2 Ts t12 FPDAT 7 4 setup to Shift Pulse falling edge 2 Ts t13 F...

Page 627: ...1 11 1 315 1 4 1 12 1 316 1 5 1 13 1 317 1 6 1 14 1 318 1 7 1 15 1 319 1 8 1 16 1 320 Line 2 Line 3 Line 1 Line 2 Line 4 Line 239 Line 240 HDP HNDP Diagram drawn with 2 FPLINE vertical blank period Example timing for a 320 240 panel For this timing diagram FPSMASK is set to 1 HDP Horizontal Display Period HDPCNT 6 0 1 8 Ts HNDP Horizontal Non Display Period HTCNT 6 0 HDPCNT 6 0 8 Ts VDP Vertical D...

Page 628: ...e Pulse width 9 Ts t5 MOD delay from Line Pulse rising edge 1 Ts t6 Shift Pulse falling edge to Line Pulse rising edge note 4 t7 Shift Pulse falling edge to Line Pulse falling edge note 5 t8 Line Pulse falling edge to Shift Pulse falling edge t14 4 Ts t9 Shift Pulse period 8 Ts t10 Shift Pulse width low 4 Ts t11 Shift Pulse width high 4 Ts t12 FPDAT 7 0 setup to Shift Pulse falling edge 4 Ts t13 F...

Page 629: ...B319 1 G1 1 B2 1 R320 1 B1 1 R3 1 G320 1 R2 1 G3 1 B3 1 R4 1 G4 1 B4 1 B320 Line 2 Line 3 Line 1 Line 2 Line 4 Line 239 Line 240 HDP HNDP Diagram drawn with 2 FPLINE vertical blank period Example timing for a 320 240 panel HDP Horizontal Display Period HDPCNT 6 0 1 8 Ts HNDP Horizontal Non Display Period HTCNT 6 0 HDPCNT 6 0 8 Ts VDP Vertical Display Period VDPCNT 9 0 1 lines VNDP Vertical Non Dis...

Page 630: ...idth 9 Ts t5 MOD delay from Line Pulse rising edge 1 Ts t6 Shift Pulse falling edge to Line Pulse rising edge note 4 t7 Shift Pulse falling edge to Line Pulse falling edge note 5 t8 Line Pulse falling edge to Shift Pulse falling edge t14 0 5 Ts t9 Shift Pulse period 1 Ts t10 Shift Pulse width low 0 5 Ts t11 Shift Pulse width high 0 5 Ts t12 FPDAT 7 4 setup to Shift Pulse falling edge 0 5 Ts t13 FP...

Page 631: ...240 1 B5 1 R6 1 B240 1 G6 1 R7 1 B7 1 G8 1 R9 1 B9 1 G10 1 R11 1 B6 1 G7 1 R8 1 B8 1 G9 1 R10 1 B10 1 G11 1 B11 1 G12 1 R13 1 B13 1 G14 1 R15 1 B15 1 G16 1 R12 1 B12 1 G13 1 R14 1 B14 1 G15 1 R16 1 B16 Line 2 Line 3 Line 1 Line 2 Line 4 Line 239 Line 240 HDP HNDP Diagram drawn with 2 FPLINE vertical blank period Example timing for a 320 240 panel HDP Horizontal Display Period HDPCNT 6 0 1 8 Ts HND...

Page 632: ...ge to Line Pulse rising edge note 5 t7a Shift Pulse 2 falling edge to Line Pulse falling edge note 6 t7b Shift Pulse falling edge to Line Pulse falling edge note 7 t8 Line Pulse falling edge to Shift Pulse rising Shift Pulse 2 falling edge t14 2 Ts t9 Shift Pulse 2 Shift Pulse period 4 Ts t10 Shift Pulse 2 Shift Pulse width low 2 Ts t11 Shift Pulse 2 Shift Pulse width high 2 Ts t12 FPDAT 7 0 setup...

Page 633: ... 1 G4 1 R239 1 R2 1 B4 1 G239 1 G2 1 R5 1 B239 1 B2 1 G5 1 R240 1 R3 1 B5 1 G240 1 G3 1 R6 1 G6 1 B6 1 R7 1 G7 1 B7 1 R8 1 G8 1 B8 1 B240 Line 2 Line 3 Line 1 Line 2 Line 4 Line 239 Line 240 HDP HNDP Diagram drawn with 2 FPLINE vertical blank period Example timing for a 320 240 panel HDP Horizontal Display Period HDPCNT 6 0 1 8 Ts HNDP Horizontal Non Display Period HTCNT 6 0 HDPCNT 6 0 8 Ts VDP Ve...

Page 634: ... Pulse width 9 Ts t5 MOD delay from Line Pulse rising edge 1 Ts t6 Shift Pulse falling edge to Line Pulse rising edge note 4 t7 Shift Pulse falling edge to Line Pulse falling edge note 5 t8 Line Pulse falling edge to Shift Pulse falling edge t14 2 Ts t9 Shift Pulse period 2 3 Ts t10 Shift Pulse width low 1 Ts t11 Shift Pulse width high 1 Ts t12 FPDAT 7 0 setup to Shift Pulse falling edge 1 Ts t13 ...

Page 635: ...s t6 Horizontal display period note 6 Ts t7 FPLINE rising edge to TFT_CTL3 rising edge 59 Ts t8 TFT_CTL3 pulse width 1 Ts t9 FPLINE rising edge to TFT_CTL2 change 11 Ts note 1 Ts pixel clock period 2 t1typ FPLINE_ST 9 0 1 Ts 3 t2typ HTCNT 6 0 1 8 Ts 4 t3typ FPLINE_WD 6 0 1 Ts 5 t5typ HDPSCNT 9 0 1 Ts 6 t6typ HDPCNT 6 0 1 8 Ts 2 Generic HR TFT panel vertical timing Line 1 Line 2 Line 239 Line 240 F...

Page 636: ...re for at least tBUPS 2 Before setting the STBY pin to high to cancel backup state wait at least tBUPH after LVDD goes 1 65 V or higher USB DC and AC Characteristics 31 9 Input levels Unless otherwise specified LVDD 1 65 to 1 95V HVDD 3 0 to 3 6V VSS 0V Ta 0 to 70 C Item Symbol Condition Min Typ Max Unit VBUS input 1 VBUS 4 40 5 25 V High driven 2 VIH 2 0 V High floating 2 VIHZ 2 7 3 6 V Low 2 VIL...

Page 637: ...ceiving 5 VPUA 1 425 3 090 kW 5 Refer to ECN in the USB2 0 Specification for the conditions Driver characteristics Unless otherwise specified LVDD 1 65 to 1 95V HVDD 3 0 to 3 6V VSS 0V Ta 0 to 70 C Item Symbol Condition Min Typ Max Unit Rise time 6 TFR 4 20 ns Fall time 6 TFF 4 20 ns Differential rise and fall time matching TFRFM TFR TFF 90 111 11 Driver output resistance ZDRV 28 44 W VBUS input i...

Page 638: ...H PWM_L T16A_EXCL_x T16A_ATMA_x T16A_ATMB_x REMC_I REMC_O Pxx LCD panel Card NAND Flash I2S A D input 16 bit PWM timer T16A5 input output I O Serial I O UART SPI I2C Serial parallel I O UART SPI I2C LCD driver Serial I O FSIO Remote transmitter receiver 16 bit audio PWM timer T16P input output S1C33L26 The potential of the substrate back of the chip is VSS LVDD RTCVDD PLLVDD HVDD AVDD MCLKI MCLKO ...

Page 639: ...facturing Co Ltd 1M CSBFB1M00J58 R1 SMD 330 330 1M 680 20 to 80 1M CSBLA1M00J58 B0 leaded 330 330 1M 680 20 to 80 4M CSTCR4M00G55 R0 leaded 39 39 1M 470 20 to 80 4M CSTLS4M00G56 B0 leaded 47 47 1M 330 20 to 80 10M CSTCE10M0G55 R0 SMD 33 33 1M 220 20 to 80 10M CSTLS10M0G56 B0 leaded 47 47 1M 220 20 to 80 20M CSTCE20M0V53 R0 SMD 15 15 1M 0 20 to 80 20M CSTCG20M0V53 R0 small SMD 15 15 1M 0 20 to 80 4...

Page 640: ...Level Register Set T16A5 Ch 0 interrupt level 0x30021a ITC_T16A1_LV T16A5 Ch 1 Interrupt Level Register Set T16A5 Ch 1 interrupt level 0x30021b ITC_LCDC_LV LCDC Interrupt Level Register Set LCDC interrupt level 0x30021d ITC_T804_LV T8 Ch 0 4 Interrupt Level Register Set T8 Ch 0 and 4 interrupt levels 0x30021e ITC_T815_LV T8 Ch 1 5 Interrupt Level Register Set T8 Ch 1 and 5 interrupt levels 0x30021...

Page 641: ...FPTC F interrupts 0x300338 GPIO_FPT03_MOD FPT0 3 Interrupt Mode Select Register Select edge level mode for FPT0 3 interrupts 0x300339 GPIO_FPT47_MOD FPT4 7 Interrupt Mode Select Register Select edge level mode for FPT4 7 interrupts 0x30033a GPIO_FPT8B_MOD FPT8 B Interrupt Mode Select Register Select edge level mode for FPT8 B interrupts 0x30033b GPIO_FPTCF_MOD FPTC F Interrupt Mode Select Register...

Page 642: ..._ISIF USI I2C Slave Mode Interrupt Flag Register Indicate I2C slave interrupt cause status USIL 8 bit device 0x300600 USIL_GCFG USIL Global Configuration Register Set interface and MSB LSB modes 0x300601 USIL_TD USIL Transmit Data Buffer Register Transmit data buffer 0x300602 USIL_RD USIL Receive Data Buffer Register Receive data buffer 0x300640 USIL_UCFG USIL UART Mode Configuration Register Set ...

Page 643: ... RTC_MIN RTC Minute Register Minute counter data 0x300a06 RTC_HOUR RTC Hour Register Hour counter data 0x300a07 RTC_DAY RTC Day Register Day counter data 0x300a08 RTC_MONTH RTC Month Register Month counter data 0x300a09 RTC_YEAR RTC Year Register Year counter data 0x300a0a RTC_WEEK RTC Days of Week Register Days of week counter data 0x300a0f RTC_WAKEUP RTC Wakeup Configuration Register Set RTC wak...

Page 644: ...1 Register 0x300c5c EPdMaxSize_H EPd Max Packet Size High Register Set EPd max packet size 0x300c5d EPdMaxSize_L EPd Max Packet Size Low Register 0x300c5e EPdConfig_0 EPd Configuration 0 Register Configure EPd 0x300c5f EPdConfig_1 EPd Configuration 1 Register 0x300c70 EPaStartAdrs_H EPa FIFO Start Address High Register Set FIFO start address for EPa 0x300c71 EPaStartAdrs_L EPa FIFO Start Address L...

Page 645: ...3 Control Register Set timer mode and start stop timer 0x301138 T8_INT3 T8 Ch 3 Interrupt Control Register Control interrupt 8 bit timer T8 Ch 4 16 bit device 0x301140 T8_CLK4 T8 Ch 4 Input Clock Select Register Select prescaler output clock 0x301142 T8_TR4 T8 Ch 4 Reload Data Register Set reload data 0x301144 T8_TC4 T8 Ch 4 Counter Data Register Counter data 0x301146 T8_CTL4 T8 Ch 4 Control Regis...

Page 646: ...PSAVE Status and Power Save Configuration Register Indicate LCDC status and set power save mode 0x302010 LCDC_HDISP Horizontal Display Register Set horizontal display period 0x302014 LCDC_VDISP Vertical Display Register Set vertical display period 0x302018 LCDC_MODR MOD Rate Register Set MOD rate 0x302020 LCDC_HDPS Horizontal Display Start Position Register Set horizontal display start position fo...

Page 647: ...x302449 GE_IF2 GE Interrupt Flag Register 2 Indicate drawing error status 0x30244a GE_IF3 GE Interrupt Flag Register 3 Indicate cause of termination 0x30244c GE_REAL_W VRAM Work Area Width Register Indicate work area width after VRAM rotation 0x302450 GE_WK_ADDR VRAM Work Area Start Address Register Set work drawing area start address 0x302454 GE_WK_SIZE VRAM Work Area Size Register Set work area ...

Page 648: ...served 0 when being read RAM Location Select Register MISC_RAM_ LOC 0x300018 8 bits D7 5 reserved 0 when being read D4 DSTRAM_ CFG DSTRAM configuration 1 LUTRAM 0 DSTRAM 0 R W Write protected D3 1 reserved 0 when being read D0 IVRAM_LOC IVRAM location select 1 Area 3 0 Area 0 1 R W Write protected Misc Protect Register MISC_ PROTECT 0x300020 8 bits D7 0 PROT 7 0 Misc register write protect flag Wr...

Page 649: ...W D2 PCLK2_EN PCLK2 clock enable 1 Enable 0 Disable 1 R W D1 PCLK1_EN PCLK1 clock enable 1 Enable 0 Disable 1 R W D0 GCLK_EN GCLK clock enable 1 Enable 0 Disable 1 R W System Clock Division Ratio Select Register CMU_ SYSCLKDIV 0x300105 8 bits D7 5 reserved 0 when being read D4 MCLKDIV MCLK clock divider select 1 1 2 0 1 1 0 R W Write protected D3 reserved 0 when being read D2 0 SYSCLKDIV 2 0 Syste...

Page 650: ...capacitance 0x0 0x0 R D5 PLLBYP PLL bypass mode 0 0 R D4 0 PLLCP 4 0 PLL charge pump current 0x10 0x10 R SSCG Macro Control Register 0 CMU_SSCG0 0x30010c 8 bits D7 1 reserved 0 when being read D0 SSMCON SSCG enable 1 Enable 0 Disable 0 R W Write protected SSCG Macro Control Register 1 CMU_SSCG1 0x30010d 8 bits D7 4 SSMCITM 3 0 SSCG interval timer ITM setting 0x0 to 0xf X R W Write protected D3 0 S...

Page 651: ... D2 0 INT_LV 2 0 LCDC interrupt level 1 to 7 0x0 R W T8 Ch 0 4 Interrupt Level Register ITC_T804_LV 0x30021d 8 bits D7 3 reserved 0 when being read D2 0 INT_LV 2 0 T8 Ch 0 and 4 interrupt level 1 to 7 0x0 R W T8 Ch 1 5 Interrupt Level Register ITC_T815_LV 0x30021e 8 bits D7 3 reserved 0 when being read D2 0 INT_LV 2 0 T8 Ch 1 and 5 interrupt level 1 to 7 0x0 R W T8 Ch 2 6 Interrupt Level Register ...

Page 652: ...gister GPIO_P2_IOC 0x300305 8 bits D7 2 reserved 0 when being read D1 0 IOC2 1 0 P2 1 0 I O control 1 Output 0 Input 0x0 R W P3 Port Data Register GPIO_P3_DAT 0x300306 8 bits D7 reserved 0 when being read D6 0 P3 6 0 D P3 6 0 I O port data 1 1 High 0 0 Low Ext R W Ext Depends on the external pin status P3 Port I O Control Register GPIO_P3_IOC 0x300307 8 bits D7 reserved 0 when being read D6 0 IOC3...

Page 653: ...p Write protected P1 Port Pull up Control Register GPIO_P1_PUP 0x300322 8 bits D7 0 PUP1 7 0 P1 7 0 port pull up enable 1 Enable 0 Disable 0x0 R W P1 7 0 not pulled up Write protected P2 Port Pull up Control Register GPIO_P2_PUP 0x300323 8 bits D7 2 reserved 0 when being read D1 0 PUP2 1 0 P2 1 0 port pull up enable 1 Enable 0 Disable 0x0 R W P2 1 0 not pulled up Write protected P3 Port Pull up Co...

Page 654: ...2 0x1 0x0 P30 P10 P50 P00 FPT4 7 Interrupt Port Select Register GPIO_FPT47_ SEL 0x300331 8 bits D7 6 SPT7 1 0 FPT7 interrupt input port select SPT7 1 0 Port 0x0 R W 0x3 0x2 0x1 0x0 PA3 P17 PC7 P07 D5 4 SPT6 1 0 FPT6 interrupt input port select SPT6 1 0 Port 0x0 R W 0x3 0x2 0x1 0x0 PA2 P16 PC6 P06 D3 2 SPT5 1 0 FPT5 interrupt input port select SPT5 1 0 Port 0x0 R W 0x3 0x2 0x1 0x0 PA1 P15 PC5 P05 D...

Page 655: ...olarity select 1 High 0 Low 1 R W D0 SPPTC FPTC input polarity select 1 High 0 Low 1 R W FPT0 3 Interrupt Mode Select Register GPIO_FPT03_ MOD 0x300338 8 bits D7 4 reserved 0 when being read D3 SEPT3 FPT3 interrupt mode select 1 Edge 0 Level 1 R W D2 SEPT2 FPT2 interrupt mode select 1 Edge 0 Level 1 R W D1 SEPT1 FPT1 interrupt mode select 1 Edge 0 Level 1 R W D0 SEPT0 FPT0 interrupt mode select 1 ...

Page 656: ...GPIO_FPT8B_ FLG 0x300342 8 bits D7 4 reserved 0 when being read D3 SFGPB FPTB interrupt flag 1 Cause of interrupt occurred 0 Cause of interrupt not occurred X R W Reset by writing 1 D2 SFGPA FPTA interrupt flag X R W D1 SFGP9 FPT9 interrupt flag X R W D0 SFGP8 FPT8 interrupt flag X R W FPTC F Interrupt Flag Register GPIO_FPTCF_ FLG 0x300343 8 bits D7 4 reserved 0 when being read D3 SFGPF FPTF inte...

Page 657: ...D7 reserved 0 when being read D6 4 SCTP7 2 0 FPT7 chattering filter time select SCTP7 2 0 Filter sampling time 0x0 R W 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 64 fPCLK2 32 fPCLK2 16 fPCLK2 8 fPCLK2 4 fPCLK2 2 fPCLK2 1 fPCLK2 None D3 reserved 0 when being read D2 0 SCTP6 2 0 FPT6 chattering filter time select SCTP6 2 0 Filter sampling time 0x0 R W 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 64 fPCLK2 32 fPCLK2 16 fPCL...

Page 658: ...D7 reserved 0 when being read D6 4 SCTPD 2 0 FPTD chattering filter time select SCTPD 2 0 Filter sampling time 0x0 R W 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 64 fPCLK2 32 fPCLK2 16 fPCLK2 8 fPCLK2 4 fPCLK2 2 fPCLK2 1 fPCLK2 None D3 reserved 0 when being read D2 0 SCTPC 2 0 FPTC chattering filter time select SCTPC 2 0 Filter sampling time 0x0 R W 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 64 fPCLK2 32 fPCLK2 16 fPCL...

Page 659: ... CFP00 1 0 Function 0x0 R W 0x3 0x2 0x1 0x0 NAND_WR SIN1 USI_DI P00 P0 7 4 Port Function Select Register PMUX_P0_47 0x300801 8 bits D7 6 CFP07 1 0 P07 port function select CFP07 1 0 Function 0x0 R W Write protected 0x3 0x2 0x1 0x0 PWM_L I2S_MCLK SRDY0 P07 D5 4 CFP06 1 0 P06 port function select CFP06 1 0 Function 0x0 R W 0x3 0x2 0x1 0x0 PWM_H I2S_SCLK SCLK0 P06 D3 2 CFP05 1 0 P05 port function sel...

Page 660: ...CLK D1 0 CFP20 1 0 P20 port function select CFP20 1 0 Function 0x0 R W 0x3 0x2 0x1 0x0 reserved reserved P20 SDCKE P3 3 0 Port Function Select Register PMUX_P3_03 0x300806 8 bits D7 6 CFP33 1 0 P33 port function select CFP33 1 0 Function 0x0 R W Write protected 0x3 0x2 0x1 0x0 REMC_I TFT_CTL3 reserved P33 D5 4 CFP32 1 0 P32 port function select CFP32 1 0 Function 0x0 R W 0x3 0x2 0x1 0x0 REMC_O TFT...

Page 661: ... Function 0x0 R W 0x3 0x2 0x1 0x0 reserved SDCS P50 CE7 P5 6 4 Port Function Select Register PMUX_P5_46 0x30080b 8 bits D7 6 reserved 0 when being read D5 4 CFP56 1 0 P56 port function select CFP56 1 0 Function 0x0 R W Write protected 0x3 0x2 0x1 0x0 reserved reserved P56 WRH BSH D3 2 CFP55 1 0 P55 port function select CFP55 1 0 Function 0x0 R W 0x3 0x2 0x1 0x0 reserved reserved P55 WRL D1 0 CFP54...

Page 662: ...ort function select CFP80 1 0 Function 0x0 R W 0x3 0x2 0x1 0x0 reserved USIL_CS FPFRAME P80 P9 3 0 Port Function Select Register PMUX_P9_03 0x300812 8 bits D7 6 CFP93 1 0 P93 port function select CFP93 1 0 Function 0x0 R W Write protected 0x3 0x2 0x1 0x0 SRDY0 LCD_D3 FPDAT3 P93 D5 4 CFP92 1 0 P92 port function select CFP92 1 0 Function 0x0 R W 0x3 0x2 0x1 0x0 SCLK0 LCD_D2 FPDAT2 P92 D3 2 CFP91 1 0...

Page 663: ...C_I T16A_ATMB_1 PA5 A25 D1 0 CFPA4 1 0 PA4 port function select CFPA4 1 0 Function 0x0 R W 0x3 0x2 0x1 0x0 REMC_O T16A_ATMA_1 PA4 A24 PB 3 0 Port Function Select Register PMUX_PB_03 0x300816 8 bits D7 6 CFPB3 1 0 PB3 port function select CFPB3 1 0 Function 0x0 R W Write protected 0x3 0x2 0x1 0x0 PWM_L I2S_MCLK FPDAT11 PB3 D5 4 CFPB2 1 0 PB2 port function select CFPB2 1 0 Function 0x0 R W 0x3 0x2 0...

Page 664: ...5 D13 D1 0 CFPC4 1 0 PC4 port function select CFPC4 1 0 Function 0x0 R W 0x3 0x2 0x1 0x0 reserved reserved PC4 D12 Port Noise Filter Control Register GPIO_FILTER 0x30083e 8 bits D7 1 reserved 0 when being read D0 ANFEN Input port noise filter enable 1 Enable 0 Disable 0 R W Write protected GPIO PMUX Write Protect Register GPIO_ PROTECT 0x30083f 8 bits D7 0 PPROT 7 0 GPIO PMUX register protect flag...

Page 665: ...SPI Master Slave Mode In terrupt Enable Register USI_SIE 0x300451 8 bits D7 3 reserved 0 when being read D2 SEIE Receive error interrupt enable 1 Enable 0 Disable 0 R W D1 SRDIE Receive buffer full interrupt enable 1 Enable 0 Disable 0 R W D0 STDIE Transmit buffer empty int enable 1 Enable 0 Disable 0 R W USI SPI Master Slave Mode Interrupt Flag Register USI_SIF 0x300452 8 bits D7 4 reserved 0 whe...

Page 666: ...00600 8 bits D7 4 reserved 0 when being read D3 LSBFST MSB LSB first mode select 1 MSB first 0 LSB first 0 R W D2 0 USILMOD 2 0 Interface mode configuration USILMOD 2 0 I F mode 0x0 R W 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 LCD Parallel LCD SPI I2C slave I2C master SPI slave SPI master UART Software reset USIL Transmit Data Buffer Register USIL_TD 0x300601 8 bits D7 0 TD 7 0 USIL transmit data buffer TD...

Page 667: ...ster trigger mode select IMTGMOD 2 0 Trigger mode 0x0 R W 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 reserved Receive ACK NAK Transmit NAK Transmit ACK Receive data Transmit data Stop condition Start condition USIL I2C Master Mode Interrupt Enable Register USIL_IMIE 0x300661 8 bits D7 2 reserved 0 when being read D1 IMEIE Receive error interrupt enable 1 Enable 0 Disable 0 R W D0 IMIE Operation completion in...

Page 668: ...a Configuration Register USIL_ LSDCFG 0x30068f 8 bits D7 4 reserved 0 when being read D3 2 LS18DFM 1 0 LCD SPI 18 bit data format select LS18DFM 1 0 Data format 0x0 R W 0x3 0x2 0x1 0x0 Format 3 Format 2 Format 1 Format 0 D1 0 LSDMOD 1 0 LCD SPI data mode select LSDMOD 1 0 Data mode 0x0 R W 0x3 0x2 0x1 0x0 24 bit mode 18 bit mode 16 bit mode 8 bit mode USIL LCD Parallel I F Mode Configu ration Regi...

Page 669: ... D1 0 SMD 1 0 Transfer mode select SMD 1 0 Transfer mode 0x0 R W 0x3 0x2 0x1 0x0 8 bit async 7 bit async Clk sync slave Clk sync master FSIO Ch 0 IrDA Register FSIO_IRDA0 0x300704 8 bits D7 SRDYCTL SRDY control 1 High mask 0 Normal 0 R W Writing is disabled when SIOADV 0 D6 5 FIFOINT 1 0 Receive buffer full interrupt timing FIFOINT 1 0 Receive level 0x0 R W 0x3 0x2 0x1 0x0 4 3 2 1 D4 DIVMD Async c...

Page 670: ...us flag 1 Busy 0 End Idle 0 R D4 FER Framing error flag 1 Error 0 Normal 0 R W Reset by writing 0 D3 PER Parity error flag 1 Error 0 Normal 0 R W D2 OER Overrun error flag 1 Error 0 Normal 0 R W D1 TDBE Transmit data buffer empty flag 1 Empty 0 Full 1 R D0 RDBF Receive data buffer status flag 1 Contained 0 Not contained 0 R FSIO Ch 1 Control Register FSIO_CTL1 0x300713 8 bits D7 TXEN Transmit enab...

Page 671: ...tus Register RTC_INTSTAT 0x300a00 8 bits D7 1 reserved 0 when being read D0 RTCIRQ Interrupt status 1 Occurred 0 Not occurred X 0 R W Reset by writing 1 RTC Interrupt Mode Register RTC_INTMODE 0x300a01 8 bits D7 5 reserved 0 when being read D4 2 RTCT 2 0 RTC interrupt cycle setup RTCT 2 0 Cycle X 0x1 R W 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 reserved 1 128 second 1 256 second 1 512 second 1 hour 1 minut...

Page 672: ...ts D7 SIE_IntStat 1 SIE interrupts 0 None 0 R D6 EPrIntStat 1 EPr interrupts 0 None 0 R D5 DMA_IntStat 1 DMA interrupts 0 None 0 R D4 FIFO_IntStat 1 FIFO interrupts 0 None 0 R D3 2 0 when being read D1 EP0IntStat 1 EP0 interrupts 0 None 0 R D0 RcvEP0SETUP 1 Receive EP0 SETUP 0 None 0 R W SIE_IntStat SIE interrupt status 0x300c01 8 bits D7 VBUS_Changed 1 VBUS is changed 0 None 0 R W D6 NonJ 1 Detec...

Page 673: ...nterrupt status 0x300c0b 8 bits D7 0 when being read D6 OUT_ShortACK 1 Out short packet ACK 0 None 0 R W D5 IN_TranACK 1 In transaction ACK 0 None 0 R W D4 OUT_TranACK 1 Out transaction ACK 0 None 0 R W D3 IN_TranNAK 1 In transaction NAK 0 None 0 R W D2 OUT_TranNAK 1 Out transaction NAK 0 None 0 R W D1 IN_TranErr 1 In transaction error 0 None 0 R W D0 OUT_TranErr 1 Out transaction error 0 None 0 R...

Page 674: ...negotiation 0 Disable auto negotiation 0 R W D5 InSUSPEND 1 Monitor NonJ 0 Do nothing 0 R W D4 StartDetectJ 1 Start J state detection 0 Do nothing 0 R W D3 SendWakeup 1 Send remote wakeup signal 0 Do nothing 0 R W D2 1 0 when being read D0 ActiveUSB 1 Activate USB 0 Disactivate USB 0 R W USB_Status USB status 0x300c22 8 bits D7 VBUS 1 VBUS High 0 VBUS Low X R D6 FS 1 FS mode fixed 0 1 R D5 2 0 whe...

Page 675: ...ALL 0 Do nothing 0 R W EP0ControlOUT EP0 control OUT 0x300c3b 8 bits D7 AutoForceNAK 1 Auto force NAK 0 Do nothing 0 R W D6 5 0 when being read D4 ToggleStat Toggle sequence bit 0 R D3 ToggleSet 1 Set toggle sequence bit 0 Do nothing 0 W 0 when being read D2 ToggleClr 1 Clear toggle sequence bit 0 Do nothing 0 W D1 ForceNAK 1 Force NAK 0 Do nothing 0 R W D0 ForceSTALL 1 Force STALL 0 Do nothing 0 ...

Page 676: ...ow 0x300c55 8 bits D7 0 EPbMaxSize 7 0 Endpoint EPb max packet size 0x0 R W EPbConfig_0 EPb configuration 0 0x300c56 8 bits D7 INxOUT 1 In 0 Out 0 R W D6 ToggleMode 1 Always toggle 0 Normal toggle 0 R W D5 EnEndPoint 1 Enable endpoint 0 Disable endpoint 0 R W D4 0 when being read D3 0 EndPointNumber 3 0 Endpoint number 0x1 to 0xf 0x0 R W EPbConfig_1 EPb configuration 1 0x300c57 8 bits D7 ISO 1 ISO...

Page 677: ...IFO read 0 Do nothing 0 R W D2 JoinEPcRd 1 Join EPc FIFO read 0 Do nothing 0 R W D1 JoinEPbRd 1 Join EPb FIFO read 0 Do nothing 0 R W D0 JoinEPaRd 1 Join EPa FIFO read 0 Do nothing 0 R W CPU_JoinWr CPU join FIFO write 0x300c81 8 bits D7 4 0 when being read D3 JoinEPdWr 1 Join EPd FIFO write 0 Do nothing 0 R W D2 JoinEPcWr 1 Join EPc FIFO write 0 Do nothing 0 R W D1 JoinEPbWr 1 Join EPb FIFO write ...

Page 678: ...ormal 0 R W D6 4 0 when being read D3 SingleWord 1 Single word 0 Multi word 0 R W D2 1 0 when being read D0 CountMode 1 Count down mode 0 Free run mode 0 R W DMA_Latency DMA latency 0x300c97 8 bits D7 4 0 when being read D3 0 DMA_Latency 3 0 Latency 0x0 R W DMA_Remain_H DMA FIFO remain high 0x300c98 8 bits D7 4 0 when being read D3 0 DMA_Remain 11 8 DMA FIFO remain 0x0 R DMA_Remain_L DMA FIFO rema...

Page 679: ...ad D0 WDRESEN WDT reset 1 Reset 0 ignored 0 W 0x301100 0x301108 8 bit Timer T8 Ch 0 with Fine mode Register name Address Bit Name Function Setting Init R W Remarks T8 Ch 0 Input Clock Select Register T8_CLK0 0x301100 16 bits D15 4 reserved 0 when being read D3 0 DF 3 0 T8 clock division ratio select Prescaler output clock DF 3 0 Division ratio 0x0 R W Source clock PCLK1 0xf 0xe 0xd 0xc 0xb 0xa 0x9...

Page 680: ...reserved 0 when being read D4 TRMD Count mode select 1 One shot 0 Repeat 0 R W D3 2 reserved 0 when being read D1 PRESER Timer reset 1 Reset 0 Ignored 0 W D0 PRUN Timer run stop control 1 Run 0 Stop 0 R W T8 Ch 1 Interrupt Control Register T8_INT1 0x301118 16 bits D15 9 reserved 0 when being read D8 T8IE T8 interrupt enable 1 Enable 0 Disable 0 R W D7 1 reserved 0 when being read D0 T8IF T8 interr...

Page 681: ...3 0 DF 3 0 T8 clock division ratio select Prescaler output clock DF 3 0 Division ratio 0x0 R W Source clock PCLK2 0xf 0xe 0xd 0xc 0xb 0xa 0x9 0x8 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 reserved 1 16384 1 8192 1 4096 1 2048 1 1024 1 512 1 256 1 128 1 64 1 32 1 16 1 8 1 4 1 2 1 1 T8 Ch 3 Reload Data Register T8_TR3 0x301132 16 bits D15 8 reserved 0 when being read D7 0 TR 7 0 T8 reload data TR7 MSB TR0 LSB...

Page 682: ...T8 Ch 4 Interrupt Control Register T8_INT4 0x301148 16 bits D15 9 reserved 0 when being read D8 T8IE T8 interrupt enable 1 Enable 0 Disable 0 R W D7 1 reserved 0 when being read D0 T8IF T8 interrupt flag 1 Cause of interrupt occurred 0 Cause of interrupt not occurred 0 R W Reset by writing 1 0x301150 0x301158 8 bit Timer T8 Ch 5 Register name Address Bit Name Function Setting Init R W Remarks T8 C...

Page 683: ... counter data TC7 MSB TC0 LSB 0x0 to 0xff 0xff R T8 Ch 6 Control Register T8_CTL6 0x301166 16 bits D15 5 reserved 0 when being read D4 TRMD Count mode select 1 One shot 0 Repeat 0 R W D3 2 reserved 0 when being read D1 PRESER Timer reset 1 Reset 0 Ignored 0 W D0 PRUN Timer run stop control 1 Run 0 Stop 0 R W T8 Ch 6 Interrupt Control Register T8_INT6 0x301168 16 bits D15 9 reserved 0 when being re...

Page 684: ...384 1 8192 1 4096 1 2048 1 1024 1 512 1 256 1 128 1 64 1 32 1 16 1 8 1 4 1 2 1 1 D7 BUSY Register writing status 1 Busy 0 Idle 0 R D6 reserved 0 when being read D5 4 T16SEL 1 0 Counter select T16SEL 1 0 Counter channel 0x0 R W 0x3 0x2 0x1 0x0 Ch 1 Ch 0 Ch 1 Ch 0 D3 CBUFEN Compare buffer enable 1 Enable 0 Disable 0 R W D2 TMMD Count mode select 1 One shot 0 Repeat 0 R W D1 PRESET Counter reset 1 Re...

Page 685: ... not occurred 0 R W Reset by writing 1 D4 CAPAOWIF Capture A overwrite interrupt flag 0 R W D3 CAPBIF Capture B interrupt flag 0 R W D2 CAPAIF Capture A interrupt flag 0 R W D1 CBIF Compare B interrupt flag 0 R W D0 CAIF Compare A interrupt flag 0 R W 0x301190 0x30119c 16 bit PWM Timer T16A5 Ch 1 Register name Address Bit Name Function Setting Init R W Remarks T16A5 Ch 1 Counter Control Register T...

Page 686: ...Enable 0 Disable 0 R W D4 CAPAOWIE Capture A overwrite interrupt enable 1 Enable 0 Disable 0 R W D3 CAPBIE Capture B interrupt enable 1 Enable 0 Disable 0 R W D2 CAPAIE Capture A interrupt enable 1 Enable 0 Disable 0 R W D1 CBIE Compare B interrupt enable 1 Enable 0 Disable 0 R W D0 CAIE Compare A interrupt enable 1 Enable 0 Disable 0 R W T16A5 Ch 1 Comparator Capture Interrupt Flag Register T16A_...

Page 687: ...1 128 1 64 1 32 1 16 1 8 1 4 1 2 1 1 T16P Interrupt Control Register T16P_INT 0x30120e 16 bits D15 11 reserved 0 when being read D10 BUFEF Buffer empty interrupt flag 1 Cause of interrupt occurred 0 Cause of interrupt not occurred X R W Reset by writing 1 D9 INTBF B match interrupt flag 0 R W D8 INTAF A match interrupt flag 0 R W D7 3 reserved 0 when being read D2 INTBEEN Buffer empty interrupt en...

Page 688: ...ource clock PCLK1 0xf 0xe 0xd 0xc 0xb 0xa 0x9 0x8 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 reserved 1 32768 1 16384 1 8192 1 4096 1 2048 1 1024 1 512 1 256 1 128 1 64 1 32 1 16 1 8 1 4 1 2 0x301400 0x301412 I2S Register name Address Bit Name Function Setting Init R W Remarks I2S Control Register I2S_CTL 0x301400 16 bits D15 9 reserved 0 when being read D8 DTSIGN I2S signed unsigned data format select 1 Sig...

Page 689: ...IFOEF I2S FIFO empty flag 1 Empty 0 Not empty 1 R I2S Interrupt Control Register I2S_INT 0x30140c 16 bits D15 11 reserved 0 when being read D10 WEIF I2S FIFO whole empty int flag 1 Cause of interrupt occurred 0 Cause of interrupt not occurred 0 R W Reset by writing 1 D9 HEIF I2S FIFO half empty interrupt flag 1 0 0 R W D8 OEIF I2S FIFO one empty interrupt flag 1 0 0 R W D7 3 reserved 0 when being ...

Page 690: ...erved 0 when being read D1 0 PSAVE 1 0 Power save mode select PSAVE 1 0 Mode 0x0 R W 0x3 0x2 0x1 0x0 Normal reserved reserved Power save Horizontal Display Register LCDC_HDISP 0x302010 32 bits D31 23 reserved 0 when being read D22 16 HTCNT 6 0 Horizontal total period HT setup HT HDP HNDP HT HDPS HDP for HR TFT HT HTCNT 1 8 Ts HNDP HTCNT HDPCNT 8 Ts 0x0 R W D15 7 reserved 0 when being read D6 0 HDP...

Page 691: ...TL1 swap 1 Swap 0 Not swap 0 R W TFT_CTL1 Pulse Register LCDC_TFT_ CTL1 0x302044 32 bits D31 26 reserved 0 when being read D25 16 CTL1STP 9 0 TFT_CTL1 pulse stop offset TFT_CTL1 pulse width CTL1STP CTL1ST 1 Ts Stop offset CTL1STP 1 Ts 0x0 R W 2 For TFT This register is enabled when CTLCNT_RUN 1 D15 10 reserved 0 when being read D9 0 CTL1ST 9 0 TFT_CTL1 pulse start offset Start offset CTL1ST Ts 0x0...

Page 692: ...START31 MSB SW_START0 LSB 0x0 to 0xfffffffc Areas 3 5 7 10 13 16 and 19 22 0x0 R W Sub screen Address Offset Register LCDC_ SUBOFS 0x302084 32 bits D31 12 reserved 0 when being read D11 0 SW_OFS 11 0 Sub screen address offset Sub screen width pixels bpp 32 0x0 R W Sub window Start Position Register LCDC_SUBSP 0x302088 32 bits D31 PIP_EN PIP enable 1 Enable 0 Disable 0 R W D30 26 reserved 0 when be...

Page 693: ... Cannot be altered R DMAC Interrupt Enable Register DMAC_IE 0x302108 32 bits D31 8 reserved 0 when being read D7 DMAIE7 DMAC Ch 7 interrupt enable 1 Enable 0 Disable 0 R W D6 DMAIE6 DMAC Ch 6 interrupt enable 1 Enable 0 Disable 0 R W D5 DMAIE5 DMAC Ch 5 interrupt enable 1 Enable 0 Disable 0 R W D4 DMAIE4 DMAC Ch 4 interrupt enable 1 Enable 0 Disable 0 R W D3 DMAIE3 DMAC Ch 3 interrupt enable 1 Ena...

Page 694: ...N2 Ch 2 running status 1 Running 0 Idle paused 0 R D1 RUN1 Ch 1 running status 1 Running 0 Idle paused 0 R D0 RUN0 Ch 0 running status 1 Running 0 Idle paused 0 R DMAC Pause Status Register DMAC_ PAUSE_STAT 0x30211c 32 bits D31 8 reserved 0 when being read D7 PAUSE7 Ch 7 pause status 1 Paused 0 Not paused 0 R D6 PAUSE6 Ch 6 pause status 1 Paused 0 Not paused 0 R D5 PAUSE5 Ch 5 pause status 1 Pause...

Page 695: ...x302220 0x302228 SRAM Controller SRAMC Register name Address Bit Name Function Setting Init R W Remarks CE 7 4 Access Timing Configuration Register SRAMC_ TMG47 0x302220 32 bits D31 30 CE7SETUP 1 0 CE7 setup cycle CE7SETUP 1 0 Setup cycle 0x3 R W 0x3 0x2 0x1 0x0 4 cycles 3 cycles 2 cycles 1 cycle D29 28 CE7HOLD 1 0 CE7 hold cycle CE7HOLD 1 0 Hold cycle 0x3 R W 0x3 0x2 0x1 0x0 4 cycles 3 cycles 2 c...

Page 696: ...cycle D5 4 CE8HOLD 1 0 CE8 hold cycle CE8HOLD 1 0 Hold cycle 0x3 R W 0x3 0x0 4 cycles 1 cycle D3 0 CE8WAIT 3 0 CE8 static wait cycle CE8WAIT 3 0 Wait cycle 0xf R W 0xf 0x0 15 cycles 0 cycles CE 10 4 Device Configuration Register SRAMC_TYPE 0x302228 32 bits D31 14 reserved 0 when being read D13 12 CE10TYPE 1 0 CE10 device type CExTYPE 1 0 Device type 0x0 R W 0x3 0x2 0x1 0x0 8 bit device 16 bit BSL ...

Page 697: ... 0 Inactive X R Cache Write Buffer Status Register CCU_WB_ STAT 0x302318 32 bits D31 10 reserved 0 when being read D9 WEFINISH Write finish flag 1 Finished 0 Writing 1 R D8 WBEMPTY Write buffer empty flag 1 Empty 0 Full 1 R D7 0 reserved X 0 when being read CCLK Division Ratio Select Register CCU_ CCLKDV 0x302360 32 bits D31 2 reserved 0 when being read D1 0 CLK_ DOWN 1 0 CCLK division ratio selec...

Page 698: ...B boundary address Areas 3 5 7 10 13 16 and 19 22 0x0 R W D9 0 VWIN_ ADDR 9 0 Fixed at 0x0 Cannot be altered R VRAM Work Area Size Register GE_WK_SIZE 0x302454 32 bits D31 28 reserved 0 when being read D27 16 VWIN_H 11 0 Work area height Height VWIN_H 1 pixels 0x0 R W D15 12 reserved 0 when being read D11 0 VWIN_W 11 0 Work area width Width VWIN_W 1 pixels 0x1f R W Display Configuration Register G...

Page 699: ... 0xfff R W Cleared by writing any data D15 12 reserved 0 when being read D11 0 UPDT_UPL _X 11 0 Updated area upper left corner X coordinate 0 to 4 095 0xfff R W Cleared by writing any data Updated Area End Position Register GE_UPDT_ END 0x302474 32 bits D31 28 reserved 0 when being read D27 16 UPDT_LWR _Y 11 0 Updated area lower right corner Y coordinate 0 to 4 095 0x0 R W Cleared by writing any d...

Page 700: ...ur rent consumed Selecting a low system clock CMU module The CMU module provides a clock divider to set the system clock speed to 1 1 to 1 32 of the source clock OSC3 PLL OSC1 By running the S1C33L26 with the lowest speed required for the application s task current consumption can be reduced CPU clock CCLK Executing the halt instruction Execute the halt instruction if there is no task to be proces...

Page 701: ...r LCDC bus interface Clock management unit CMU registers Bus arbiters Can be stopped in HALT mode Table B 2 lists the clock control conditions and how to suspend resume the CPU operation 2 List of Clock Control Conditions Table B Current con sumption OSC1 OSC3 PLL CPU CCLK Peripherals CPU suspending method CPU resuming method Low Oscillating Stop Stop Stop slp instruction 1 Oscillating Stop Stop S...

Page 702: ...system power and RTCVDD power sources it is possible to operate only the RTCVDD system circuits RTC OSC1 and BBRAM with the system power turned off to reduce current consumption Turning the system power off reduces leakage current that cannot be reduced in SLEEP mode The STBY and WAKEUP pins that have been provided in the RTC module are used for controlling this function Refer to the Real Time Clo...

Page 703: ...al lines on other layers Never place digital signal lines alongside such components or wiring even if more than 3 mm distance or located on other layers Avoid crossing wires 3 Use VSS to shield RTCCLKI MCLKI and RTCCLKO MCLKO pins and related wiring including wiring for adjacent circuit board layers Layers wired should be adequately shielded as shown to the right Fully ground adjacent layers where...

Page 704: ...rter is not used the power supply pin AVDD for the analog system should be connected to HVDD Signal line location To prevent electromagnetically induced noise arising from mutual induction large current signal lines should not be positioned close to circuits susceptible to noise such as oscillators Locating signal lines in parallel over significant distances or crossing signal lines operating at h...

Page 705: ...lso created for the internal layer immediately below that In particular the routing of high speed digital sig nal lines parallel to or across these signal lines should be avoided as much as possible We recommend that you verify the EYE pattern on the actual circuit board Noise induced malfunctions Check the following five points if you suspect the presence of noise induced IC malfunctions 1 TEST p...

Page 706: ...e potential noise keep the following two points in mind when designing circuit boards A It is important to lower the signal driving impedance as described above Connect pins to the power supply or GND with impedance of 1 kΩ or less preferably 0 Ω The signal lines connected should be no longer than approximately 5 mm B Parallel routing of signal lines with other digital lines on the board is undesi...

Page 707: ...e form of voltages exceeding the absolute maximum rating when mounting the product in addition to physical damage The following factors can give rise to these variations 1 Electromagnetically induced noise from industrial power supplies used in mounting reflow reworking after mounting and individual characteristic evaluation testing processes 2 Electromagnetically induced noise from a solder iron ...

Page 708: ...evel to 1 or 0 NOR Flash External ROM Boot D 2 Configuration of NOR Flash External ROM Boot System D 2 1 When the S1C33L26 is turned on or reset with the BOOT pin set to 0 VSS the S1C33L26 reads the reset vector from address 0x20000000 in the external NOR Flash or external ROM and jumps to the user reset handler routine This boot sequence is similar to the standard function of the C33 PE Core Howe...

Page 709: ...he reset vector is 0 4 Reads the reset vector again and jumps to that address Figures D 2 2 2 and D 2 2 3 show 16 bit and 8 bit NOR Flash boot sequences CE10 RD A 25 0 D 15 0 C00000 C00002 20000000 P 15 0 P 31 16 20000000 20000002 P 15 0 P 31 16 P P 2 P 15 0 Dummy read Reset vector read Jump to P LSB check Bus size configuration 2 2 2 16 bit NOR Flash Boot Figure D CE10 RD A 25 0 D 7 0 C00000 C000...

Page 710: ... up with external resistors as the CE10 P53 inter nal pull up resistor is disabled 3 1 1 SPI EEPROM Boot System Figure D 3 1 1 Pins Used for SPI EEPROM Boot Table D S1C33L26 pin EEPROM pin Pin status before booting Pin status after booting P02 USI_CS SCLK1 REMC_O CS Input High output P00 USI_DI SIN1 NAND_WR Q Input Input P01 USI_DO SOUT1 NAND_RD D Input Output P03 USI_CK SRDY1 REMC_I CLK Input Low...

Page 711: ...t functions Switches CE10 pin to P53 input Initializes TTBR 0x20000000 WIP bit 1 0 P53 CE10 0 To PC RS232C boot sequence 1 Loads 512 byte executable code Issues 32 bit address 3 2 1 SPI EEPROM Boot Flowchart Figure D 1 When the BOOT and P53 CE10 pins are set to 1 at power on or reset the SPI EEPROM boot sequence is executed 2 The boot sequence configures the port and the USI module 3 Issues the RD...

Page 712: ...herefore MBR codes must be followed by an appropriate offset The boot sequence ignores the offset bytes Table D 3 3 1 and Figure D 3 3 1 show the data locations according to the EEPROM size 3 3 1 EEPROM Size and Address Size Table D EEPROM size Address size MBR data location 1 to 256 bytes 1 byte 4th byte to 256th byte 0 25K to 64K bytes 2 bytes 3rd byte to 514th byte 64K to 16M bytes 3 bytes 2nd ...

Page 713: ...I EEPROM boot or PC RS232C boot during boot mode configuration with the BOOT pin The pins listed in the table are configured for FSIO Ch 1 pin names in boldface in the boot sequence Therefore these pins cannot be used for general purpose I O or other peripheral functions The baud rate and RS232C parameters are configured as below in the boot sequence Baud rate Automatically detected 9600 bps typ N...

Page 714: ...ecutable code for verification Initializes FSIO Ch 1 4 2 1 PC RS232C Boot Flowchart Figure D 1 When the BOOT pin is set to 1 and the P53 CE10 pin is set to 0 at power on or reset the PC RS232C boot sequence is executed 2 The boot sequence configures the port and the T16A5 Ch 0 3 Waits for the P00 SIN1 input pulled down to 0 start bit When a start bit is input the boot sequence starts T16A5 Ch 0 to...

Page 715: ...a after verifying the 4 byte chip ID code received from the S1C33L26 The S1C33L26 calculates the baud rate by counting the 4 bytes of 0x80 received from the PC and configures its serial interface Then the S1C33L26 sends the 4 byte chip ID code to the PC After the 512 byte MBR data is re ceived the S1C33L26 returns it to the PC for verification Figure D 4 3 1 shows the transfer data 1st byte 512 by...

Page 716: ...section in the Reset and NMI chapter for the power on reset time Power supply Power off sequence Old Power off 3 LVDD PLLVDD and RTCVDD May be turned off with 1 above at the same time Notes Applying only HVDD makes a diode circuit on the path from HVDD to AVDD Be sure to avoid applying AVDD degraded due to flow through current of the AVDD New Power off 3 LVDD PLLVDD and RTCVDD May be turned off wi...

Page 717: ...al data transfer set SMSKEN to 0 default to disable the receive data mask function New Deleted 18 7 USI Data transfer in UART mode Data reception Old If the subsequent receive data is written to the receive data buffer when URDIF is 1 an overrun er ror occurs New If the next reception is completed an overrun error occurs at the time stop bit has been received 18 8 USI Data receiving timing chart U...

Page 718: ...r occurs write 0x0 to USIMOD 2 0 USI_GCFG register to initialize USI 18 28 18 29 AP A 26 USI USI SPI Master Slave Mode Configuration Register USI_SCFG Old D1 SMSKEN Receive Data Mask Enable Bit New D1 Reserved Do not set to 1 18 30 USI USI SPI Master Slave Mode Interrupt Flag Register USI_SIF D2 SEIF Overrun Error Flag Bit Old An overrun error occurs when the previous received data SEIF is reset b...

Page 719: ...t ISSTA 2 0 to 0x0 19 20 USIL I2C slave data transmission timing chart Modified Figure 19 5 3 12 19 22 USIL I2C slave data receiving timing chart Modified Figure 19 5 3 14 19 23 USIL Data Transmission in LCD SPI Mode Old The LSBSY flag indicates the USIL status the LCD SPI controller is operating or at standby New The LSBSY flag indicates the USIL status LSDMOD 1 0 USIL_LSDCFG register has complet...

Page 720: ... 1 to SEIF and reads USIL_RD register twice can be reversed 19 41 USIL USIL I2C Master Mode Interrupt Flag Register USIL_IMIF D 4 2 IMSTA 2 0 I2C Master Status Bits Old When an operation completion interrupt occurs the operation that has been finished New the operation that has been finished IMSTA 2 0 is automatically reset to 0x0 by writing 1 to IMIF USIL USIL I2C Master Mode Interrupt Flag Regis...

Page 721: ...et to 1 New This bit is valid when the InSUSPEND bit of the USB_Control register is set to 1 This bit is valid during snooze as well 31 1 Electrical characteristics Absolute maximum rating Old No description New 2 The maximum input voltage range of the STBY pin is VSS 0 3 V to 4 0 V Electrical characteristics Recommended operating conditions Old No description New 1 HVDD AVDD LVDD RTCVDD PLLVDD LV...

Page 722: ...28 Fax 86 755 2699 3838 EPSON HONG KONG LTD 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Phone 852 2585 4600 Fax 852 2827 4346 Telex 65542 EPSCO HX EPSON TAIWAN TECHNOLOGY TRADING LTD 14F No 7 Song Ren Road Taipei 110 TAIWAN Phone 886 2 8786 6688 Fax 886 2 8786 6660 EPSON SINGAPORE PTE LTD 1 HarbourFront Place 03 02 HarbourFront Tower One Singapore 098633 Phone 65 6586 5500 Fax 65 6271 31...

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