EMR-5000
IM02602012E
Name
Description
Logic.LE62.Gate In2-I
State of the module input: Assignment of the Input Signal
Logic.LE62.Gate In3-I
State of the module input: Assignment of the Input Signal
Logic.LE62.Gate In4-I
State of the module input: Assignment of the Input Signal
Logic.LE62.Reset Latch-I
State of the module input: Reset Signal for the Latching
Logic.LE63.Gate Out
Signal: Output of the logic gate
Logic.LE63.Timer Out
Signal: Timer Output
Logic.LE63.Out
Signal: Latched Output (Q)
Logic.LE63.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE63.Gate In1-I
State of the module input: Assignment of the Input Signal
Logic.LE63.Gate In2-I
State of the module input: Assignment of the Input Signal
Logic.LE63.Gate In3-I
State of the module input: Assignment of the Input Signal
Logic.LE63.Gate In4-I
State of the module input: Assignment of the Input Signal
Logic.LE63.Reset Latch-I
State of the module input: Reset Signal for the Latching
Logic.LE64.Gate Out
Signal: Output of the logic gate
Logic.LE64.Timer Out
Signal: Timer Output
Logic.LE64.Out
Signal: Latched Output (Q)
Logic.LE64.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE64.Gate In1-I
State of the module input: Assignment of the Input Signal
Logic.LE64.Gate In2-I
State of the module input: Assignment of the Input Signal
Logic.LE64.Gate In3-I
State of the module input: Assignment of the Input Signal
Logic.LE64.Gate In4-I
State of the module input: Assignment of the Input Signal
Logic.LE64.Reset Latch-I
State of the module input: Reset Signal for the Latching
Logic.LE65.Gate Out
Signal: Output of the logic gate
Logic.LE65.Timer Out
Signal: Timer Output
Logic.LE65.Out
Signal: Latched Output (Q)
Logic.LE65.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE65.Gate In1-I
State of the module input: Assignment of the Input Signal
Logic.LE65.Gate In2-I
State of the module input: Assignment of the Input Signal
Logic.LE65.Gate In3-I
State of the module input: Assignment of the Input Signal
Logic.LE65.Gate In4-I
State of the module input: Assignment of the Input Signal
Logic.LE65.Reset Latch-I
State of the module input: Reset Signal for the Latching
Logic.LE66.Gate Out
Signal: Output of the logic gate
Logic.LE66.Timer Out
Signal: Timer Output
Logic.LE66.Out
Signal: Latched Output (Q)
Logic.LE66.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE66.Gate In1-I
State of the module input: Assignment of the Input Signal
Logic.LE66.Gate In2-I
State of the module input: Assignment of the Input Signal
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