EMR-5000
IM02602012E
Name
Description
Logic.LE17.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE17.Gate In1-I
State of the module input: Assignment of the Input Signal
Logic.LE17.Gate In2-I
State of the module input: Assignment of the Input Signal
Logic.LE17.Gate In3-I
State of the module input: Assignment of the Input Signal
Logic.LE17.Gate In4-I
State of the module input: Assignment of the Input Signal
Logic.LE17.Reset Latch-I
State of the module input: Reset Signal for the Latching
Logic.LE18.Gate Out
Signal: Output of the logic gate
Logic.LE18.Timer Out
Signal: Timer Output
Logic.LE18.Out
Signal: Latched Output (Q)
Logic.LE18.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE18.Gate In1-I
State of the module input: Assignment of the Input Signal
Logic.LE18.Gate In2-I
State of the module input: Assignment of the Input Signal
Logic.LE18.Gate In3-I
State of the module input: Assignment of the Input Signal
Logic.LE18.Gate In4-I
State of the module input: Assignment of the Input Signal
Logic.LE18.Reset Latch-I
State of the module input: Reset Signal for the Latching
Logic.LE19.Gate Out
Signal: Output of the logic gate
Logic.LE19.Timer Out
Signal: Timer Output
Logic.LE19.Out
Signal: Latched Output (Q)
Logic.LE19.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE19.Gate In1-I
State of the module input: Assignment of the Input Signal
Logic.LE19.Gate In2-I
State of the module input: Assignment of the Input Signal
Logic.LE19.Gate In3-I
State of the module input: Assignment of the Input Signal
Logic.LE19.Gate In4-I
State of the module input: Assignment of the Input Signal
Logic.LE19.Reset Latch-I
State of the module input: Reset Signal for the Latching
Logic.LE20.Gate Out
Signal: Output of the logic gate
Logic.LE20.Timer Out
Signal: Timer Output
Logic.LE20.Out
Signal: Latched Output (Q)
Logic.LE20.Out inverted
Signal: Negated Latched Output (Q NOT)
Logic.LE20.Gate In1-I
State of the module input: Assignment of the Input Signal
Logic.LE20.Gate In2-I
State of the module input: Assignment of the Input Signal
Logic.LE20.Gate In3-I
State of the module input: Assignment of the Input Signal
Logic.LE20.Gate In4-I
State of the module input: Assignment of the Input Signal
Logic.LE20.Reset Latch-I
State of the module input: Reset Signal for the Latching
Logic.LE21.Gate Out
Signal: Output of the logic gate
Logic.LE21.Timer Out
Signal: Timer Output
Logic.LE21.Out
Signal: Latched Output (Q)
Logic.LE21.Out inverted
Signal: Negated Latched Output (Q NOT)
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