Datex-Ohmeda Aestiva 7900 SmartVent, Service Manual

Page: 34 / 181

2/Theory of Operation
2-16 1503-0151-000 3/27/97
Software Watchdog Timer
The software controlled internal watchdog timer guards against program execution
going astray.
External Bus Interface
The external bus interface handles the transfer of information between the CPU32,
external memory and peripherals.
Chip Selects
The four programmable chip selects access external memory and peripheral cir-
cuits, providing handshaking and timing signals as well as a wait state generation.
I/O Lines
Spare I/O lines are used for digital control and/or sense lines.
Timer Modules
Counter/Timer #1
The first counter/timer module is used to monitor the 68340 system clock frequen-
cy. The external 3.6864 MHz baud rate clock is the time base for this measure-
ment.
Counter/Timer #2
The second counter/timer module can be used as desired by the application soft-
ware. The time base for this timer is the internal 24.11 MHz system clock.
Serial Communications Module
Timing Reference
An external 3.6864 MHz clock oscillator serves as the basic timing reference for
the Baud Rate Generator.
Configuration
Both of the serial communication channels are configured as full-duplex asynchro-
nous RS232C ports. The internal Baud Rate Generator establishes the communi-
cation baud rate, with an upper limit of 38.4k Baud.
Special Operating Modes
The serial channels are capable of operating in various looping modes for self test-
ing as well as for remote testing of serial communications. These tests include au-
tomatic echo, local loop-back, and remote loop-back.