Cypress enCoRe V CY7C643 Series, Technical Reference Manual

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enCoRe™ V CY7C643xx, enCoRe™ V LV CY7C604xx TRM, Document No. 001-32519 Rev *H 6
Contents
11.3.3 SLP_CFG2 Register .............................................................................................83
11.3.4 SLP_CFG3 Register .............................................................................................83
11.3.5 Related Registers ..................................................................................................83
11.4 Timing Diagrams.....................................................................................................................84
11.4.1 Sleep Sequence.....................................................................................................84
11.4.2 Wakeup Sequence.................................................................................................85
11.4.3 Bandgap Refresh ...................................................................................................85
11.4.4 Watchdog Timer.....................................................................................................86
11.5 ................................................................................................................................................86
12. Regulated I/O 87
12.1 Architectural Description.........................................................................................................87
12.1.1 Bias Generator.......................................................................................................88
12.1.2 Charge Pump.........................................................................................................88
12.1.3 Comparator ............................................................................................................88
12.1.4 Replica Structure....................................................................................................88
12.1.5 Pass Transistors ....................................................................................................88
12.2 Application Overview ..............................................................................................................88
12.3 Register Definitions.................................................................................................................89
12.3.1 IO_CFG1 Register .................................................................................................89
12.3.2 IO_CFG2 Register .................................................................................................89
13. I/O Analog Multiplexer 90
13.1 Architectural Description.........................................................................................................90
13.2 Register Definitions.................................................................................................................91
13.2.1 MUX_CRx Registers..............................................................................................91
Section C: System Resources 92
14. Digital Clocks 96
14.1 Architectural Description.........................................................................................................96
14.1.1 Internal Main Oscillator ..........................................................................................96
14.1.2 Internal Low-speed Oscillator ................................................................................96
14.1.3 External Clock........................................................................................................97
14.2 Register Definitions.................................................................................................................99
14.2.1 USB_MISC_CR Register ......................................................................................99
14.2.2 OUT_P1 Register ..................................................................................................99
14.2.3 OSC_CR0 Register .............................................................................................101
14.2.4 OSC_CR2 Register .............................................................................................102
15. I
2
C Slave 103
15.1 Architectural Description.......................................................................................................103
15.1.1 Basic I
2
C Data Transfer .......................................................................................104
15.2 Application Overview ............................................................................................................105
15.2.1 Slave Operation ...................................................................................................105
15.3 Register Definitions...............................................................................................................106
15.3.1 I2C_XCFG Register .............................................................................................106
15.3.2 I2C_ADDR Register.............................................................................................106
15.3.3 I2C_CFG Register ..............................................................................................107
15.3.4 I2C_SCR Register ..............................................................................................109
15.3.5 I2C_DR Register .................................................................................................110
15.4 Timing Diagrams...................................................................................................................111
15.4.1 Clock Generation ................................................................................................. 111
15.4.2 Basic I/O Timing................................................................................................... 111