enCoRe™ V CY7C643xx, enCoRe™ V LV CY7C604xx TRM, Document No. 001-32519 Rev *H
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CPU Core (M8C)
2.6
Register Definitions
The following register is associated with the CPU Core (M8C). The register description has an associated register table show-
ing the bit structure. The bits that are grayed out in the table are reserved bits and are not detailed in the register description
that follows. Always write reserved bits with a value of ‘0’.
2.6.1
CPU_F Register
The M8C Flag Register (CPU_F) provides read access to
the M8C flags.
Bits 7 and 6: PgMode[1:0].
PgMode determines how the
CUR_PP, STK_PP, and IDX_PP registers are used in form-
ing effective RAM addresses for Direct Address mode and
Indexed Address mode operands. PgMode also determines
whether the stack page is determined by the STK_PP or
IDX_PP register. (See the
Register Definitions on page 41
in
the RAM Paging chapter.)
Bit 4: XIO.
The I/O bank select bit, also known as the regis-
ter bank select bit, is used to select the register bank that is
active for a register read or write. This bit allows the enCoRe
V device to have 512 8-bit registers and is thought of as the
ninth address bit for registers. The address space accessed
when the XIO bit is set to ‘0’ is called
, while
address space accessed when the XIO bit is set to ‘1’ is
called
.
Bit 2: Carry.
The Carry flag bit is set or cleared in response
to the result of several instructions. It is also manipulated by
the flag logic opcodes (for example, OR F, 4). See the
PSoC
Designer Assembly Language User Guide
for more details.
Bit 1: Zero.
The Zero flag bit is set or cleared in response
to the result of several instructions. It is also manipulated by
the flag logic opcodes (for example, OR F, 2). See the
PSoC
Designer Assembly Language User Guide
for more details.
Bit 0: GIE.
The state of the Global Interrupt Enable bit
determines whether interrupts (by way of the interrupt
request (IRQ)) are recognized by the M8C. This bit is set or
cleared using the flag logic instructions (for example, OR F,
1). GIE is also automatically cleared when an interrupt is
processed, after the flag byte is stored on the stack, pre-
venting nested interrupts. If wanted, set the bit in an
. For GIE=1, the M8C samples
the IRQ input for each instruction. For GIE=0, the M8C
ignores the IRQ.
For additional information, refer to the
2.6.2
Related Registers
The following registers are related to the M8C block:
■
■
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Access
x,F7h
PgMode[1:0]
XIO
Carry
Zero
GIE
RL : 02
Legend
L The AND F, expr; OR F, expr; and XOR F, expr flag instructions can be used to modify this register.
x An “x” before the comma in the address field indicates that this register can be read or written to no matter what bank is used.
