Cypress enCoRe V CY7C643 Series, Technical Reference Manual

Page: 70 / 257

enCoRe™ V CY7C643xx, enCoRe™ V LV CY7C604xx TRM, Document No. 001-32519 Rev *H 70
Internal Main Oscillator (IMO)
8.5 Clocking Strategy
No clocks are needed for this block integration in the chip.
8.6 Usage Guidelines
Oscillator clock frequency is adjusted to it operating fre-
quency at a given process corner using the trim bits of the
DAC.
8.6.1 Power Down Guidelines
The 36 MHz oscillators for SPC control shares resources
with main oscillator, therefore, 36 MHz clock has to be pow-
ered down prior to main oscillator is powered down. The PD
applied to the main oscillator will power down the 36MHz
output but the state of the SPC clock may not be known as it
powers down the entire circuit when SYSCLK clock goes
low irrespective of the state of the SPC clock. This ensures
circuit powers down when state of the clock is low.
Current/Voltage Reference guidelines.
Output clock frequency is very sensitive to band gap refer-
ence current source. A trimmed (over process corner) and
stable (across V-T) current reference/voltage reference
should be used for stable output frequency.
A high accuracy current reference of 10 µA is required. The
accuracy of oscillator largely depends on the accuracy of
the current reference input.Prerequisite IP
8.7 Block Size/Area
8.8 Gate Count
8.9 Block Pin List
8.10 Block Level Interfaces
8.11 Initialization
8.12 Wounding
This block cannot be wounded.
8.13 On-Chip Debugger Modes
There are no on-chip debugger modes associated with this
block.
8.14 Test Modes
There are no test modes associated with this block.
8.15 Power Modes
8.16 Design Flow
This block uses an analog design flow.
Table 8-2. IMO Block Size
BROS BR1 BR2 BR3 BR4
Block Size
(um x um)
Block Area
(um
2
)
Table 8-3. IMO Gate Count
BROS BR1 BR2 BR3 BR4
Gate Count
Table 8-4. IMO Signals
Name Type Direction Description
General
vpwr Supply Input Power Supply
vgnd Supply Input Ground
F2xOFF CMOS Input
Powers down the frequency dou-
bler. Active High.
RESET CMOS Input
Reset, forces clock outputs to
ground. Active High.
V
REF1
Analog Input 0.6V voltage reference
V
REF2
Analog Input 1.2V voltage reference
I
IN
Analog Input
Bandgap current reference
used as input to the DAC
PDC CMOS Input
System-wide power down. Pow-
ers down CLKout and Doubler.
Active High.
PDX CMOS Input
Powers down CLKout and Dou-
bler. Active High.
XCLK CMOS Input External clock input
XCSEL CMOS Input
CLKMUX control. Selects XCLK
when set high
SYSCLK CMOS Output 6/12 MHz clock output
SYSCLKx2 CMOS Output Doubled (12/24 MHz) clock output