enCoRe™ V CY7C643xx, enCoRe™ V LV CY7C604xx TRM, Document No. 001-32519 Rev *H
118
System Resets
16.4
Timing Diagrams
16.4.1
Power-On-Reset
A power-on-reset (POR) is triggered whenever the supply
voltage is below the POR trip point. POR ends when the
supply voltage rises above this voltage. Refer to the
operation of the POR block.
POR consists of two pieces: an Imprecise POR (IPOR) and
a Precision POR (PPOR). POR refers to the OR of these
two functions. IPOR has coarser accuracy and its trip point
is typically lower than PPOR’s trip point. PPOR is derived
from a circuit that is calibrated (during boot) for a very accu-
rate location of the POR trip point.
During POR (POR=1), the IMO is powered off for low power
during startup. After POR deasserts, the IMO is started (see
POR configures register reset status bits, as shown in
16.4.4 Reset Details on page 120
16.4.2
External Reset
An external reset (XRES) is caused by pulling the XRES pin
high. The XRES pin has an always-on, pull-down resistor,
so it does not require an external pull down for operation
and can be tied directly to ground or left open. Behavior after
XRES is similar to POR. In reset, shifting key AC52h (with
MSB shifted in first) onto ISSP bus lines can lead to perma-
nent chip damage. This is possible because, upon reception
of key AC52h, the chip enters a test mode in which the inter-
nal regulator is bypassed and the core powered with a
higher voltage than specified. For this reason, avoid shifting
key AC52h while in reset.
During XRES (XRES=1), the IMO is powered off for low
power during startup. After XRES deasserts, the IMO is
started (see
).
16.4.4 Reset Details on page 120
shows how the XRES
configures register reset status bits.
16.4.3
Watchdog Timer Reset
You can enable the Watchdog Timer Reset (WDR), by clear-
ing the PORS bit in the CPU_SCR0 register. After the PORS
bit is cleared, the watchdog timer cannot be disabled. The
only exception to this is if a POR/XRES event takes place,
which disables the WDR. Note that a WDR does not clear
the watchdog timer. See
for
details of the watchdog operation.
When the watchdog timer expires, a watchdog event occurs,
resulting in the reset sequence. Some characteristics
unique to the WDR are as follows.
■
enCoRe V device reset asserts for one cycle of the
CLK32K clock (at its reset state).
■
The IMO is not halted during or after WDR (that is, the
part does not go through a low-power phase).
■
CPU operation re-starts one CLK32K cycle after the
internal reset deasserts (see
16.4.4 Reset Details on page 120
shows how the WDR con-
figures register reset status bits.
Figure 16-3. Key Signals During WDR
CLK32
Reset
Sleep Timer
IMO PD
IMO (not to scale)
CPU Reset
0
1
2
N=2048
IRES
: Reset 1 cycle, then 2048 additional cycles low power hold-off, and then 1
cycle with IMO on before the CPU reset is released.
WDR
: Reset 1 cycle, then one additional cycle before the CPU reset is released.
IMO PD
IMO (not to scale)
CPU Reset
(Stays low)
Reset
Sleep Timer
0
1
2
CLK32
