Cypress enCoRe V CY7C643 Series, Technical Reference Manual

Page: 139 / 257

enCoRe™ V CY7C643xx, enCoRe™ V LV CY7C604xx TRM, Document No. 001-32519 Rev *H 139
Programmable Timer
19.2 Register Definitions
The following registers are associated with the Programmable Timer and are listed in address order. The register descriptions
have an associated register table showing the bit structure for that register. The bits in the tables that are grayed out are
reserved bits and are not detailed in the register descriptions that follow. Reserved bits must always be written with a value of
‘0’. For a complete table of programmable timer registers, refer to the
Summary Table of the System Resource Registers on
page 93 .
19.2.1 PT0_CFG Register
The Programmable Timer Configuration Register
(PT0_CFG) configures the enCoRe V’s programmable
timer.
Bit 2: CLKSEL. This bit determines if the timer runs on the
32-kHz clock or CPU clock. If the bit is set to 1, the timer
runs on the CPU clock, otherwise, the timer runs on the 32-
kHz clock.
Bit 1: One Shot. This bit determines if the timer runs in
one-shot mode or continuous mode. In one-shot mode the
timer completes one full count cycle and terminates. Upon
termination, the START bit in this register is cleared. In con-
tinuous mode, the timer reloads the count value each time
upon completion of its count cycle and repeats.
Bit 0: START. This bit starts the timer counting from a full
count. The full count is determined by the value loaded into
the data registers. This bit is cleared when the timer is run-
ning in one-shot mode upon completion of a full count cycle.
For additional information, refer to the PT0_CFG register on
page 181 .
19.2.2 PT1_CFG Register
The Programmable Timer Configuration Register
(PT1_CFG) configures the enCoRe V’s programmable
timer.
Bit 2: CLKSEL. This bit determines if the timer runs on the
32-kHz clock or CPU clock. If the bit is set to ‘1’, the timer
runs on the CPU clock, otherwise, the timer runs on the 32-
kHz clock.
Bit 1: One Shot. This bit determines if the timer runs in
one-shot mode or continuous mode. In one-shot mode the
timer completes one full count cycle and terminates. Upon
termination, the START bit in this register is cleared. In con-
tinuous mode, the timer reloads the count value each time
upon completion of its count cycle and repeats.
Bit 0: START. This bit starts the timer counting from a full
count. The full count is determined by the value loaded into
the data registers. This bit is cleared when the timer is run-
ning in one-shot mode upon completion of a full count cycle.
For additional information, refer to the PT1_CFG register on
page 184 .
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access
0,B0h PT0_CFG CLKSEL One Shot START RW : 0
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access
0,B3h PT1_CFG CLKSEL One Shot START RW : 0