enCoRe™ V CY7C643xx, enCoRe™ V LV CY7C604xx TRM, Document No. 001-32519 Rev *H
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1,DDh
21.4.14 OUT_P1
Output Override to Port 1 Register
This register enables specific internal signals to be output to Port 1 pins.
The GPIO drive modes must be specified to support the desired output mode (registers PRT1DM1 and PRT1DM0). If a pin is
enabled for output by a bit in this register, the corresponding signal has priority over any other internal function that may be
configured to output to that pin. Reserved bits must always be written with a value of ‘0’.
For additional information, refer to the
Register Definitions on page 99
in the Digital Clocks chapter.
7
P16D
Bit selects the data output to P1[6] when P16EN is high.
0
Select Timer output (TIMEROUT)
1
Select CLK32
6
P16EN
Bit enables pin P1[6] for output of the signal selected by the P16D bit.
0
No internal signal output to P1[6]
1
Output the signal selected by P16D to P1[6]
2
P12EN
Bit enables pin P1[2] to output the main system clock (SYSCLK).
0
No internal signal output to P1[2]
1
Output SYSCLK to P1[2]
(continued on next page)
Individual Register Names and Addresses:
1,DDh
OUT_P1: 1,DDh
7
6
5
4
3
2
1
0
Access : POR
RW : 0
RW : 0
RW : 0
RW : 0
Bit Name
P16D
P16EN
RSVD
RSVD
RSVD
P12EN
RSVD
P10EN
Bit
Name
Description
