enCoRe™ V CY7C643xx, enCoRe™ V LV CY7C604xx TRM, Document No. 001-32519 Rev *H
218
1,54h
21.4.7
EPx_CR0
Endpoint Control Registers 0
These registers endpoint control registers.
In the table, note that the reserved bit is a grayed table cell and is not described in the bit description section. Reserved bits
must always be written with a value of ‘0’. For additional information, refer to the
Register Definitions on page 147
Speed USB chapter.
7
Stall
When this bit is set, the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls
an IN packet if the Mode bits are set to ACK-IN. This bit must be clear for all other modes.
5
NAK_INT_EN
When set, this bit causes an endpoint interrupt to be generated even when a transfer completes with
a NAK.
4
ACKed Tx
The ACKed transaction bit is set whenever the SIE engages in a transaction to the register's endpoint
that completes with an ACK packet.
3:0
Mode[3:0]
The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of
that endpoint as a result of host packets to the endpoint.
Individual Register Names and Addresses:
1,54h
EP1_CR0 : 1,54h
EP2_CR0 : 1,55h
EP3_CR0 : 1,56h
EP4_CR0 : 1,57h
EP5_CR0 : 1,58h
EP6_CR0 : 1,59h
EP7_CR0 : 1,5Ah
EP7_CR0 : 1,5Bh
7
6
5
4
3
2
1
0
Access : POR
RW : 0
RW : 0
RC : 0
RW : 0
Bit Name
Stall
NAK_INT_EN
ACKed Tx
Mode[3:0]
Bit
Name
Description
