enCoRe™ V CY7C643xx, enCoRe™ V LV CY7C604xx TRM, Document No. 001-32519 Rev *H
10
Top-Level Architecture
The
enCoRe
V
block
diagram
on
the
next
page
illustrates
the
top-level
architecture
of
the
CY8C20X46A/46AS/96A/46L/96LCY7C643xx and CY7C604xx devices. Each major grouping in the diagram is covered in this
manual in its own section: enCoRe V Core and System Resources. Banding these two main areas together is the communica-
tion network of the system
.
enCoRe V Core
The enCoRe V Core is a powerful engine that supports a rich instruction set. It includes the
for data storage, an
controller for easy program execution to new addresses, sleep and watchdog timers, a regulated 3.0-V output option for
Port 1 I/Os, and multiple
sources that include the IMO (internal main oscillator) and ILO (internal low-speed oscillator)
for precision, programmable clocking.
The CPU core, called the M8C, is a powerful processor with speeds up to 24 MHz. The M8C is a four MIPS 8-
Harvard
architecture microprocessor. Within the CPU core are the
memory components that provide flexible pro-
gramming.
enCoRe V GPIOs provide connection to the CPU and external resources of the device. Each pin’s drive mode is selectable
from four options, allowing great flexibility in external interfacing. Every pin also has the capability to generate a system inter-
rupt on low level and change from last read.
System Resources
The System Resources provide additional enCoRe V capability. These system resources include:
■
Digital clocks to increase flexibility.
■
I2C functionality with “no bus stalling.”
■
Various system resets supported by the M8C.
■
Power-on-reset (POR) circuit protection.
■
SPI master and slave functionality.
■
A programmable timer to provide periodic interrupts.
■
Clock boost network providing a stronger signal to switches.
■
Full-speed USB interface for USB 2.0 communication with 512 bytes of dedicated buffer memory and an internal 3-V reg-
ulator.
