enCoRe™ V CY7C643xx, enCoRe™ V LV CY7C604xx TRM, Document No. 001-32519 Rev *H
231
1,E3h
21.4.19 VLT_CR
Voltage Monitor Control Register
This register is used to set the trip points for POR and LVD.
In the table, note that reserved bits are grayed table cells and are not described in the bit description section. Reserved bits
must always be written with a value of ‘0’. For additional information, refer to the
Register Definitions on page 122
in the POR
chapter.
7
HPOR
This bit along with PORLEV sets one of the four values for the PPOR trip voltage. See
.
See the “DC POR and LVD Specifications” table in the Electrical Specifications section of the enCoRe
V device datasheet for voltage tolerances for each setting.
5:4
PORLEV[1:0]
These bits along with HPOR sets one of the four values for the PPOR trip voltage. See
3
LVDTBEN
Enables reset of the CPU speed register by LVD comparator output.
2:0
VM[2:0]
Sets the LVD levels per the DC Electrical Specifications in the enCoRe V device datasheet, for those
devices with this feature.
000b
Lowest voltage setting.
001b
010b
011b
100b
101b
110b
111b
Highest voltage setting.
Individual Register Names and Addresses:
1,E3h
VLT_CR: 1,E3h
7
6
5
4
3
2
1
0
Access : POR
RW : 0
RW : 0
RW : 0
RW : 0
Bit Name
HPOR
PORLEV[1:0]
LVDTBEN
VM[2:0]
Bit
Name
Description
Table 21-1. PPOR Range Setting
HPOR, PORLEV[1:0]
(VLT_CR[7], VLT_CR[5:4])
Typical PPOR Trip Voltage
000b
1.66 V
001b, 010b, 011b
Do not use
100b
2.36 V
101b
2.60 V
110b
2.82 V
111b
Do not use
