enCoRe™ V CY7C643xx, enCoRe™ V LV CY7C604xx TRM, Document No. 001-32519 Rev *H
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RAM Paging
4.2.6
MVW_PP Register
The MVI Write Page Pointer Register (MVW_PP) sets the
effective SRAM page for MVI write memory accesses in a
multi-SRAM page enCoRe V device.
Bits 2 to 0: Page Bits[2:0].
These bits are only used by
the
MVI [expr], A
instruction, not to be confused with the
MVI A, [expr]
instruction covered by the MVR_PP regis-
ter. This instruction is considered a write because data is
transferred from the microprocessor's A register (CPU_A) to
SRAM.
When an
MVI [expr], A
instruction is executed in a
device with more than one page of SRAM, the SRAM
address that is written by the instruction is determined by
the value of the least significant bits in this register. How-
ever, the pointer for the
MVI [expr], A
instruction is
always located in the current SRAM page. See the
PSoC
Designer Assembly Language User Guide
for more informa-
tion on the
MVI [expr], A
instruction.
The function of this register and the MVI instructions are
independent of the SRAM Paging bits in the CPU_F register.
For additional information, refer to the
4.2.7
Related Registers
■
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Access
0,D5h
Page Bits[2:0]
RW : 0
