enCoRe™ V CY7C643xx, enCoRe™ V LV CY7C604xx TRM, Document No. 001-32519 Rev *H
15
1.
Pin Information
This chapter lists, describes, and illustrates all pins and pinout configurations for the CY8C20X46A/46AS/96A/46L/
96LCY7C643xx and CY7C604xx enCoRe V devices. For up-to-date ordering, pinout, and packaging information, refer to the
individual enCoRe V device’s datasheet or go to
1.1
Pinouts
TheCY8C20X46A/46AS/96A/46L/96LCY7C643xx and CY7C604xx enCoRe V devices are available in a variety of packages.
Every
pin (labeled with a “P”), except for
, and XRES in the following tables and illustrations, is capable of Dig-
ital I/O.
1.1.1
CY7C60413 enCoRe V LV 16-Pin Part Pinout
,
Table 1-1.
16-Pin QFN/COL Part Pinout
Pin
No.
Type
Name
Description
Devices
Digital
Analog
1
IO
I
P2[5]
XTAL Out
2
IO
I
P2[3]
XTAL In
3
IOHR
I
P1[7]
I2C SCL, SPI SS
4
IOHR
I
P1[5]
I2C SDA, SPI MISO
5
IOHR
I
P1[3]
SPI CLK
6
IOHR
I
P1[1]
TC CLK
1
, I2C SCL, SPI MOSI
7
Power
Vss
Ground pin
8
IOHR
I
P1[0]
TC DATA
1
, I2C SDA, SPI CLK
9
IOHR
I
P1[2]
10
IOHR
I
P1[4]
EXTCLK
11
Input
XRES
Active high external reset with internal pull down
12
IOH
I
P0[4]
13
Power
Vdd
Power pin
14
IOH
I
P0[7]
15
IOH
I
P0[3]
16
IOH
I
P0[1]
Legend
A = Analog, I = Input, O = Output, H = 5-mA High Output Drive, R = Regulated Output Option.
1
These are the ISSP pins, which are not High-Z at POR.
P2[5]
P1[7]
P1[5]
P1
[3
]
P0
[3
]
P0
[7
]
Vdd
P0[4]
P1
[1
]
P1
[0
]
P1[2]
P2[3]
P1[4]
XRES
P0
[1
]
Vss
QFN
(Top View)
1
2
3
4
12
11
10
9
16
15
14
13
5
6
7
8
