enCoRe™ V CY7C643xx, enCoRe™ V LV CY7C604xx TRM, Document No. 001-32519 Rev *H
116
System Resets
16.3
Register Definitions
The following registers are associated with the enCoRe V System Resets and are listed in address order. Each register
description has an associated register table showing the bit structure for that register. The bits in the tables that are grayed
out are reserved bits and are not detailed in the register descriptions that follow. Always write reserved bits with a value of 0.
For a complete table of system reset registers, refer to the
“Summary Table of the System Resource Registers” on page 93
16.3.1
CPU_SCR1 Register
The System Status and Control Register 1 (CPU_SCR1)
conveys the status and control of events related to internal
resets and watchdog reset.
Bit 7: IRESS.
Internal Reset Status. This bit is a read-only
bit that determines if the booting process occurred more
than once.
When this bit is set, it indicates that the SROM SWBootRe-
set code executed more than once. If this bit is not set, the
SWBootReset executed only once. In either case, the
SWBootReset code does not allow execution from code
stored in flash until the M8C core is in a safe operating
mode with respect to supply voltage and flash operation.
There is no need for concern when this bit is set. It is pro-
vided for systems that may be sensitive to boot time, so that
they can determine if the normal one-pass boot time was
exceeded.
For more information on the SWBootReset code see the
Supervisory ROM (SROM) on page 32
Bit 4:3 SLIMO[1:0].
These bits set the IMO frequency
range. See the table ahead for more information. These
changes allow optimization of speed and power. The IMO
trim value must also be changed when SLIMO is changed
(see
When not in external clocking mode, the IMO is the source
for SYSCLK; therefore, when the speed of the IMO changes
so does SYSCLK.
Bit 0: IRAMDIS.
Initialize RAM Disable. This bit is a control
bit that is readable and writeable. The
for this
bit is ‘0’, which indicates that the maximum amount of SRAM
must be initialized on watchdog reset to a value of 00h.
When the bit is ‘1’, the minimum amount of SRAM is initial-
ized after a watchdog reset.
For additional information, refer to the
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Access
x,FEh
IRESS
SLIMO[1:0]
IRAMDIS
# : 0
Legend
x An “x” before the comma in the address field indicates that this register can be read or written to no matter what bank is used.
# Access is bit specific. Refer to the
Register Reference chapter on page 163
for additional information.
SLIMO
CY7C6xxxx
00
12
01
6
10
24
11
Reserved
