enCoRe™ V CY7C643xx, enCoRe™ V LV CY7C604xx TRM, Document No. 001-32519 Rev *H
210
x,FEh
21.3.43 CPU_SCR1
System Status and Control Register 1
This register is used to convey the status and control of events related to internal resets and watchdog reset.
In the table, note that reserved bits are grayed table cells and are not described in the bit description section. Reserved bits
must always be written with a value of ‘0’. For additional information, refer to the
Register Definitions on page 116
in the Sys-
tem Resets chapter.
7
IRESS
This bit is read only.
0
Boot phase only executed once.
1
Boot phase occurred multiple times.
4:3
SLIMO[1:0]
These bits set the frequency range for the IMO.
Note
When changing from the default setting, the
corresponding trim value must be loaded into the IMO_TR register for highest frequency accuracy.
SLIMO
CY7C6xxxx
00
12
01
6
10
24
11
Reserved
0
IRAMDIS
0
SRAM is initialized to 00h after POR, XRES, and WDR.
1
Addresses 03h - D7h of SRAM Page 0 are not modified by WDR.
Individual Register Names and Addresses:
x,FEh
CPU_SCR1: x,FEh
7
6
5
4
3
2
1
0
Access : POR
R : 0
RW : 0
RW : 0
Bit Name
IRESS
SLIMO[1:0]
IRAMDIS
Bit
Name
Description
