Cypress enCoRe V CY7C643 Series, Technical Reference Manual

Page: 22 / 257

enCoRe™ V CY7C643xx, enCoRe™ V LV CY7C604xx TRM, Document No. 001-32519 Rev *H 22
Pin Information
1.1.8 48-Pin SSOP
Table 1-8. Pin Definitions – CY8C20536A, CY8C20546A, and CY8C20566A PSoC Device
Pi
n N
o
.
Dig
it
al
Analo
g
Name
Desc
ri
pti
o
n
CY8C20536A, CY8C20546A, and CY8C20566A
PSoC Device
1 IOH I P0[7]
2 IOH I P0[5]
3 IOH I P0[3] Integrating Input
4 IOH I P0[1] Integrating Input
5 I/O I P2[7]
6 I/O I P2[5] XTAL Out
7 I/O I P2[3] XTAL In
8 I/O I P2[1]
9 NC No connection
10 NC No connection
11 I/O I P4[3]
12 I/O I P4[1]
13 NC No connection
14 I/O I P3[7]
15 I/O I P3[5]
16 I/O I P3[3]
17 I/O I P3[1]
18 NC No connection
19 NC No connection
20 IOHR I P1[7]
I
2
C SCL, SPI SS
21 IOHR I P1[5]
I
2
C SDA, SPI MISO
22 IOHR I P1[3] SPI CLK
23 IOHR I P1[1]
ISSP CLK
1
, I
2
C SCL, SPI MOSI
24 V
SS
Ground Pin
25 IOHR I P1[0]
ISSP DATA
1
, I
2
C SDA, SPI CLK
2
26 IOHR I P1[2]
27 IOHR I P1[4] Optional external clock input
(
EXT CLK)
28 IOHR I P1[6]
29 NC No connection
30 NC No connection
31 NC No connection
32 NC No connection
Pi
n
No.
Digit
a
l
Analog
Nam
e
De
scr
ipti
on
33 NC No connection 41 I/O I P2[2]
34 NC No connection 42 I/O I P2[4]
35 XRES Active high external reset with internal
pull-down 43 I/O I P2[6]
36 I/O I P3[0] 44 IOH I P0[0]
37 I/O I P3[2] 45 IOH I P0[2]
38 I/O I P3[4] 46 IOH I P0[4]
39 I/O I P3[6] 47 IOH I P0[6]
40 I/O I P2[0] 48 Power V
DD
Power Pin
Legend A = Analog, I = Input, O = Output, NC = No Connection, H = 5 mA High Output Drive, R = Regulated Output Option.
1
On power-up, the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The
SCL(P1[1])line drives resistive low for 512 sleep clock cycles and both the pins transition to high-impedance state. On reset, after XRES deas-
serts, the SDA and the SCL lines drive resistive low for 8 sleep clock cycles and transition to high-impedance state. Hence, during power-up or
reset event, P1[1] and P1[0] may disturb the I2C bus. Use alternate pins if you encounter issues.
2
Alternate SPI clock.
P0[7]
Vdd
P0[5]
P0[6]
P0[3]
P0[4]
0[1] P0[2]
P2[7]
P0[0]
P2[5]
P2[6]
P2[3]
P2[4]
P2[1]
P2[2]
NC
P2[0]
NC
P3[6]
P4[3]
P3[4]
P4[1]
P3[2]
NC
P3[0]
P3[7]
XRES
P3[5]
NC
P3[3]
NC
P3[1] NC
NC
NC
NC
NC
P1[7]
NC
P1[5 ]
P1[6]
P1[3]
P1[4]
P1[1] P1[2]
Vss P1[0]
P
SSOP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
43
44
42
40
41
39
38
37
36
35
33
34
32
31
30
29
28
27
26
25