Cypress enCoRe V CY7C643 Series, Technical Reference Manual

Page: 21 / 257

enCoRe™ V CY7C643xx, enCoRe™ V LV CY7C604xx TRM, Document No. 001-32519 Rev *H 21
Pin Information
1.1.7 32-Pin QFN (with USB)
Table 1-7. Pin Definitions – CY8C20496A/L PSoC Device
2
Pin
No.
Type
Name Description
CY8C20496A/L PSoC Device
Digital Analog
1 IOH I P0[1] Integrating Input
2 I/O I P2[5] XTAL Out
3 I/O I P2[3] XTAL In
4 I/O I P2[1]
5 IOHR I P1[7]
I
2
C SCL, SPI SS
6 IOHR I P1[5]
I
2
C SDA, SPI MISO
7 IOHR I P1[3] SPI CLK
8 IOHR I P1[1]
ISSP CLK
1
, I
2
C SCL, SPI MOSI
9 Power V
SS
Ground Pin
10 I D+ USB D+
11 I D– USB D–
12 Power V
DD
Power pin
13 IOHR I P1[0]
ISSP DATA
1
, I
2
C SDA, SPI CLKI
3
14 IOHR I P1[2]
15 IOHR I P1[4] Optional external clock input (EXTCLK)
16 IOHR I P1[6]
17 Input XRES Active high external reset with internal pull-down
18 I/O I P3[0]
19 I/O I P3[2]
20 I/O I P2[0]
21 I/O I P2[2]
22 I/O I P2[4]
23 I/O I P2[6]
24 IOH I P0[0]
25 IOH I P0[2]
26 IOH I P0[4]
27 IOH I P0[6]
28 Power V
DD
Power Pin
29 IOH I P0[7]
30 IOH I P0[5]
31 IOH I P0[3] Integrating Input
32 Power V
SS
Ground Pin
Legend
A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output.
1
On power-up, the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The
SCL(P1[1])line drives resistive low for 512 sleep clock cycles and both the pins transition to high-impedance state. On reset, after XRES deas-
serts, the SDA and the SCL lines drive resistive low for 8 sleep clock cycles and transition to high-impedance state. Hence, during power-up or
reset event, P1[1] and P1[0] may disturb the I2C bus. Use alternate pins if you encounter issues.
2
The center pad on the QFN package must be connected to ground (Vss) for best mechanical, thermal, and electrical performance. If not con-
nected to ground, it must be electrically floated and not connected to any other signal.
3
Alternate SPI clock.
P0[1]
P2[5]
P2[3]
P2[1]
P1[7]
P1[5]
QFN
(Top View)
9
10 11 12 13 14 15 16
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
32 31 30 29 28 27 26 25
Vs
s
P0
[3
]
P0
[7
]
Vd
d
P0
[6
]
P0
[4
]
P0
[2
]
P1[3]
P1[1]
P0[0]
P2[6]
P3[0]
XRES
Vs
s
US
B
P
H
Y
, D
+
U
SB
D–
Vd
d
P1[
0
]
P1[
2
]
P1[
4
]
P1[
6
]
P2[4]
P2[2]
P2[0]
P3[2]
P0
[5
]