enCoRe™ V CY7C643xx, enCoRe™ V LV CY7C604xx TRM, Document No. 001-32519 Rev *H
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16. System Resets
This chapter discusses the System Resets and their associated registers. enCoRe V devices support several types of resets.
The various resets are designed to provide error-free operation during power up for any voltage ramping profile, to allow user-
supplied external reset, and to provide recovery from errant code operation. For a complete table of the System Reset regis-
ters, refer to the
Summary Table of the System Resource Registers on page 93
. For a quick reference of all enCoRe V regis-
ters in address order, refer to the
Register Reference chapter on page 163
16.1
Architectural Description
When reset is initiated, all registers are restored to their
default states. In the
, this is indicated by the POR row in the register
tables and elsewhere it is indicated in the Access column
values on the right side of the colon, in the register tables.
Minor exceptions are explained ahead.
The following types of resets occur in the enCoRe V device:
■
Power-on-Reset (POR).
This occurs at low supply volt-
age and is comprised of multiple sources.
■
External Reset (XRES).
This active high reset is driven
into the enCoRe V device on parts that contain an XRES
pin.
■
Watchdog Reset (WDR).
This optional reset occurs
when the watchdog timer expires before being cleared
by user firmware. Watchdog resets default to off.
■
Internal Reset (IRES).
This occurs during the boot
sequence if the SROM code determines that flash reads
are invalid.
The occurrence of a reset is recorded in the Status and Con-
trol registers (CPU_SCR0 for POR, XRES, and WDR) or in
the System Status and Control Register 1 (CPU_SCR1 for
IRESS). Firmware can interrogate these registers to deter-
mine the cause of a reset.
16.2
Pin Behavior During Reset
POR and XRES cause toggling on two GPIO pins, P1[0] and
P1[1], as described ahead and illustrated in
and
. This allows programmers to synchronize with
the enCoRe V device. All other GPIO pins are placed in a
high-impedance state during and immediately following
reset.
16.2.1
GPIO Behavior on Power Up
At power-up, the internal POR causes P1[0] to initially drive
a strong high (1) while P1[1] drives a resistive low (0). After
256 sleep oscillator cycles (approximately 8 ms), the P1[0]
signal transitions to a resistive low state. After an additional
256 sleep oscillator clocks, both pins transition to a high-
impedance state and normal CPU operation begins. This is
illustrated in the following figure.
Figure 16-1. P1[1:0] Behavior on Power Up
Internal
Reset
P1[0]
P1[1]
HiZ
HiZ
Vdd
POR Trip
Point
S1
R0
R0
R0
T1
T2
T1 = T2 = 256 Sleep Clock Cycles
(approximately 8 ms)
