Cypress enCoRe V CY7C643 Series, Technical Reference Manual

Page: 113 / 257

enCoRe™ V CY7C643xx, enCoRe™ V LV CY7C604xx TRM, Document No. 001-32519 Rev *H 113
I
2
C Slave
15.4.4 Slave Stall Timing
When a byte complete interrupt occurs, the enCoRe V device firmware must respond with a write to the I2C_SCR Register to
continue the transfer (or terminate the transfer). The interrupt occurs two clocks after the rising edge of SCL_IN (see Status
Timing on page 112 ). As illustrated in Figure 15-10 , firmware has until one clock after the falling edge of SCL_IN to write to
the I2C_SCR Register ; otherwise, a stall occurs. After stalled, the I/O write releases the stall. The setup time between data
output and the next rising edge of SCL is always N-1 clocks.
Figure 15-10. Slave Stall Timing
SCL
CLOCK
SCL_IN
(Synchronized)
SDA_OUT
I/O WRITE
1 Clocks N-1 Clocks
STALL No STALL
SCL_OUT