enCoRe™ V CY7C643xx, enCoRe™ V LV CY7C604xx TRM, Document No. 001-32519 Rev *H
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11. Sleep and Watchdog
This chapter discusses the Sleep and Watchdog operations and their associated registers. For a complete table of the Sleep
and Watchdog registers, refer to the
Summary Table of the Core Registers on page 24
. For a quick reference of all enCoRe V
registers in address order, refer to the
Register Reference chapter on page 163
11.1
Architectural Description
Device components that are involved in Sleep and Watchdog operation are the selected 32-kHz clock, the wakeup timer, the
Sleep bit in the CPU_SCR0 register, the sleep circuit (to sequence going into and coming out of sleep), the bandgap refresh
circuit (to periodically refresh the reference voltage during sleep), and the
.
Figure 11-1. Sleep Controller Architecture
Outputs
32 kHz CLK
Control Inputs
OSC_SCR0
CPU_SCR0
Wakeup Timer
Sleep Control Logic
Register Decode Logic
(SLP_CFG, SLP_CFG2,
SLP_CFG3, Internal
Configuration Registers)
Sleep Timer
CPU Hold
Off
IMO
CLK
