enCoRe™ V CY7C643xx, enCoRe™ V LV CY7C604xx TRM, Document No. 001-32519 Rev *H
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Interrupt Controller
7. Execution resumes at the next instruction, after the
instruction that occurred before the interrupt. However, if
there are more pending interrupts, the subsequent inter-
rupts are processed before the next normal program
instruction.
Interrupt Latency.
The time between the assertion of an
enabled interrupt and the start of its ISR is calculated using
this equation:
Equation 1
For example, if the 5-cycle
JMP
instruction is executing
when an interrupt becomes active, the total number of CPU
clock cycles before the ISR begins is:
Equation 2
In this example, at 24 MHz, 25 clock cycles take 1.042
s.
Interrupt Priority.
Interrupt priorities come into consider-
ation when more than one interrupt is pending during the
same instruction cycle. In this case, the Priority Encoder
(see
) generates an interrupt vector for the high-
est priority pending interrupt.
5.1.1
Posted versus Pending Interrupts
An interrupt is posted when its interrupt conditions occur.
This results in the flip-flop in
clocking in a 1. The
interrupt remains posted until the interrupt is taken or until it
is cleared by writing to the appropriate INT_CLRx register.
A posted interrupt is not pending unless it is enabled by set-
ting its interrupt mask bit (in the appropriate INT_MSKx reg-
ister). All pending interrupts are processed by the Priority
Encoder to determine the highest priority interrupt taken by
the M8C if the Global Interrupt Enable bit is set in the
CPU_F register.
Disabling an interrupt by clearing its interrupt mask bit (in
the INT_MSKx register) does not clear a posted interrupt,
nor does it prevent an interrupt from posting. It simply pre-
vents a posted interrupt from becoming pending.
It is especially important to understand the functionality of
clearing posted interrupts, if the configuration of the enCoRe
V device is changed by the application.
For example, if a block has a posted interrupt when it is
enabled and then disabled, the posted interrupt remains.
Therefore, it is good practice to use the INT_CLR register to
clear posted interrupts before enabling or re-enabling a
block.
5.2
Application Overview
The interrupt controller and its associated registers allow the
user’s code to respond to an interrupt from almost every
functional block in enCoRe V devices. Interrupts for all the
digital blocks and each of the analog columns are available,
as well as interrupts for supply voltage, sleep, variable
clocks, and a general GPIO (pin) interrupt.
The registers associated with the interrupt controller allow
the disabling of interrupts either globally or individually. The
registers also provide a mechanism by which a user can
all pending and posted interrupts or clear individual
posted or pending interrupts. A
mechanism is pro-
vided to set individual interrupts. Setting an interrupt by way
of software is very useful during code development, when
one may not have the complete hardware system necessary
to generate a real interrupt.
The following table lists the interrupts and priorities that are
available in the enCoRe V devices.
Latency =
Time for current instruction to
Time for M8C to change program counter to interrupt a
Time for LJMP instruction in interrupt table to execute.
(1 to 5 cycles for JMP to finish) +
(13 cycles for interrupt routine) +
(7 cycles for LJMP) = 21 to 25 cycles.
Table 5-1. Device Interrupts
Interrupt Priority
Interrupt
Address
Interrupt Name
0 (Highest)
0000h
Reset
1
0004h
Supply voltage monitor
2
0008h
Reserved
3
000Ch
Reserved
4
0010h
Timer0
5
0014h
GPIO
6
0018h
SPI
7
001Ch
I2C
8
0020h
Sleep Timer
9
0024h
Timer1
10
0028h
Timer2
