Cypress enCoRe V CY7C643 Series, Technical Reference Manual

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enCoRe™ V CY7C643xx, enCoRe™ V LV CY7C604xx TRM, Document No. 001-32519 Rev *H 23
Section B: enCoRe V Core
The enCoRe V Core section discusses the core components of an enCoRe V device with a base part number of CY7C643xx
and CY7C604xx and the registers associated with those components. The core section covers the heart of the enCoRe V
device, which includes the M8C
microcontroller
; SROM, interrupt controller, GPIO, and
SRAM
paging; multiple clock
sources such as IMO and ILO; and sleep and watchdog functionality. This section includes these chapters:
■
CPU Core (M8C) on page 26 .
■
Supervisory ROM (SROM) on page 32 .
■
RAM Paging on page 38 .
■
Interrupt Controller on page 44 .
■
General-Purpose I/O (GPIO) on page 52 .
■
Internal Main Oscillator (IMO) on page 67 .
■
Internal Low-speed Oscillator (ILO) on page 72 .
■
External Crystal Oscillator (ECO), on page 74
■
Sleep and Watchdog on page 78 .
Top-Level Core Architecture
This figure displays the top-level architecture of the enCoRe V core. Each component of the figure is discussed at length in
this section.
enCoRe V Core Block Diagram
1K, 2K
SRAM
Interrupt
Controller
Sleep and
Watchdog
Multiple Clock Sources
Internal Low Speed Oscillator (ILO)
6/12/24 MHz Internal Main Oscillator (IMO)
CORE
CPU Core (M8C)
Supervisory ROM (SROM)
8K, 16K, 32K Flash
Nonvolatile Memory
SYSTEM BUS
Port 3 Port 2 Port 1 Port 0
1.8/2.5/3V
LDO
PWRSYS
(Regulator)
Port 4