enCoRe™ V CY7C643xx, enCoRe™ V LV CY7C604xx TRM, Document No. 001-32519 Rev *H
192
0,D5h
21.3.29 MVW_PP
MVI Write Page Pointer Register
This register is used to set the effective SRAM page for MVI write memory accesses in a multi-SRAM page enCoRe V device.
This register is only used when a device has more than one page of SRAM. In the table, note that reserved bits are grayed
table cells and are not described in the bit description section. Reserved bits must always be written with a value of ‘0’. For
additional information, refer to the
Register Definitions on page 41
in the RAM Paging chapter
.
2:0
Page Bits[2:0]
Bits determine which SRAM page an MVI Write instruction operates on.
000b
SRAM Page 0
001b
SRAM Page 1
010b
SRAM Page 2
011b
SRAM Page 3
100b
SRAM Page 4
101b
SRAM Page 5
110b
SRAM Page 6
111b
SRAM Page 7
Individual Register Names and Addresses:
0,D5h
MVW_PP : 0,D5h
7
6
5
4
3
2
1
0
Access : POR
RW : 0
Bit Name
Page Bits[2:0]
Bit
Name
Description
